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Iglesias" To: qemu-devel@nongnu.org Subject: [PATCH v2 1/1] target/arm: Drop access_el3_aa32ns() Date: Mon, 4 May 2020 16:21:25 +0200 Message-Id: <20200504142125.31180-2-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200504142125.31180-1-edgar.iglesias@gmail.com> References: <20200504142125.31180-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::141; envelope-from=edgar.iglesias@gmail.com; helo=mail-lf1-x141.google.com X-detected-operating-system: by eggs.gnu.org: No matching host in p0f cache. That's all we know. X-Spam_score_int: 13 X-Spam_score: 1.3 X-Spam_bar: + X-Spam_report: (1.3 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, FSL_HELO_FAKE=3.399, RCVD_IN_DNSWL_NONE=-0.0001, SPF_PASS=-0.001, URIBL_BLOCKED=0.001 autolearn=_AUTOLEARN X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, richard.henderson@linaro.org, edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Calling access_el3_aa32ns() works for AArch32 only cores but it does not handle 32-bit EL2 on top of 64-bit EL3 for mixed 32/64-bit cores. Merge access_el3_aa32ns_aa64any() into access_el3_aa32ns() and only use the latter. Fixes: 68e9c2fe65 ("target-arm: Add VTCR_EL2") Reported-by: Laurent Desnogues Signed-off-by: Edgar E. Iglesias --- target/arm/helper.c | 30 +++++++----------------------- 1 file changed, 7 insertions(+), 23 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index dfefb9b3d9..7d21bf1cc7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -502,35 +502,19 @@ void init_cpreg_list(ARMCPU *cpu) } =20 /* - * Some registers are not accessible if EL3.NS=3D0 and EL3 is using AArch3= 2 but - * they are accessible when EL3 is using AArch64 regardless of EL3.NS. - * - * access_el3_aa32ns: Used to check AArch32 register views. - * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views. + * Some registers are not accessible from AArch32 EL3 if SCR.NS =3D=3D 0. */ static CPAccessResult access_el3_aa32ns(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { - bool secure =3D arm_is_secure_below_el3(env); - - assert(!arm_el_is_aa64(env, 3)); - if (secure) { + if (!is_a64(env) && arm_current_el(env) =3D=3D 3 && + arm_is_secure_below_el3(env)) { return CP_ACCESS_TRAP_UNCATEGORIZED; } return CP_ACCESS_OK; } =20 -static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env, - const ARMCPRegInfo *ri, - bool isread) -{ - if (!arm_el_is_aa64(env, 3)) { - return access_el3_aa32ns(env, ri, isread); - } - return CP_ACCESS_OK; -} - /* Some secure-only AArch32 registers trap to EL3 if used from * Secure EL1 (but are just ordinary UNDEF in other non-EL3 contexts). * Note that an access from Secure EL1 can only happen if EL3 is AArch64. @@ -5236,7 +5220,7 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] =3D= { .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "VTCR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns_aa64any, + .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "VTTBR", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 6, .crm =3D 2, @@ -5284,7 +5268,7 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] =3D= { .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "HPFAR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 4, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns_aa64any, + .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "HSTR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 3, @@ -7626,12 +7610,12 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo vpidr_regs[] =3D { { .name =3D "VPIDR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 = =3D 0, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns_aa64= any, + .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->midr, .fieldoffset =3D offsetof(CPUARMState, cp15.vpidr_el2) }, { .name =3D "VMPIDR_EL2", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 = =3D 5, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns_aa64= any, + .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, .type =3D ARM_CP_NO_RAW, .writefn =3D arm_cp_write_ignore, .readfn =3D mpidr_read= }, REGINFO_SENTINEL --=20 2.20.1