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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 07/39] target/arm: Use correct variable for setting 'max' cpu's
ID_AA64DFR0
Date: Mon, 4 May 2020 13:32:37 +0100
Message-Id: <20200504123309.3808-8-peter.maydell@linaro.org>
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In aarch64_max_initfn() we update both 32-bit and 64-bit ID
registers. The intended pattern is that for 64-bit ID registers we
use FIELD_DP64 and the uint64_t 't' register, while 32-bit ID
registers use FIELD_DP32 and the uint32_t 'u' register. For
ID_AA64DFR0 we accidentally used 'u', meaning that the top 32 bits of
this 64-bit ID register would end up always zero. Luckily at the
moment that's what they should be anyway, so this bug has no visible
effects.
Use the right-sized variable.
Fixes: 3bec78447a958d481991
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Reviewed-by: Philippe Mathieu-Daud=C3=A9 <f4bug@amsat.org>
Message-id: 20200423110915.10527-1-peter.maydell@linaro.org
---
target/arm/cpu64.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index e232c0ea12c..9bdf75b1abb 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -710,9 +710,9 @@ static void aarch64_max_initfn(Object *obj)
u =3D FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */
cpu->isar.id_mmfr4 =3D u;
=20
- u =3D cpu->isar.id_aa64dfr0;
- u =3D FIELD_DP64(u, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
- cpu->isar.id_aa64dfr0 =3D u;
+ t =3D cpu->isar.id_aa64dfr0;
+ t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */
+ cpu->isar.id_aa64dfr0 =3D t;
=20
u =3D cpu->isar.id_dfr0;
u =3D FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */
--=20
2.20.1