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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 38/39] target/arm: Convert Neon 3-reg-same VMUL, VMLA, VMLS,
VSHL to decodetree
Date: Mon, 4 May 2020 13:33:08 +0100
Message-Id: <20200504123309.3808-39-peter.maydell@linaro.org>
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Convert the Neon VMUL, VMLA, VMLS and VSHL insns in the
3-reg-same grouping to decodetree.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-20-peter.maydell@linaro.org
---
target/arm/neon-dp.decode | 9 +++++++
target/arm/translate-neon.inc.c | 44 +++++++++++++++++++++++++++++++++
target/arm/translate.c | 28 +++------------------
3 files changed, 56 insertions(+), 25 deletions(-)
diff --git a/target/arm/neon-dp.decode b/target/arm/neon-dp.decode
index ab59b349aaa..ec3a92fe753 100644
--- a/target/arm/neon-dp.decode
+++ b/target/arm/neon-dp.decode
@@ -65,6 +65,9 @@ VCGT_U_3s 1111 001 1 0 . .. .... .... 0011 . . . 0=
.... @3same
VCGE_S_3s 1111 001 0 0 . .. .... .... 0011 . . . 1 .... @3same
VCGE_U_3s 1111 001 1 0 . .. .... .... 0011 . . . 1 .... @3same
=20
+VSHL_S_3s 1111 001 0 0 . .. .... .... 0100 . . . 0 .... @3same
+VSHL_U_3s 1111 001 1 0 . .. .... .... 0100 . . . 0 .... @3same
+
VMAX_S_3s 1111 001 0 0 . .. .... .... 0110 . . . 0 .... @3same
VMAX_U_3s 1111 001 1 0 . .. .... .... 0110 . . . 0 .... @3same
VMIN_S_3s 1111 001 0 0 . .. .... .... 0110 . . . 1 .... @3same
@@ -75,3 +78,9 @@ VSUB_3s 1111 001 1 0 . .. .... .... 1000 . . . 0=
.... @3same
=20
VTST_3s 1111 001 0 0 . .. .... .... 1000 . . . 1 .... @3same
VCEQ_3s 1111 001 1 0 . .. .... .... 1000 . . . 1 .... @3same
+
+VMLA_3s 1111 001 0 0 . .. .... .... 1001 . . . 0 .... @3same
+VMLS_3s 1111 001 1 0 . .. .... .... 1001 . . . 0 .... @3same
+
+VMUL_3s 1111 001 0 0 . .. .... .... 1001 . . . 1 .... @3same
+VMUL_p_3s 1111 001 1 0 . .. .... .... 1001 . . . 1 .... @3same
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in=
c.c
index 854ab70cd79..50b77b6d714 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -631,6 +631,7 @@ DO_3SAME_NO_SZ_3(VMAX_S, tcg_gen_gvec_smax)
DO_3SAME_NO_SZ_3(VMAX_U, tcg_gen_gvec_umax)
DO_3SAME_NO_SZ_3(VMIN_S, tcg_gen_gvec_smin)
DO_3SAME_NO_SZ_3(VMIN_U, tcg_gen_gvec_umin)
+DO_3SAME_NO_SZ_3(VMUL, tcg_gen_gvec_mul)
=20
#define DO_3SAME_CMP(INSN, COND) \
static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \
@@ -668,3 +669,46 @@ DO_3SAME_GVEC4(VQADD_S, sqadd_op)
DO_3SAME_GVEC4(VQADD_U, uqadd_op)
DO_3SAME_GVEC4(VQSUB_S, sqsub_op)
DO_3SAME_GVEC4(VQSUB_U, uqsub_op)
+
+static void gen_VMUL_p_3s(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
+ uint32_t rm_ofs, uint32_t oprsz, uint32_t maxsz)
+{
+ tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, oprsz, maxsz,
+ 0, gen_helper_gvec_pmul_b);
+}
+
+static bool trans_VMUL_p_3s(DisasContext *s, arg_3same *a)
+{
+ if (a->size !=3D 0) {
+ return false;
+ }
+ return do_3same(s, a, gen_VMUL_p_3s);
+}
+
+#define DO_3SAME_GVEC3_NO_SZ_3(INSN, OPARRAY) \
+ static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \
+ uint32_t rn_ofs, uint32_t rm_ofs, \
+ uint32_t oprsz, uint32_t maxsz) \
+ { \
+ tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, \
+ oprsz, maxsz, &OPARRAY[vece]); \
+ } \
+ DO_3SAME_NO_SZ_3(INSN, gen_##INSN##_3s)
+
+
+DO_3SAME_GVEC3_NO_SZ_3(VMLA, mla_op)
+DO_3SAME_GVEC3_NO_SZ_3(VMLS, mls_op)
+
+#define DO_3SAME_GVEC3_SHIFT(INSN, OPARRAY) \
+ static void gen_##INSN##_3s(unsigned vece, uint32_t rd_ofs, \
+ uint32_t rn_ofs, uint32_t rm_ofs, \
+ uint32_t oprsz, uint32_t maxsz) \
+ { \
+ /* Note the operation is vshl vd,vm,vn */ \
+ tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, \
+ oprsz, maxsz, &OPARRAY[vece]); \
+ } \
+ DO_3SAME(INSN, gen_##INSN##_3s)
+
+DO_3SAME_GVEC3_SHIFT(VSHL_S, sshl_op)
+DO_3SAME_GVEC3_SHIFT(VSHL_U, ushl_op)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 13ce1a5fc1d..025747c0bd4 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -4848,31 +4848,6 @@ static int disas_neon_data_insn(DisasContext *s, uin=
t32_t insn)
}
return 1;
=20
- case NEON_3R_VMUL: /* VMUL */
- if (u) {
- /* Polynomial case allows only P8. */
- if (size !=3D 0) {
- return 1;
- }
- tcg_gen_gvec_3_ool(rd_ofs, rn_ofs, rm_ofs, vec_size, vec_s=
ize,
- 0, gen_helper_gvec_pmul_b);
- } else {
- tcg_gen_gvec_mul(size, rd_ofs, rn_ofs, rm_ofs,
- vec_size, vec_size);
- }
- return 0;
-
- case NEON_3R_VML: /* VMLA, VMLS */
- tcg_gen_gvec_3(rd_ofs, rn_ofs, rm_ofs, vec_size, vec_size,
- u ? &mls_op[size] : &mla_op[size]);
- return 0;
-
- case NEON_3R_VSHL:
- /* Note the operation is vshl vd,vm,vn */
- tcg_gen_gvec_3(rd_ofs, rm_ofs, rn_ofs, vec_size, vec_size,
- u ? &ushl_op[size] : &sshl_op[size]);
- return 0;
-
case NEON_3R_VADD_VSUB:
case NEON_3R_LOGIC:
case NEON_3R_VMAX:
@@ -4882,6 +4857,9 @@ static int disas_neon_data_insn(DisasContext *s, uint=
32_t insn)
case NEON_3R_VCGE:
case NEON_3R_VQADD:
case NEON_3R_VQSUB:
+ case NEON_3R_VMUL:
+ case NEON_3R_VML:
+ case NEON_3R_VSHL:
/* Already handled by decodetree */
return 1;
}
--=20
2.20.1