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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 30/39] target/arm: Convert Neon load/store multiple structures
to decodetree
Date: Mon, 4 May 2020 13:33:00 +0100
Message-Id: <20200504123309.3808-31-peter.maydell@linaro.org>
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Convert the Neon "load/store multiple structures" insns to decodetree.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-12-peter.maydell@linaro.org
---
target/arm/neon-ls.decode | 7 ++
target/arm/translate-neon.inc.c | 124 ++++++++++++++++++++++++++++++++
target/arm/translate.c | 91 +----------------------
3 files changed, 133 insertions(+), 89 deletions(-)
diff --git a/target/arm/neon-ls.decode b/target/arm/neon-ls.decode
index 2b16c9256df..dd03d5a37bd 100644
--- a/target/arm/neon-ls.decode
+++ b/target/arm/neon-ls.decode
@@ -27,3 +27,10 @@
# 0b1111_1001_xxx0_xxxx_xxxx_xxxx_xxxx_xxxx
# This file works on the A32 encoding only; calling code for T32 has to
# transform the insn into the A32 version first.
+
+%vd_dp 22:1 12:4
+
+# Neon load/store multiple structures
+
+VLDST_multiple 1111 0100 0 . l:1 0 rn:4 .... itype:4 size:2 align:2 rm:4 \
+ vd=3D%vd_dp
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in=
c.c
index b06542b8b83..966c0d92012 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -274,3 +274,127 @@ static bool trans_VFML_scalar(DisasContext *s, arg_VF=
ML_scalar *a)
gen_helper_gvec_fmlal_idx_a32);
return true;
}
+
+static struct {
+ int nregs;
+ int interleave;
+ int spacing;
+} const neon_ls_element_type[11] =3D {
+ {1, 4, 1},
+ {1, 4, 2},
+ {4, 1, 1},
+ {2, 2, 2},
+ {1, 3, 1},
+ {1, 3, 2},
+ {3, 1, 1},
+ {1, 1, 1},
+ {1, 2, 1},
+ {1, 2, 2},
+ {2, 1, 1}
+};
+
+static void gen_neon_ldst_base_update(DisasContext *s, int rm, int rn,
+ int stride)
+{
+ if (rm !=3D 15) {
+ TCGv_i32 base;
+
+ base =3D load_reg(s, rn);
+ if (rm =3D=3D 13) {
+ tcg_gen_addi_i32(base, base, stride);
+ } else {
+ TCGv_i32 index;
+ index =3D load_reg(s, rm);
+ tcg_gen_add_i32(base, base, index);
+ tcg_temp_free_i32(index);
+ }
+ store_reg(s, rn, base);
+ }
+}
+
+static bool trans_VLDST_multiple(DisasContext *s, arg_VLDST_multiple *a)
+{
+ /* Neon load/store multiple structures */
+ int nregs, interleave, spacing, reg, n;
+ MemOp endian =3D s->be_data;
+ int mmu_idx =3D get_mem_index(s);
+ int size =3D a->size;
+ TCGv_i64 tmp64;
+ TCGv_i32 addr, tmp;
+
+ if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist */
+ if (!dc_isar_feature(aa32_simd_r32, s) && (a->vd & 0x10)) {
+ return false;
+ }
+ if (a->itype > 10) {
+ return false;
+ }
+ /* Catch UNDEF cases for bad values of align field */
+ switch (a->itype & 0xc) {
+ case 4:
+ if (a->align >=3D 2) {
+ return false;
+ }
+ break;
+ case 8:
+ if (a->align =3D=3D 3) {
+ return false;
+ }
+ break;
+ default:
+ break;
+ }
+ nregs =3D neon_ls_element_type[a->itype].nregs;
+ interleave =3D neon_ls_element_type[a->itype].interleave;
+ spacing =3D neon_ls_element_type[a->itype].spacing;
+ if (size =3D=3D 3 && (interleave | spacing) !=3D 1) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ /* For our purposes, bytes are always little-endian. */
+ if (size =3D=3D 0) {
+ endian =3D MO_LE;
+ }
+ /*
+ * Consecutive little-endian elements from a single register
+ * can be promoted to a larger little-endian operation.
+ */
+ if (interleave =3D=3D 1 && endian =3D=3D MO_LE) {
+ size =3D 3;
+ }
+ tmp64 =3D tcg_temp_new_i64();
+ addr =3D tcg_temp_new_i32();
+ tmp =3D tcg_const_i32(1 << size);
+ load_reg_var(s, addr, a->rn);
+ for (reg =3D 0; reg < nregs; reg++) {
+ for (n =3D 0; n < 8 >> size; n++) {
+ int xs;
+ for (xs =3D 0; xs < interleave; xs++) {
+ int tt =3D a->vd + reg + spacing * xs;
+
+ if (a->l) {
+ gen_aa32_ld_i64(s, tmp64, addr, mmu_idx, endian | size=
);
+ neon_store_element64(tt, n, size, tmp64);
+ } else {
+ neon_load_element64(tmp64, tt, n, size);
+ gen_aa32_st_i64(s, tmp64, addr, mmu_idx, endian | size=
);
+ }
+ tcg_gen_add_i32(addr, addr, tmp);
+ }
+ }
+ }
+ tcg_temp_free_i32(addr);
+ tcg_temp_free_i32(tmp);
+ tcg_temp_free_i64(tmp64);
+
+ gen_neon_ldst_base_update(s, a->rm, a->rn, nregs * interleave * 8);
+ return true;
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index e269642a480..be56cbb0614 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -3214,45 +3214,19 @@ static void gen_neon_trn_u16(TCGv_i32 t0, TCGv_i32 =
t1)
}
=20
=20
-static struct {
- int nregs;
- int interleave;
- int spacing;
-} const neon_ls_element_type[11] =3D {
- {1, 4, 1},
- {1, 4, 2},
- {4, 1, 1},
- {2, 2, 2},
- {1, 3, 1},
- {1, 3, 2},
- {3, 1, 1},
- {1, 1, 1},
- {1, 2, 1},
- {1, 2, 2},
- {2, 1, 1}
-};
-
/* Translate a NEON load/store element instruction. Return nonzero if the
instruction is invalid. */
static int disas_neon_ls_insn(DisasContext *s, uint32_t insn)
{
int rd, rn, rm;
- int op;
int nregs;
- int interleave;
- int spacing;
int stride;
int size;
int reg;
int load;
- int n;
int vec_size;
- int mmu_idx;
- MemOp endian;
TCGv_i32 addr;
TCGv_i32 tmp;
- TCGv_i32 tmp2;
- TCGv_i64 tmp64;
=20
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
return 1;
@@ -3274,70 +3248,9 @@ static int disas_neon_ls_insn(DisasContext *s, uint3=
2_t insn)
rn =3D (insn >> 16) & 0xf;
rm =3D insn & 0xf;
load =3D (insn & (1 << 21)) !=3D 0;
- endian =3D s->be_data;
- mmu_idx =3D get_mem_index(s);
if ((insn & (1 << 23)) =3D=3D 0) {
- /* Load store all elements. */
- op =3D (insn >> 8) & 0xf;
- size =3D (insn >> 6) & 3;
- if (op > 10)
- return 1;
- /* Catch UNDEF cases for bad values of align field */
- switch (op & 0xc) {
- case 4:
- if (((insn >> 5) & 1) =3D=3D 1) {
- return 1;
- }
- break;
- case 8:
- if (((insn >> 4) & 3) =3D=3D 3) {
- return 1;
- }
- break;
- default:
- break;
- }
- nregs =3D neon_ls_element_type[op].nregs;
- interleave =3D neon_ls_element_type[op].interleave;
- spacing =3D neon_ls_element_type[op].spacing;
- if (size =3D=3D 3 && (interleave | spacing) !=3D 1) {
- return 1;
- }
- /* For our purposes, bytes are always little-endian. */
- if (size =3D=3D 0) {
- endian =3D MO_LE;
- }
- /* Consecutive little-endian elements from a single register
- * can be promoted to a larger little-endian operation.
- */
- if (interleave =3D=3D 1 && endian =3D=3D MO_LE) {
- size =3D 3;
- }
- tmp64 =3D tcg_temp_new_i64();
- addr =3D tcg_temp_new_i32();
- tmp2 =3D tcg_const_i32(1 << size);
- load_reg_var(s, addr, rn);
- for (reg =3D 0; reg < nregs; reg++) {
- for (n =3D 0; n < 8 >> size; n++) {
- int xs;
- for (xs =3D 0; xs < interleave; xs++) {
- int tt =3D rd + reg + spacing * xs;
-
- if (load) {
- gen_aa32_ld_i64(s, tmp64, addr, mmu_idx, endian | =
size);
- neon_store_element64(tt, n, size, tmp64);
- } else {
- neon_load_element64(tmp64, tt, n, size);
- gen_aa32_st_i64(s, tmp64, addr, mmu_idx, endian | =
size);
- }
- tcg_gen_add_i32(addr, addr, tmp2);
- }
- }
- }
- tcg_temp_free_i32(addr);
- tcg_temp_free_i32(tmp2);
- tcg_temp_free_i64(tmp64);
- stride =3D nregs * interleave * 8;
+ /* Load store all elements -- handled already by decodetree */
+ return 1;
} else {
size =3D (insn >> 10) & 3;
if (size =3D=3D 3) {
--=20
2.20.1