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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 29/39] target/arm: Convert VFM[AS]L (scalar) to decodetree
Date: Mon, 4 May 2020 13:32:59 +0100
Message-Id: <20200504123309.3808-30-peter.maydell@linaro.org>
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Convert the VFM[AS]L (scalar) insns in the 2reg-scalar-ext group
to decodetree. These are the last ones in the group so we can remove
all the legacy decode for the group.
Note that in disas_thumb2_insn() the parts of this encoding space
where the decodetree decoder returns false will correctly be directed
to illegal_op by the "(insn & (1 << 28))" check so they won't fall
into disas_coproc_insn() by mistake.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-11-peter.maydell@linaro.org
---
target/arm/neon-shared.decode | 7 +++
target/arm/translate-neon.inc.c | 32 ++++++++++
target/arm/translate.c | 107 +-------------------------------
3 files changed, 40 insertions(+), 106 deletions(-)
diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
index 63a46c63c07..f297ba8cdfc 100644
--- a/target/arm/neon-shared.decode
+++ b/target/arm/neon-shared.decode
@@ -57,3 +57,10 @@ VCMLA_scalar 1111 1110 1 . rot:2 .... .... 1000 . q:1 =
. 0 .... \
=20
VDOT_scalar 1111 1110 0 . 10 .... .... 1101 . q:1 index:1 u:1 rm:4 \
vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp
+
+%vfml_scalar_q0_rm 0:3 5:1
+%vfml_scalar_q1_index 5:1 3:1
+VFML_scalar 1111 1110 0 . 0 s:1 .... .... 1000 . 0 . 1 index:1 ... \
+ rm=3D%vfml_scalar_q0_rm vn=3D%vn_sp vd=3D%vd_dp q=3D0
+VFML_scalar 1111 1110 0 . 0 s:1 .... .... 1000 . 1 . 1 . rm:3 \
+ index=3D%vfml_scalar_q1_index vn=3D%vn_dp vd=3D%vd_dp q=3D1
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in=
c.c
index 7cc6ccb0697..b06542b8b83 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -242,3 +242,35 @@ static bool trans_VDOT_scalar(DisasContext *s, arg_VDO=
T_scalar *a)
tcg_temp_free_ptr(fpst);
return true;
}
+
+static bool trans_VFML_scalar(DisasContext *s, arg_VFML_scalar *a)
+{
+ int opr_sz;
+
+ if (!dc_isar_feature(aa32_fhm, s)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd & 0x10) || (a->q && (a->vn & 0x10)))) {
+ return false;
+ }
+
+ if (a->vd & a->q) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ opr_sz =3D (1 + a->q) * 8;
+ tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
+ vfp_reg_offset(a->q, a->vn),
+ vfp_reg_offset(a->q, a->rm),
+ cpu_env, opr_sz, opr_sz,
+ (a->index << 2) | a->s, /* is_2 =3D=3D 0 */
+ gen_helper_gvec_fmlal_idx_a32);
+ return true;
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 8574d0964f7..e269642a480 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -2610,8 +2610,6 @@ static int disas_dsp_insn(DisasContext *s, uint32_t i=
nsn)
}
=20
#define VFP_REG_SHR(x, n) (((n) > 0) ? (x) >> (n) : (x) << -(n))
-#define VFP_SREG(insn, bigbit, smallbit) \
- ((VFP_REG_SHR(insn, bigbit - 1) & 0x1e) | (((insn) >> (smallbit)) & 1))
#define VFP_DREG(reg, insn, bigbit, smallbit) do { \
if (dc_isar_feature(aa32_simd_r32, s)) { \
reg =3D (((insn) >> (bigbit)) & 0x0f) \
@@ -2622,11 +2620,8 @@ static int disas_dsp_insn(DisasContext *s, uint32_t =
insn)
reg =3D ((insn) >> (bigbit)) & 0x0f; \
}} while (0)
=20
-#define VFP_SREG_D(insn) VFP_SREG(insn, 12, 22)
#define VFP_DREG_D(reg, insn) VFP_DREG(reg, insn, 12, 22)
-#define VFP_SREG_N(insn) VFP_SREG(insn, 16, 7)
#define VFP_DREG_N(reg, insn) VFP_DREG(reg, insn, 16, 7)
-#define VFP_SREG_M(insn) VFP_SREG(insn, 0, 5)
#define VFP_DREG_M(reg, insn) VFP_DREG(reg, insn, 0, 5)
=20
static void gen_neon_dup_low16(TCGv_i32 var)
@@ -7032,94 +7027,6 @@ static int disas_neon_data_insn(DisasContext *s, uin=
t32_t insn)
return 0;
}
=20
-/* Advanced SIMD two registers and a scalar extension.
- * 31 24 23 22 20 16 12 11 10 9 8 3 =
0
- * +-----------------+----+---+----+----+----+---+----+---+----+---------+=
----+
- * | 1 1 1 1 1 1 1 0 | o1 | D | o2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U |=
Vm |
- * +-----------------+----+---+----+----+----+---+----+---+----+---------+=
----+
- *
- */
-
-static int disas_neon_insn_2reg_scalar_ext(DisasContext *s, uint32_t insn)
-{
- gen_helper_gvec_3 *fn_gvec =3D NULL;
- gen_helper_gvec_3_ptr *fn_gvec_ptr =3D NULL;
- int rd, rn, rm, opr_sz, data;
- int off_rn, off_rm;
- bool is_long =3D false, q =3D extract32(insn, 6, 1);
- bool ptr_is_env =3D false;
-
- if ((insn & 0xffa00f10) =3D=3D 0xfe000810) {
- /* VFM[AS]L -- 1111 1110 0.0S .... .... 1000 .Q.1 .... */
- int is_s =3D extract32(insn, 20, 1);
- int vm20 =3D extract32(insn, 0, 3);
- int vm3 =3D extract32(insn, 3, 1);
- int m =3D extract32(insn, 5, 1);
- int index;
-
- if (!dc_isar_feature(aa32_fhm, s)) {
- return 1;
- }
- if (q) {
- rm =3D vm20;
- index =3D m * 2 + vm3;
- } else {
- rm =3D vm20 * 2 + m;
- index =3D vm3;
- }
- is_long =3D true;
- data =3D (index << 2) | is_s; /* is_2 =3D=3D 0 */
- fn_gvec_ptr =3D gen_helper_gvec_fmlal_idx_a32;
- ptr_is_env =3D true;
- } else {
- return 1;
- }
-
- VFP_DREG_D(rd, insn);
- if (rd & q) {
- return 1;
- }
- if (q || !is_long) {
- VFP_DREG_N(rn, insn);
- if (rn & q & !is_long) {
- return 1;
- }
- off_rn =3D vfp_reg_offset(1, rn);
- off_rm =3D vfp_reg_offset(1, rm);
- } else {
- rn =3D VFP_SREG_N(insn);
- off_rn =3D vfp_reg_offset(0, rn);
- off_rm =3D vfp_reg_offset(0, rm);
- }
- if (s->fp_excp_el) {
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
- syn_simd_access_trap(1, 0xe, false), s->fp_excp=
_el);
- return 0;
- }
- if (!s->vfp_enabled) {
- return 1;
- }
-
- opr_sz =3D (1 + q) * 8;
- if (fn_gvec_ptr) {
- TCGv_ptr ptr;
- if (ptr_is_env) {
- ptr =3D cpu_env;
- } else {
- ptr =3D get_fpstatus_ptr(1);
- }
- tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, ptr,
- opr_sz, opr_sz, data, fn_gvec_ptr);
- if (!ptr_is_env) {
- tcg_temp_free_ptr(ptr);
- }
- } else {
- tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm,
- opr_sz, opr_sz, data, fn_gvec);
- }
- return 0;
-}
-
static int disas_coproc_insn(DisasContext *s, uint32_t insn)
{
int cpnum, is64, crn, crm, opc1, opc2, isread, rt, rt2;
@@ -10843,12 +10750,6 @@ static void disas_arm_insn(DisasContext *s, unsign=
ed int insn)
}
}
}
- } else if ((insn & 0x0f000a00) =3D=3D 0x0e000800
- && arm_dc_feature(s, ARM_FEATURE_V8)) {
- if (disas_neon_insn_2reg_scalar_ext(s, insn)) {
- goto illegal_op;
- }
- return;
}
goto illegal_op;
}
@@ -11026,13 +10927,7 @@ static void disas_thumb2_insn(DisasContext *s, uin=
t32_t insn)
}
break;
}
- if ((insn & 0xff000a00) =3D=3D 0xfe000800
- && arm_dc_feature(s, ARM_FEATURE_V8)) {
- /* The Thumb2 and ARM encodings are identical. */
- if (disas_neon_insn_2reg_scalar_ext(s, insn)) {
- goto illegal_op;
- }
- } else if (((insn >> 24) & 3) =3D=3D 3) {
+ if (((insn >> 24) & 3) =3D=3D 3) {
/* Translate into the equivalent ARM encoding. */
insn =3D (insn & 0xe2ffffff) | ((insn & (1 << 28)) >> 4) | (1 =
<< 28);
if (disas_neon_data_insn(s, insn)) {
--=20
2.20.1