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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 26/39] target/arm: Convert VFM[AS]L (vector) to decodetree
Date: Mon, 4 May 2020 13:32:56 +0100
Message-Id: <20200504123309.3808-27-peter.maydell@linaro.org>
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Convert the VFM[AS]L (vector) insns to decodetree. This is the last
insn in the legacy decoder for the 3same_ext group, so we can
delete the legacy decoder function for the group entirely.
Note that in disas_thumb2_insn() the parts of this encoding space
where the decodetree decoder returns false will correctly be directed
to illegal_op by the "(insn & (1 << 28))" check so they won't fall
into disas_coproc_insn() by mistake.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-8-peter.maydell@linaro.org
---
target/arm/neon-shared.decode | 6 +++
target/arm/translate-neon.inc.c | 31 +++++++++++
target/arm/translate.c | 92 +--------------------------------
3 files changed, 38 insertions(+), 91 deletions(-)
diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
index c9c641905d3..90cd5c871e2 100644
--- a/target/arm/neon-shared.decode
+++ b/target/arm/neon-shared.decode
@@ -43,3 +43,9 @@ VCADD 1111 110 rot:1 1 . 0 size:1 .... .... 1000=
. q:1 . 0 .... \
# VUDOT and VSDOT
VDOT 1111 110 00 . 10 .... .... 1101 . q:1 . u:1 .... \
vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp
+
+# VFM[AS]L
+VFML 1111 110 0 s:1 . 10 .... .... 1000 . 0 . 1 .... \
+ vm=3D%vm_sp vn=3D%vn_sp vd=3D%vd_dp q=3D0
+VFML 1111 110 0 s:1 . 10 .... .... 1000 . 1 . 1 .... \
+ vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp q=3D1
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in=
c.c
index 6537506c5b6..6c58abc54b5 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -136,3 +136,34 @@ static bool trans_VDOT(DisasContext *s, arg_VDOT *a)
opr_sz, opr_sz, 0, fn_gvec);
return true;
}
+
+static bool trans_VFML(DisasContext *s, arg_VFML *a)
+{
+ int opr_sz;
+
+ if (!dc_isar_feature(aa32_fhm, s)) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ (a->vd & 0x10)) {
+ return false;
+ }
+
+ if (a->vd & a->q) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ opr_sz =3D (1 + a->q) * 8;
+ tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
+ vfp_reg_offset(a->q, a->vn),
+ vfp_reg_offset(a->q, a->vm),
+ cpu_env, opr_sz, opr_sz, a->s, /* is_2 =3D=3D 0 */
+ gen_helper_gvec_fmlal_a32);
+ return true;
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index 7d3aea8c98a..79cd9138fe7 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7032,84 +7032,6 @@ static int disas_neon_data_insn(DisasContext *s, uin=
t32_t insn)
return 0;
}
=20
-/* Advanced SIMD three registers of the same length extension.
- * 31 25 23 22 20 16 12 11 10 9 8 3 =
0
- * +---------------+-----+---+-----+----+----+---+----+---+----+---------+=
----+
- * | 1 1 1 1 1 1 0 | op1 | D | op2 | Vn | Vd | 1 | o3 | 0 | o4 | N Q M U |=
Vm |
- * +---------------+-----+---+-----+----+----+---+----+---+----+---------+=
----+
- */
-static int disas_neon_insn_3same_ext(DisasContext *s, uint32_t insn)
-{
- gen_helper_gvec_3 *fn_gvec =3D NULL;
- gen_helper_gvec_3_ptr *fn_gvec_ptr =3D NULL;
- int rd, rn, rm, opr_sz;
- int data =3D 0;
- int off_rn, off_rm;
- bool is_long =3D false, q =3D extract32(insn, 6, 1);
- bool ptr_is_env =3D false;
-
- if ((insn & 0xff300f10) =3D=3D 0xfc200810) {
- /* VFM[AS]L -- 1111 1100 S.10 .... .... 1000 .Q.1 .... */
- int is_s =3D extract32(insn, 23, 1);
- if (!dc_isar_feature(aa32_fhm, s)) {
- return 1;
- }
- is_long =3D true;
- data =3D is_s; /* is_2 =3D=3D 0 */
- fn_gvec_ptr =3D gen_helper_gvec_fmlal_a32;
- ptr_is_env =3D true;
- } else {
- return 1;
- }
-
- VFP_DREG_D(rd, insn);
- if (rd & q) {
- return 1;
- }
- if (q || !is_long) {
- VFP_DREG_N(rn, insn);
- VFP_DREG_M(rm, insn);
- if ((rn | rm) & q & !is_long) {
- return 1;
- }
- off_rn =3D vfp_reg_offset(1, rn);
- off_rm =3D vfp_reg_offset(1, rm);
- } else {
- rn =3D VFP_SREG_N(insn);
- rm =3D VFP_SREG_M(insn);
- off_rn =3D vfp_reg_offset(0, rn);
- off_rm =3D vfp_reg_offset(0, rm);
- }
-
- if (s->fp_excp_el) {
- gen_exception_insn(s, s->pc_curr, EXCP_UDEF,
- syn_simd_access_trap(1, 0xe, false), s->fp_excp=
_el);
- return 0;
- }
- if (!s->vfp_enabled) {
- return 1;
- }
-
- opr_sz =3D (1 + q) * 8;
- if (fn_gvec_ptr) {
- TCGv_ptr ptr;
- if (ptr_is_env) {
- ptr =3D cpu_env;
- } else {
- ptr =3D get_fpstatus_ptr(1);
- }
- tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd), off_rn, off_rm, ptr,
- opr_sz, opr_sz, data, fn_gvec_ptr);
- if (!ptr_is_env) {
- tcg_temp_free_ptr(ptr);
- }
- } else {
- tcg_gen_gvec_3_ool(vfp_reg_offset(1, rd), off_rn, off_rm,
- opr_sz, opr_sz, data, fn_gvec);
- }
- return 0;
-}
-
/* Advanced SIMD two registers and a scalar extension.
* 31 24 23 22 20 16 12 11 10 9 8 3 =
0
* +-----------------+----+---+----+----+----+---+----+---+----+---------+=
----+
@@ -10956,12 +10878,6 @@ static void disas_arm_insn(DisasContext *s, unsign=
ed int insn)
}
}
}
- } else if ((insn & 0x0e000a00) =3D=3D 0x0c000800
- && arm_dc_feature(s, ARM_FEATURE_V8)) {
- if (disas_neon_insn_3same_ext(s, insn)) {
- goto illegal_op;
- }
- return;
} else if ((insn & 0x0f000a00) =3D=3D 0x0e000800
&& arm_dc_feature(s, ARM_FEATURE_V8)) {
if (disas_neon_insn_2reg_scalar_ext(s, insn)) {
@@ -11145,15 +11061,9 @@ static void disas_thumb2_insn(DisasContext *s, uin=
t32_t insn)
}
break;
}
- if ((insn & 0xfe000a00) =3D=3D 0xfc000800
+ if ((insn & 0xff000a00) =3D=3D 0xfe000800
&& arm_dc_feature(s, ARM_FEATURE_V8)) {
/* The Thumb2 and ARM encodings are identical. */
- if (disas_neon_insn_3same_ext(s, insn)) {
- goto illegal_op;
- }
- } else if ((insn & 0xff000a00) =3D=3D 0xfe000800
- && arm_dc_feature(s, ARM_FEATURE_V8)) {
- /* The Thumb2 and ARM encodings are identical. */
if (disas_neon_insn_2reg_scalar_ext(s, insn)) {
goto illegal_op;
}
--=20
2.20.1