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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 24/39] target/arm: Convert VCADD (vector) to decodetree
Date: Mon, 4 May 2020 13:32:54 +0100
Message-Id: <20200504123309.3808-25-peter.maydell@linaro.org>
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Convert the VCADD (vector) insns to decodetree.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200430181003.21682-6-peter.maydell@linaro.org
---
target/arm/neon-shared.decode | 3 +++
target/arm/translate-neon.inc.c | 37 +++++++++++++++++++++++++++++++++
target/arm/translate.c | 11 +---------
3 files changed, 41 insertions(+), 10 deletions(-)
diff --git a/target/arm/neon-shared.decode b/target/arm/neon-shared.decode
index d1d707a56d5..ed65dae1809 100644
--- a/target/arm/neon-shared.decode
+++ b/target/arm/neon-shared.decode
@@ -36,3 +36,6 @@
=20
VCMLA 1111 110 rot:2 . 1 size:1 .... .... 1000 . q:1 . 0 .... \
vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp
+
+VCADD 1111 110 rot:1 1 . 0 size:1 .... .... 1000 . q:1 . 0 .... \
+ vm=3D%vm_dp vn=3D%vn_dp vd=3D%vd_dp
diff --git a/target/arm/translate-neon.inc.c b/target/arm/translate-neon.in=
c.c
index 0baae1338a3..28011e88d9e 100644
--- a/target/arm/translate-neon.inc.c
+++ b/target/arm/translate-neon.inc.c
@@ -67,3 +67,40 @@ static bool trans_VCMLA(DisasContext *s, arg_VCMLA *a)
tcg_temp_free_ptr(fpst);
return true;
}
+
+static bool trans_VCADD(DisasContext *s, arg_VCADD *a)
+{
+ int opr_sz;
+ TCGv_ptr fpst;
+ gen_helper_gvec_3_ptr *fn_gvec_ptr;
+
+ if (!dc_isar_feature(aa32_vcma, s)
+ || (!a->size && !dc_isar_feature(aa32_fp16_arith, s))) {
+ return false;
+ }
+
+ /* UNDEF accesses to D16-D31 if they don't exist. */
+ if (!dc_isar_feature(aa32_simd_r32, s) &&
+ ((a->vd | a->vn | a->vm) & 0x10)) {
+ return false;
+ }
+
+ if ((a->vn | a->vm | a->vd) & a->q) {
+ return false;
+ }
+
+ if (!vfp_access_check(s)) {
+ return true;
+ }
+
+ opr_sz =3D (1 + a->q) * 8;
+ fpst =3D get_fpstatus_ptr(1);
+ fn_gvec_ptr =3D a->size ? gen_helper_gvec_fcadds : gen_helper_gvec_fca=
ddh;
+ tcg_gen_gvec_3_ptr(vfp_reg_offset(1, a->vd),
+ vfp_reg_offset(1, a->vn),
+ vfp_reg_offset(1, a->vm),
+ fpst, opr_sz, opr_sz, a->rot,
+ fn_gvec_ptr);
+ tcg_temp_free_ptr(fpst);
+ return true;
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index ae6799c6ae0..993bead82ff 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -7048,16 +7048,7 @@ static int disas_neon_insn_3same_ext(DisasContext *s=
, uint32_t insn)
bool is_long =3D false, q =3D extract32(insn, 6, 1);
bool ptr_is_env =3D false;
=20
- if ((insn & 0xfea00f10) =3D=3D 0xfc800800) {
- /* VCADD -- 1111 110R 1.0S .... .... 1000 ...0 .... */
- int size =3D extract32(insn, 20, 1);
- data =3D extract32(insn, 24, 1); /* rot */
- if (!dc_isar_feature(aa32_vcma, s)
- || (!size && !dc_isar_feature(aa32_fp16_arith, s))) {
- return 1;
- }
- fn_gvec_ptr =3D size ? gen_helper_gvec_fcadds : gen_helper_gvec_fc=
addh;
- } else if ((insn & 0xfeb00f00) =3D=3D 0xfc200d00) {
+ if ((insn & 0xfeb00f00) =3D=3D 0xfc200d00) {
/* V[US]DOT -- 1111 1100 0.10 .... .... 1101 .Q.U .... */
bool u =3D extract32(insn, 4, 1);
if (!dc_isar_feature(aa32_dp, s)) {
--=20
2.20.1