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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j22sm491518wre.84.2020.04.30.04.51.44 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 04:51:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=/MnAU0cO9JgocJyxoLrzCpuFBf9q8CvPSi85jGiI5DM=; b=YvtNnQW4BR7HCNPgQzK/rFLYnyii5Xtrcm9qNz9eXaJbyqpcXLFqQpzJXczhpISXXO dmfXVsL0b6CJIyokpY8nvPDAQx+iI63HQVWBg3YYAMBjq6QiffzU7kOIegD36X2ApmXH dnLEhZppsD8ncVxwsfmqKwlsE1Ayzss3ZSs/8nnadO+CxMQC88ZsZ8DK86vu+IzPxhnr tNGyTFkTBT5b6GQfaM7kNaD2Q+8kFt73sR8NcsQZ3KJeZX5RXrxrdQoVQRTKJiIfRbcs i4oL8I0Vz2/zpstWU5azrf+GdZSID/WctO1fSI0tHyKPZqspfZKs8HOBX6C+wPku9Zqf tAKA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/MnAU0cO9JgocJyxoLrzCpuFBf9q8CvPSi85jGiI5DM=; b=OuBdxykYCZ0909rpB79vXrhR39YVFxIlx3ul0aWTT82pL/eJMDPQcglXa/+isL1NgS yYUA89ZIvEkZLL8xcT1i1PBidA00ishs9n9ARbvT0SweiVKOjaA8zddbrb2g36yOwqXH qIbDVaT3fuMeMT0+XfsrcIupttR4iIpPiEsZsfwCYPDXCWQ1i3w8sSHEkA3RjxJlyTek P1c5M7D1Toht4C37Snbsbv0QrG92PBkZAa9rzaIJuwOitWSvBsD0KykuTI0Fos2RBRvh Nb94oUFscUNJQIZK3ukRpd5nxg7U3H3pw/VVjotKhpGQJE9h1/YWUhaRTO2F/FaIjOLz Qagg== X-Gm-Message-State: AGi0Puba4M3GOP8mPGwW7ZeIoZ4m8ABhexokX0GwOBlaDcTMVrixYY2e NusWF0Zj1SEY3dIWdUpG+siQJy2x7yblDA== X-Google-Smtp-Source: APiQypKCFFAuR5plM3+7dCTALpj5ecz9UVzHjCF4NeRYnc+NknJxPXb44NYl0ayuG4QKYE79bhlQ7Q== X-Received: by 2002:a1c:9a16:: with SMTP id c22mr2514194wme.38.1588247505769; Thu, 30 Apr 2020 04:51:45 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/31] dma/xlnx-zdma: Fix descriptor loading (MEM) wrt endianness Date: Thu, 30 Apr 2020 12:51:12 +0100 Message-Id: <20200430115142.13430-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200430115142.13430-1-peter.maydell@linaro.org> References: <20200430115142.13430-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::32a X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: "Edgar E. Iglesias" Fix descriptor loading from memory wrt host endianness. Reported-by: Peter Maydell Signed-off-by: Edgar E. Iglesias Reviewed-by: Francisco Iglesias Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20200404122718.25111-2-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- hw/dma/xlnx-zdma.c | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c index 1c45367f3c6..5f4775f6634 100644 --- a/hw/dma/xlnx-zdma.c +++ b/hw/dma/xlnx-zdma.c @@ -299,19 +299,22 @@ static void zdma_put_regaddr64(XlnxZDMA *s, unsigned = int basereg, uint64_t addr) s->regs[basereg + 1] =3D addr >> 32; } =20 -static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr, void *buf) +static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr, + XlnxZDMADescr *descr) { /* ZDMA descriptors must be aligned to their own size. */ if (addr % sizeof(XlnxZDMADescr)) { qemu_log_mask(LOG_GUEST_ERROR, "zdma: unaligned descriptor at %" PRIx64, addr); - memset(buf, 0x0, sizeof(XlnxZDMADescr)); + memset(descr, 0x0, sizeof(XlnxZDMADescr)); s->error =3D true; return false; } =20 - address_space_read(s->dma_as, addr, s->attr, buf, sizeof(XlnxZDMADescr= )); + descr->addr =3D address_space_ldq_le(s->dma_as, addr, s->attr, NULL); + descr->size =3D address_space_ldl_le(s->dma_as, addr + 8, s->attr, NUL= L); + descr->attr =3D address_space_ldl_le(s->dma_as, addr + 12, s->attr, NU= LL); return true; } =20 @@ -344,7 +347,7 @@ static void zdma_update_descr_addr(XlnxZDMA *s, bool ty= pe, } else { addr =3D zdma_get_regaddr64(s, basereg); addr +=3D sizeof(s->dsc_dst); - address_space_read(s->dma_as, addr, s->attr, (void *) &next, 8); + next =3D address_space_ldq_le(s->dma_as, addr, s->attr, NULL); } =20 zdma_put_regaddr64(s, basereg, next); --=20 2.20.1 From nobody Thu May 2 02:03:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1588247586; cv=none; d=zohomail.com; s=zohoarc; b=R3n1qIa9W8DF/BewQ+LIRoopeBEzZJj3jROXYrKNB0CDraroRMFpRHMhX3k4ZbcqfhCk1hNKkF/pyyKn3CIZhIPJ+Pq7wgbMghah+u4D7IiMqZ+KqllbKcDYZzJ7TZBgAevnEEsWc/DECBbx0qvlBL2MvsKoG9l3RmYwndBKp9k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588247586; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=BESuML9GbRyguxqavl6NTEOE21Pzf9E6NWZj1nNhY7E=; b=iPq1DQo/U5fbIv5oQrab5temCVu3q9Us7aChI/eayShgoikt1SNGib4cGDxd9qeOofSomGJQUSxL7KGRCEADYOUVKkvhDY7EIzWWlozfIqd8EpJVBp0CFAudIMz3ToneOhJcTt5/HNUKP7qRStbU4vKLU7FjFniq0SITQZR/Qfg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1588247586587208.34652995981116; Thu, 30 Apr 2020 04:53:06 -0700 (PDT) Received: from localhost ([::1]:34790 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU7kX-0004JT-6r for importer@patchew.org; Thu, 30 Apr 2020 07:53:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33662) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU7jL-0002XM-1b for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:51:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.90_1) (envelope-from ) id 1jU7jK-0000Iy-F8 for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:51:50 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:35364) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jU7jK-0000HH-2E for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:51:50 -0400 Received: by mail-wr1-x42d.google.com with SMTP id x18so6529025wrq.2 for ; Thu, 30 Apr 2020 04:51:49 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j22sm491518wre.84.2020.04.30.04.51.45 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 04:51:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=BESuML9GbRyguxqavl6NTEOE21Pzf9E6NWZj1nNhY7E=; b=i4eA2l04wSBKHwxuyED4RfyLAsRhcHtTtzPso8JzKvUBzK+ikIoF5pwJTbT59dOD6n xhO6fQ8w7/HbrUg4uJ6w5D9jX/UmVdvIUMBTxizoDxQYsDzmz3ZezZD9Hp7vm7acWlUK BqZsYuCtjbhHGR9pxnO+cdhuhslMWbjgCdHxt/Br5Lvg3vFrCrA82E40l44MwV2uvzEf xIsphQu/+Rcl9sVAGjqWJ/Y0zo7/zGR08o9ADiYGz3zNVABQiypIoLVdh7GoOt11tZiC xq20ql1EJ8FUu22mJA2XC5Sqrtq/IVtrg9FhjdhTXDVPuzhgFqAfOAID4X7fv5cJxEWW KWRQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BESuML9GbRyguxqavl6NTEOE21Pzf9E6NWZj1nNhY7E=; b=j7cY7DicDgdQQipKLRreH0/kn6IBtn7m5i2N1q4HHWzWt+hPTjZ7NhOxFe4cu4fV1d J5j4wuVq0yA2ZDkcwouqEecUGklQqcZo+y/j4Vj0rvpf4cRbyMWhRylqopIHPdEA0SAO Nq3QSACE5IPyMXvPe7/y0y8hEmhGHnBM5uCI136tx1vR6MQgN6T6ZCQoEPG80sCH5tO8 WdVHgsHvjsX2hAJridLsVMLOnu/YskkWKEf6ifyMos/J14Hu9K6c1Z0bV8LxAACcAP2S 433fqX9GDeHFsQgJvdsvpF86Ok4ogq6u4+S8LSyLffPR4EZG1174uMk277W6NayX70S1 +RHQ== X-Gm-Message-State: AGi0PubWmaFGdzzJA//Gr+ZKDBMArawKkuvFxH4G3efOGFHG/mJ4VOUY IcX249opPyU3QdzcuOf+GPR8ESWzfWEvPg== X-Google-Smtp-Source: APiQypJGCLmYn+OyY8yRHkWZ8BNn+2ubOToE7Lgeja9m+zH+Nr0CqL8tpSQbgi9oD2RSn0Q8vaGr3w== X-Received: by 2002:adf:bb4e:: with SMTP id x14mr249340wrg.63.1588247506806; Thu, 30 Apr 2020 04:51:46 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/31] dma/xlnx-zdma: Fix descriptor loading (REG) wrt endianness Date: Thu, 30 Apr 2020 12:51:13 +0100 Message-Id: <20200430115142.13430-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200430115142.13430-1-peter.maydell@linaro.org> References: <20200430115142.13430-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::42d X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Fix descriptor loading from registers wrt host endianness. Reported-by: Peter Maydell Signed-off-by: Edgar E. Iglesias Reviewed-by: Francisco Iglesias Message-id: 20200404122718.25111-3-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- hw/dma/xlnx-zdma.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c index 5f4775f6634..4121a1b489c 100644 --- a/hw/dma/xlnx-zdma.c +++ b/hw/dma/xlnx-zdma.c @@ -299,6 +299,14 @@ static void zdma_put_regaddr64(XlnxZDMA *s, unsigned i= nt basereg, uint64_t addr) s->regs[basereg + 1] =3D addr >> 32; } =20 +static void zdma_load_descriptor_reg(XlnxZDMA *s, unsigned int reg, + XlnxZDMADescr *descr) +{ + descr->addr =3D zdma_get_regaddr64(s, reg); + descr->size =3D s->regs[reg + 2]; + descr->attr =3D s->regs[reg + 3]; +} + static bool zdma_load_descriptor(XlnxZDMA *s, uint64_t addr, XlnxZDMADescr *descr) { @@ -324,8 +332,7 @@ static void zdma_load_src_descriptor(XlnxZDMA *s) unsigned int ptype =3D ARRAY_FIELD_EX32(s->regs, ZDMA_CH_CTRL0, POINT_= TYPE); =20 if (ptype =3D=3D PT_REG) { - memcpy(&s->dsc_src, &s->regs[R_ZDMA_CH_SRC_DSCR_WORD0], - sizeof(s->dsc_src)); + zdma_load_descriptor_reg(s, R_ZDMA_CH_SRC_DSCR_WORD0, &s->dsc_src); return; } =20 @@ -360,8 +367,7 @@ static void zdma_load_dst_descriptor(XlnxZDMA *s) bool dst_type; =20 if (ptype =3D=3D PT_REG) { - memcpy(&s->dsc_dst, &s->regs[R_ZDMA_CH_DST_DSCR_WORD0], - sizeof(s->dsc_dst)); + zdma_load_descriptor_reg(s, R_ZDMA_CH_DST_DSCR_WORD0, &s->dsc_dst); return; } =20 --=20 2.20.1 From nobody Thu May 2 02:03:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1588247670; cv=none; d=zohomail.com; s=zohoarc; b=j+i+P62sH1WGIKsfDSuvdWxLEAjd8iyB4tYIxZ8EIDfWb12J73WFKbnnP500RcsFcoUilmO4KKcsx77pNK/lrXlbfimHp63p73Hbf6Nl2kSocxW+bn3pJQQL4BFQ/n6UqI5R1UIGyeWKA8z7TMRoJaqqtUdHXI7X4IEHnOC0Lf0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588247670; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LRt+lYSZxICWhOZXCGhxNCm7v8wo6m7PPTzVoY8b3a0=; b=VehtcWOivXtvLH+WnYeV9l0C6w+N2VCdyCKHU8K7K+8ynU6OYQf7UHO9CSrBVBrvOGMrIJolX9D/9/mlsQpVi1kXcyK69ictu7hZvtZaTtG0gY/E7nEJ3jX6TVwJFEamj+4emBOstqORdJSVhCKiGvFGhug39lGBFqTkZyQJo4o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1588247670954693.046543132207; Thu, 30 Apr 2020 04:54:30 -0700 (PDT) Received: from localhost ([::1]:43230 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU7lt-0007se-M5 for importer@patchew.org; Thu, 30 Apr 2020 07:54:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33658) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU7jK-0002X7-Si for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:51:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.90_1) (envelope-from ) id 1jU7jJ-0000Ij-UC for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:51:50 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:34399) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jU7jJ-0000DL-GC for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:51:49 -0400 Received: by mail-wr1-x435.google.com with SMTP id j1so6545601wrt.1 for ; Thu, 30 Apr 2020 04:51:48 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j22sm491518wre.84.2020.04.30.04.51.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 04:51:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=LRt+lYSZxICWhOZXCGhxNCm7v8wo6m7PPTzVoY8b3a0=; b=Q/mZ1ygEfsJcFYtfk8Rb6ns5vCKF7xqY11Uq4q2uL23rmKeVi93hgQRZpQeM1kJ03U VIg2cO97UkM8PRijFuAeEZ7DCiCV1ral3XglmVvIGslWpEhdaoN8bP+vaPFjPyWnyiAP DB4dZaW7CnabmlytA4H3scZ8J6lLEl23yCZxa8klMGb6pMHyooOBB3bE86cp5aY/Nh9x aRVLXVj+MEl85c+fDaOvaknm3+CJg2Gdg0o8x+Cb3cGfS0nAwYTklJuFJBwVyW6qLiFI 5497vV4NLQVBrhuMeku0n1/pdW3ebQuHKJQs9qK+NR5zWQrdf4ji1jWCcrykXQy1de/D Sqqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LRt+lYSZxICWhOZXCGhxNCm7v8wo6m7PPTzVoY8b3a0=; b=iqp4EqR/l4klRf9kNHA7gs+ATpqHuWjTWuc9pn8ONoZBRR1AW3aQHpJp6eFW7FHTIt M9tvpZmEZT46cqRkxP2ZWLY+9vnodr+irk0mUBU4Yziau9azYP4DFEhGff5TJ1fLKN3Z gNoIk3nogabdtT2EqYZI1qbPVPYDdpHogbreRdOgAMLzk2GsSnfYi1RB/5cZIXH5Fy+x gVeyk4SrWHV7g8Mz8DU02HfXQE3O7tv4JQZeT2lC2Y1PsDosFPmwybkS5T1H8pVRrR2Y QE9AmpsDpZcfpOyKgfibS8aPqAwMWbx2T6r4rxWCfGwE1RQ6giAqFyjHOe6bAU9mcupQ LZMg== X-Gm-Message-State: AGi0PuYHOIgwXg8sZnI6YOFcw8WTgXNGdiXg+nWFUOpd4wIfv9nMh7Nh uJxwXsM0QH5sjDC1m2Lc2HMuSJd/N/DwsQ== X-Google-Smtp-Source: APiQypLwT2k7CDrajjpNsSq5DNhq9eBeJ0FWmPubpK4BK4frrckAWJ+ORqq5b9dE2y3c83lOiZ/EFA== X-Received: by 2002:a5d:4cc2:: with SMTP id c2mr3643097wrt.130.1588247507744; Thu, 30 Apr 2020 04:51:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/31] nrf51: Fix last GPIO CNF address Date: Thu, 30 Apr 2020 12:51:14 +0100 Message-Id: <20200430115142.13430-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200430115142.13430-1-peter.maydell@linaro.org> References: <20200430115142.13430-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::435 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Cameron Esfahani NRF51_GPIO_REG_CNF_END doesn't actually refer to the start of the last valid CNF register: it's referring to the last byte of the last valid CNF register. This hasn't been a problem up to now, as current implementation in memory.c turns an unaligned 4-byte read from 0x77f to a single byte read and the qtest only looks at the least-significant byte of the register. But when running with patches which fix unaligned accesses in memory.c, the qtest breaks. Considering NRF51 doesn't support unaligned accesses, the simplest fix is to actually set NRF51_GPIO_REG_CNF_END to the start of the last valid CNF register: 0x77c. Now, qtests work with or without the unaligned access patches. Reviewed-by: C=C3=A9dric Le Goater Tested-by: C=C3=A9dric Le Goater Reviewed-by: Joel Stanley Signed-off-by: Cameron Esfahani Message-id: 51b427f06838622da783d38ba56e3630d6d85c60.1586925392.git.dirty@a= pple.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/gpio/nrf51_gpio.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/include/hw/gpio/nrf51_gpio.h b/include/hw/gpio/nrf51_gpio.h index 337ee534bbc..1d62bbc9285 100644 --- a/include/hw/gpio/nrf51_gpio.h +++ b/include/hw/gpio/nrf51_gpio.h @@ -42,7 +42,7 @@ #define NRF51_GPIO_REG_DIRSET 0x518 #define NRF51_GPIO_REG_DIRCLR 0x51C #define NRF51_GPIO_REG_CNF_START 0x700 -#define NRF51_GPIO_REG_CNF_END 0x77F +#define NRF51_GPIO_REG_CNF_END 0x77C =20 #define NRF51_GPIO_PULLDOWN 1 #define NRF51_GPIO_PULLUP 3 --=20 2.20.1 From nobody Thu May 2 02:03:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1588247701; cv=none; d=zohomail.com; s=zohoarc; b=IWgIe51VMMJ/1UH12I6szzT2rdv+JZN78uVr5VAqwIUmIzDfpPyjUo9Y7ZtlLU2t3Y1a9c/+oFYsRjWcd4Xz+4RT2BKOY702JrQa4GMrhJ3r68MnMiNAhTKOnLcqwEoh7d50/KVYpSJwCPg0h2CZJcMp+X2Z2DBDTFWa47sIbQg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588247701; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=aa1qqIMnXpjpthzM2FPrENFyjimJ3PELzKEsUQJpRs8=; b=TpouaQn8XvAFeBRfGkT1ViH+jJwQIQeMXRAoWQmnWJbtboQ3/lE1sKWdAxp5C6wItZSR8LA517n9pru6uKC3TAM991X4PHHJOJxA1DTK8PYep+78Chqk3VYqimZ9vUXJZ2IX7QWGIbJPk5TJubjlinU6fazBLzmavnx1tYWmCTU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1588247701432403.2301529230225; Thu, 30 Apr 2020 04:55:01 -0700 (PDT) Received: from localhost ([::1]:46376 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU7mO-0000gz-5L for importer@patchew.org; Thu, 30 Apr 2020 07:55:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33670) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU7jL-0002YG-G2 for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:51:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.90_1) (envelope-from ) id 1jU7jK-0000J9-M8 for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:51:51 -0400 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:40414) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jU7jK-0000IG-8z for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:51:50 -0400 Received: by mail-wm1-x343.google.com with SMTP id u16so1541386wmc.5 for ; Thu, 30 Apr 2020 04:51:49 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j22sm491518wre.84.2020.04.30.04.51.47 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 04:51:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=aa1qqIMnXpjpthzM2FPrENFyjimJ3PELzKEsUQJpRs8=; b=IMX5xQMLXV5vCVWhNk06NdmsJFZyfapHgFItGiUnuNTX1DnAly6kKAmFjFw9pNrk5F /Ao6io/ZQntIJoyijSaPn7i/OBhMBBkHdB5ELz3FQO6t7m9V1NnMQFCe5/QQOh7G87u9 x1Ps4oq0uMLmMP2I0veFKTxnHHanmCJEcPLO8ZQAo1yzamTZ8DwRN3bCJMTBiIFF7JP0 wX1J+WGmefotWajRECtj99m4e3iERpkj5VNZpWFb1om3EbjKN7OXFt6gR0HLtkv25/BU OV9qvvwZOgpXFH/5H6kg4dJy2mn/ooNSsZor4xEhjTUNk8sdpxJ4pa9vdXPrGywQreBE J6tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aa1qqIMnXpjpthzM2FPrENFyjimJ3PELzKEsUQJpRs8=; b=gvjZFoW5zmpkxkeLbFKxDGEp1B570F+D2jr0XBkImwcDwP29Yz7nysLTPOaZjTDtKP ZG9RL1OC+edngK82C7M4rTpwkdvUekh0DaOmPn6FY1xJXHcuDOinGqHuLyVub1V4Smi+ 6/QlyZqHwVQyLKRE65SkwR5I75/yl1w4/P3qzAc0HaTyrXzGz3uX+qK549/9RRiQbdrq cLINSlk/C6XOfD3HhViJ4QjLVXADg/17wL9oFTqkpj/ehXpdfJdm/7fPqroFeTDGXE+A KS/v9YNLEVyHOB0R7eGEOuroFM7VH0qxok6u/YPhEAlYw8hCJfKe28hk7+MB/bwz3Owp crJQ== X-Gm-Message-State: AGi0PuaHhF0jCq0Zg9EFEWixdyQgfPtBYV6hiREySV73ZEaBOdfnCP+w 8CLWtKxH52GwgNklH8G2WAJ8NUhNfo/wKA== X-Google-Smtp-Source: APiQypItK3+3K3yJyqhPcIpL+rTJvCuB5q/myiiHA5hA3hqBn4qmA2fYCITf1G9yzb9hwYUBp5Ml1A== X-Received: by 2002:a7b:c38e:: with SMTP id s14mr2462301wmj.12.1588247508669; Thu, 30 Apr 2020 04:51:48 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/31] bugfix: Use gicr_typer in arm_gicv3_icc_reset Date: Thu, 30 Apr 2020 12:51:15 +0100 Message-Id: <20200430115142.13430-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200430115142.13430-1-peter.maydell@linaro.org> References: <20200430115142.13430-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x343.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Keqian Zhu The KVM_VGIC_ATTR macro expect the second parameter as gicr_typer, of which high 32bit is constructed by mp_affinity. For most case, the high 32bit of mp_affinity is zero, so it will always access the ICC_CTLR_EL1 of CPU0. Signed-off-by: Keqian Zhu Message-id: 20200413091552.62748-2-zhukeqian1@huawei.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/intc/arm_gicv3_kvm.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 49304ca589d..ca43bf87cab 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -658,13 +658,11 @@ static void kvm_arm_gicv3_get(GICv3State *s) =20 static void arm_gicv3_icc_reset(CPUARMState *env, const ARMCPRegInfo *ri) { - ARMCPU *cpu; GICv3State *s; GICv3CPUState *c; =20 c =3D (GICv3CPUState *)env->gicv3state; s =3D c->gic; - cpu =3D ARM_CPU(c->cpu); =20 c->icc_pmr_el1 =3D 0; c->icc_bpr[GICV3_G0] =3D GIC_MIN_BPR; @@ -681,7 +679,7 @@ static void arm_gicv3_icc_reset(CPUARMState *env, const= ARMCPRegInfo *ri) =20 /* Initialize to actual HW supported configuration */ kvm_device_access(s->dev_fd, KVM_DEV_ARM_VGIC_GRP_CPU_SYSREGS, - KVM_VGIC_ATTR(ICC_CTLR_EL1, cpu->mp_affinity), + KVM_VGIC_ATTR(ICC_CTLR_EL1, c->gicr_typer), &c->icc_ctlr_el1[GICV3_NS], false, &error_abort); =20 c->icc_ctlr_el1[GICV3_S] =3D c->icc_ctlr_el1[GICV3_NS]; --=20 2.20.1 From nobody Thu May 2 02:03:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1588247588; cv=none; d=zohomail.com; s=zohoarc; b=eSc6IEQexKBBGVFVMy7+ubAAXl2+oI2PaaoWQhfHixkCA/tNgVsJuWQx9wnKUJZN39uz0R/E/0XQRTi9qc5OKad5niwi0Q2PN5rQr5hkW+i9Zy8O08+aE82OTdBJyl6vZgHDTvEW+9O2PmMDMVJnGis9CmWh79tAmRm0YJy3Qdg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588247588; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=sMT/+tHHwir88ccyz19t7Y3T6ca9xpFk0IXaCH1jghA=; b=ODczrykAfn8nW+dRfj2Zzpkki4OuQqz/zIjZ/jI63uJ3ORFB8wawwJtmbhXPaA3CyoXznEODsTTjnp3J0MkTbjTKrroRvUZ7dpGMsz2gVQkcESWEO1DYY6V37MQeNXF3p4Uu5EDQDV8L8WxXDksmnYGKpDgWiL0nZUtDYTA+lO4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1588247588803535.5929185733592; Thu, 30 Apr 2020 04:53:08 -0700 (PDT) Received: from localhost ([::1]:34930 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU7kZ-0004Mm-GF for importer@patchew.org; Thu, 30 Apr 2020 07:53:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33680) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU7jM-0002ai-VL for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:51:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.90_1) (envelope-from ) id 1jU7jL-0000Jo-Sr for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:51:52 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:40091) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jU7jL-0000Iw-El for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:51:51 -0400 Received: by mail-wm1-x334.google.com with SMTP id u16so1541429wmc.5 for ; Thu, 30 Apr 2020 04:51:51 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j22sm491518wre.84.2020.04.30.04.51.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 04:51:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=sMT/+tHHwir88ccyz19t7Y3T6ca9xpFk0IXaCH1jghA=; b=Oucdw6sKR7H6AI6GH+A7eUeRIpjxhVp2P8Lo0dN0OHdvGdhv49J/MfrYDAqb5Mssr5 tYjb9kNcGmkj4VE189UstiJAjy8PNbauX8IwwdXmAmkf7gDTkxwrOnNdO221qVLVqiLz nR2RAIdAFmxpD1mqUDcSZDZjZGv2/B/HBZlZ9oYbIfk9fTFqiIKXEFznvTL1SYpxrhjZ UmFHuR6Jg5TpfzqmFhCNbjj3r8kDYXU6J8Za20Tb03JhbcTqab2JtRkoANT0ZV89UJG7 geIwTiAc0uTgb9s/aR6iLsz9+RvJxsbVcPi3bcR2O59+KzVOdPpHfeJ4LOEjPemIxqrO V4Ag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sMT/+tHHwir88ccyz19t7Y3T6ca9xpFk0IXaCH1jghA=; b=PxrXsn6d+Vfh+EC82x7rRRi+DVTJ3iFrou1JYK0tHZ1PXCTriMSFLyvclkHISDi5fN Byp9EXv3hNPslgpottXE6oMCT2BJLFpGqrfVOk7ioa8vlgWCrbK6t027Y42RSF0ldg1e X8MBSOg/wtPXaXUoFghFY0NMChtxmGu1cEm0btMYe///r1V1lgmugaki1dZWWGraOiYI 8Pna3YXFOwgRKlZT0vWSh5Z06K0sm8rc+bfHM1vG96e5zgd1cWlKVS/yfy/IHaHDl7ms oiGCSGzWNbLZ0G+0obPyDJoXJWD9VR5zJ1mMH1ZXG5uFvXW6TevYVGN9S3sdEakMH/WT f1dA== X-Gm-Message-State: AGi0PuZGd1BLdthUgluFHpsxwqmCZBK3Bg7XTB5YtAd60t/mU5/xuwZ0 A40BywCovevZ96/bEkv1mMlIK5u0YTTMZA== X-Google-Smtp-Source: APiQypICVtulZLxmFfTNYLJlfdYQGr1bBtL9mkMq2OYT6cSvYVWe4jtXFQLUcaQmidgjIdpsMFfucw== X-Received: by 2002:a7b:c104:: with SMTP id w4mr2605509wmi.8.1588247509744; Thu, 30 Apr 2020 04:51:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/31] Typo: Correct the name of CPU hotplug memory region Date: Thu, 30 Apr 2020 12:51:16 +0100 Message-Id: <20200430115142.13430-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200430115142.13430-1-peter.maydell@linaro.org> References: <20200430115142.13430-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::334 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Keqian Zhu Replace "acpi-mem-hotplug" with "acpi-cpu-hotplug" Signed-off-by: Keqian Zhu Message-id: 20200413091552.62748-4-zhukeqian1@huawei.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/acpi/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c index e2c957ce008..3d6a500fb7e 100644 --- a/hw/acpi/cpu.c +++ b/hw/acpi/cpu.c @@ -222,7 +222,7 @@ void cpu_hotplug_hw_init(MemoryRegion *as, Object *owne= r, state->devs[i].arch_id =3D id_list->cpus[i].arch_id; } memory_region_init_io(&state->ctrl_reg, owner, &cpu_hotplug_ops, state, - "acpi-mem-hotplug", ACPI_CPU_HOTPLUG_REG_LEN); + "acpi-cpu-hotplug", ACPI_CPU_HOTPLUG_REG_LEN); memory_region_add_subregion(as, base_addr, &state->ctrl_reg); } =20 --=20 2.20.1 From nobody Thu May 2 02:03:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1588247676; cv=none; d=zohomail.com; s=zohoarc; b=VcTckZilaIbK8FGvu7TiNlKryZr+ly82wPJ2DdLg2dnyM0RUdpoTYZrzt0plJDzPDBrDiH4gjqRGNzvvJTQpMVlLRqhCJLSqrwSFG6CzxOMWUOKrcJKCA7k/WK8SK6LvqEt2mI/gdy8CjleXKWZjlJaHNKyRxprljufNSUbp29E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588247676; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0v9TpXWCdSPPaJnxlOPd5RjkqBA9i10UdAk+4sFnELg=; b=grQIlOnFVDAwafG4S/tnHhXDhAIjDAkWKhS6vEcKy9JF8keOkJRbcWwrx8NMrlhM2oRz1bwhgb/UB+xUDmmIqwVPtmfqtEyC2gD+hsIuu09FB29qJFL3qvLN1/Dbm36G3mE/G7pp8ZNYpxPLwZo97CNp2w7ce/cwB73o1Q84Xao= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1588247676326199.1694104963873; Thu, 30 Apr 2020 04:54:36 -0700 (PDT) Received: from localhost ([::1]:43718 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU7ly-00084M-U7 for importer@patchew.org; Thu, 30 Apr 2020 07:54:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33708) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU7jP-0002gi-Jx for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:51:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.90_1) (envelope-from ) id 1jU7jN-0000KN-RB for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:51:55 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:34397) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jU7jN-0000Jw-B5 for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:51:53 -0400 Received: by mail-wr1-x432.google.com with SMTP id j1so6545825wrt.1 for ; Thu, 30 Apr 2020 04:51:52 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j22sm491518wre.84.2020.04.30.04.51.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 04:51:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=0v9TpXWCdSPPaJnxlOPd5RjkqBA9i10UdAk+4sFnELg=; b=i9NpVkxDTWBHD9GGY5OAN1iCrHrCT0IUjTUAOyDn/8Ynjk16+3EfpEbVDcVyvOib+N gyVaENRnSyJvjTBByWYRTwtooDglSYwwLnq24PtqSgGbkBauJ8+iaEhyHEDzIIfB9t0N I60rwey17Exve6gxPRgu1icEqZzQB87R+lw6I1qGG9MAKVlplf4LF0YaFm1ahST8Z9XN b3AbOQC6qvWB8KBMXfoBbuUU9XMdoB1TgGDyieQxcBWIk6dBcELy6t+5NI2fsvQ1I2Xf 1fIBum/utkbvJJ1TWUtS5E0f2dKVm/hs1iQpEBI6VaVjbUyQcgckkTeFNl6TegaHRjV2 NBUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0v9TpXWCdSPPaJnxlOPd5RjkqBA9i10UdAk+4sFnELg=; b=iO3qGZvQgPU5O7yNhekAtibt6mlzg89GZ1Go6356v7Crm7KQuYNBU1B7glDXEXmwX7 H9k7K2T4KYLMBY0x4lKukJxEJtGfBiesnik7MTJViDpC+IxW6yQ4TYUA70innngc4/U+ U/cPhXMF8nzhc8CBh5MJ7W/wZXnTpAD1uv7hkiWcZF4EDUzzecux+wbHhDblWMiAwREd i37/dcJLcHWdG1CIwG1GN5bWk85JfAeHQt0ul3NWYmXh7E2lBP1ui9m9TqLOqX2z+JI6 zHaSI5laLkOkFICIazlcEjotiWCUwD4C3WpucnZ423VxIO/xkncGLa1SAbelHE7FyQ98 sEPA== X-Gm-Message-State: AGi0PubNTaUgN99FubyD4l7Hq8mlAzpQ1Qw7H5QmhGprI8W1iLU2AN7I OyTFjJLlw2WugM0kjkDZrlIJ/c3cPLZtOQ== X-Google-Smtp-Source: APiQypLTxq+l/5GTDvcKKeVvBDhtA2I7jSW+Dg6jAeb5i2lujhco8LbfrxQuw+TCUk51B+ElnBlk6Q== X-Received: by 2002:adf:a151:: with SMTP id r17mr408762wrr.161.1588247511039; Thu, 30 Apr 2020 04:51:51 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/31] hw/net: Add Smartfusion2 emac block Date: Thu, 30 Apr 2020 12:51:17 +0100 Message-Id: <20200430115142.13430-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200430115142.13430-1-peter.maydell@linaro.org> References: <20200430115142.13430-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::432 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Subbaraya Sundeep Modelled Ethernet MAC of Smartfusion2 SoC. Micrel KSZ8051 PHY is present on Emcraft's SOM kit hence same PHY is emulated. Signed-off-by: Subbaraya Sundeep Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Message-id: 1587048891-30493-2-git-send-email-sundeep.lkml@gmail.com Signed-off-by: Peter Maydell --- hw/net/Makefile.objs | 1 + include/hw/net/msf2-emac.h | 53 ++++ hw/net/msf2-emac.c | 589 +++++++++++++++++++++++++++++++++++++ MAINTAINERS | 2 + 4 files changed, 645 insertions(+) create mode 100644 include/hw/net/msf2-emac.h create mode 100644 hw/net/msf2-emac.c diff --git a/hw/net/Makefile.objs b/hw/net/Makefile.objs index af4d1948666..f2b73983eec 100644 --- a/hw/net/Makefile.objs +++ b/hw/net/Makefile.objs @@ -55,3 +55,4 @@ common-obj-$(CONFIG_ROCKER) +=3D rocker/rocker.o rocker/r= ocker_fp.o \ obj-$(call lnot,$(CONFIG_ROCKER)) +=3D rocker/qmp-norocker.o =20 common-obj-$(CONFIG_CAN_BUS) +=3D can/ +common-obj-$(CONFIG_MSF2) +=3D msf2-emac.o diff --git a/include/hw/net/msf2-emac.h b/include/hw/net/msf2-emac.h new file mode 100644 index 00000000000..37966d3a813 --- /dev/null +++ b/include/hw/net/msf2-emac.h @@ -0,0 +1,53 @@ +/* + * QEMU model of the Smartfusion2 Ethernet MAC. + * + * Copyright (c) 2020 Subbaraya Sundeep . + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "hw/sysbus.h" +#include "exec/memory.h" +#include "net/net.h" +#include "net/eth.h" + +#define TYPE_MSS_EMAC "msf2-emac" +#define MSS_EMAC(obj) \ + OBJECT_CHECK(MSF2EmacState, (obj), TYPE_MSS_EMAC) + +#define R_MAX (0x1a0 / 4) +#define PHY_MAX_REGS 32 + +typedef struct MSF2EmacState { + SysBusDevice parent; + + MemoryRegion mmio; + MemoryRegion *dma_mr; + AddressSpace dma_as; + + qemu_irq irq; + NICState *nic; + NICConf conf; + + uint8_t mac_addr[ETH_ALEN]; + uint32_t rx_desc; + uint16_t phy_regs[PHY_MAX_REGS]; + + uint32_t regs[R_MAX]; +} MSF2EmacState; diff --git a/hw/net/msf2-emac.c b/hw/net/msf2-emac.c new file mode 100644 index 00000000000..32ba9e84124 --- /dev/null +++ b/hw/net/msf2-emac.c @@ -0,0 +1,589 @@ +/* + * QEMU model of the Smartfusion2 Ethernet MAC. + * + * Copyright (c) 2020 Subbaraya Sundeep . + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + * + * Refer to section Ethernet MAC in the document: + * UG0331: SmartFusion2 Microcontroller Subsystem User Guide + * Datasheet URL: + * https://www.microsemi.com/document-portal/cat_view/56661-internal-docum= ents/ + * 56758-soc?lang=3Den&limit=3D20&limitstart=3D220 + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "exec/address-spaces.h" +#include "hw/registerfields.h" +#include "hw/net/msf2-emac.h" +#include "hw/net/mii.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "migration/vmstate.h" + +REG32(CFG1, 0x0) + FIELD(CFG1, RESET, 31, 1) + FIELD(CFG1, RX_EN, 2, 1) + FIELD(CFG1, TX_EN, 0, 1) + FIELD(CFG1, LB_EN, 8, 1) +REG32(CFG2, 0x4) +REG32(IFG, 0x8) +REG32(HALF_DUPLEX, 0xc) +REG32(MAX_FRAME_LENGTH, 0x10) +REG32(MII_CMD, 0x24) + FIELD(MII_CMD, READ, 0, 1) +REG32(MII_ADDR, 0x28) + FIELD(MII_ADDR, REGADDR, 0, 5) + FIELD(MII_ADDR, PHYADDR, 8, 5) +REG32(MII_CTL, 0x2c) +REG32(MII_STS, 0x30) +REG32(STA1, 0x40) +REG32(STA2, 0x44) +REG32(FIFO_CFG0, 0x48) +REG32(FIFO_CFG4, 0x58) + FIELD(FIFO_CFG4, BCAST, 9, 1) + FIELD(FIFO_CFG4, MCAST, 8, 1) +REG32(FIFO_CFG5, 0x5C) + FIELD(FIFO_CFG5, BCAST, 9, 1) + FIELD(FIFO_CFG5, MCAST, 8, 1) +REG32(DMA_TX_CTL, 0x180) + FIELD(DMA_TX_CTL, EN, 0, 1) +REG32(DMA_TX_DESC, 0x184) +REG32(DMA_TX_STATUS, 0x188) + FIELD(DMA_TX_STATUS, PKTCNT, 16, 8) + FIELD(DMA_TX_STATUS, UNDERRUN, 1, 1) + FIELD(DMA_TX_STATUS, PKT_SENT, 0, 1) +REG32(DMA_RX_CTL, 0x18c) + FIELD(DMA_RX_CTL, EN, 0, 1) +REG32(DMA_RX_DESC, 0x190) +REG32(DMA_RX_STATUS, 0x194) + FIELD(DMA_RX_STATUS, PKTCNT, 16, 8) + FIELD(DMA_RX_STATUS, OVERFLOW, 2, 1) + FIELD(DMA_RX_STATUS, PKT_RCVD, 0, 1) +REG32(DMA_IRQ_MASK, 0x198) +REG32(DMA_IRQ, 0x19c) + +#define EMPTY_MASK (1 << 31) +#define PKT_SIZE 0x7FF +#define PHYADDR 0x1 +#define MAX_PKT_SIZE 2048 + +typedef struct { + uint32_t pktaddr; + uint32_t pktsize; + uint32_t next; +} EmacDesc; + +static uint32_t emac_get_isr(MSF2EmacState *s) +{ + uint32_t ier =3D s->regs[R_DMA_IRQ_MASK]; + uint32_t tx =3D s->regs[R_DMA_TX_STATUS] & 0xF; + uint32_t rx =3D s->regs[R_DMA_RX_STATUS] & 0xF; + uint32_t isr =3D (rx << 4) | tx; + + s->regs[R_DMA_IRQ] =3D ier & isr; + return s->regs[R_DMA_IRQ]; +} + +static void emac_update_irq(MSF2EmacState *s) +{ + bool intr =3D emac_get_isr(s); + + qemu_set_irq(s->irq, intr); +} + +static void emac_load_desc(MSF2EmacState *s, EmacDesc *d, hwaddr desc) +{ + address_space_read(&s->dma_as, desc, MEMTXATTRS_UNSPECIFIED, d, sizeof= *d); + /* Convert from LE into host endianness. */ + d->pktaddr =3D le32_to_cpu(d->pktaddr); + d->pktsize =3D le32_to_cpu(d->pktsize); + d->next =3D le32_to_cpu(d->next); +} + +static void emac_store_desc(MSF2EmacState *s, EmacDesc *d, hwaddr desc) +{ + /* Convert from host endianness into LE. */ + d->pktaddr =3D cpu_to_le32(d->pktaddr); + d->pktsize =3D cpu_to_le32(d->pktsize); + d->next =3D cpu_to_le32(d->next); + + address_space_write(&s->dma_as, desc, MEMTXATTRS_UNSPECIFIED, d, sizeo= f *d); +} + +static void msf2_dma_tx(MSF2EmacState *s) +{ + NetClientState *nc =3D qemu_get_queue(s->nic); + hwaddr desc =3D s->regs[R_DMA_TX_DESC]; + uint8_t buf[MAX_PKT_SIZE]; + EmacDesc d; + int size; + uint8_t pktcnt; + uint32_t status; + + if (!(s->regs[R_CFG1] & R_CFG1_TX_EN_MASK)) { + return; + } + + while (1) { + emac_load_desc(s, &d, desc); + if (d.pktsize & EMPTY_MASK) { + break; + } + size =3D d.pktsize & PKT_SIZE; + address_space_read(&s->dma_as, d.pktaddr, MEMTXATTRS_UNSPECIFIED, + buf, size); + /* + * This is very basic way to send packets. Ideally there should be + * a FIFO and packets should be sent out from FIFO only when + * R_CFG1 bit 0 is set. + */ + if (s->regs[R_CFG1] & R_CFG1_LB_EN_MASK) { + nc->info->receive(nc, buf, size); + } else { + qemu_send_packet(nc, buf, size); + } + d.pktsize |=3D EMPTY_MASK; + emac_store_desc(s, &d, desc); + /* update sent packets count */ + status =3D s->regs[R_DMA_TX_STATUS]; + pktcnt =3D FIELD_EX32(status, DMA_TX_STATUS, PKTCNT); + pktcnt++; + s->regs[R_DMA_TX_STATUS] =3D FIELD_DP32(status, DMA_TX_STATUS, + PKTCNT, pktcnt); + s->regs[R_DMA_TX_STATUS] |=3D R_DMA_TX_STATUS_PKT_SENT_MASK; + desc =3D d.next; + } + s->regs[R_DMA_TX_STATUS] |=3D R_DMA_TX_STATUS_UNDERRUN_MASK; + s->regs[R_DMA_TX_CTL] &=3D ~R_DMA_TX_CTL_EN_MASK; +} + +static void msf2_phy_update_link(MSF2EmacState *s) +{ + /* Autonegotiation status mirrors link status. */ + if (qemu_get_queue(s->nic)->link_down) { + s->phy_regs[MII_BMSR] &=3D ~(MII_BMSR_AN_COMP | + MII_BMSR_LINK_ST); + } else { + s->phy_regs[MII_BMSR] |=3D (MII_BMSR_AN_COMP | + MII_BMSR_LINK_ST); + } +} + +static void msf2_phy_reset(MSF2EmacState *s) +{ + memset(&s->phy_regs[0], 0, sizeof(s->phy_regs)); + s->phy_regs[MII_BMCR] =3D 0x1140; + s->phy_regs[MII_BMSR] =3D 0x7968; + s->phy_regs[MII_PHYID1] =3D 0x0022; + s->phy_regs[MII_PHYID2] =3D 0x1550; + s->phy_regs[MII_ANAR] =3D 0x01E1; + s->phy_regs[MII_ANLPAR] =3D 0xCDE1; + + msf2_phy_update_link(s); +} + +static void write_to_phy(MSF2EmacState *s) +{ + uint8_t reg_addr =3D s->regs[R_MII_ADDR] & R_MII_ADDR_REGADDR_MASK; + uint8_t phy_addr =3D (s->regs[R_MII_ADDR] >> R_MII_ADDR_PHYADDR_SHIFT)= & + R_MII_ADDR_REGADDR_MASK; + uint16_t data =3D s->regs[R_MII_CTL] & 0xFFFF; + + if (phy_addr !=3D PHYADDR) { + return; + } + + switch (reg_addr) { + case MII_BMCR: + if (data & MII_BMCR_RESET) { + /* Phy reset */ + msf2_phy_reset(s); + data &=3D ~MII_BMCR_RESET; + } + if (data & MII_BMCR_AUTOEN) { + /* Complete autonegotiation immediately */ + data &=3D ~MII_BMCR_AUTOEN; + s->phy_regs[MII_BMSR] |=3D MII_BMSR_AN_COMP; + } + break; + } + + s->phy_regs[reg_addr] =3D data; +} + +static uint16_t read_from_phy(MSF2EmacState *s) +{ + uint8_t reg_addr =3D s->regs[R_MII_ADDR] & R_MII_ADDR_REGADDR_MASK; + uint8_t phy_addr =3D (s->regs[R_MII_ADDR] >> R_MII_ADDR_PHYADDR_SHIFT)= & + R_MII_ADDR_REGADDR_MASK; + + if (phy_addr =3D=3D PHYADDR) { + return s->phy_regs[reg_addr]; + } else { + return 0xFFFF; + } +} + +static void msf2_emac_do_reset(MSF2EmacState *s) +{ + memset(&s->regs[0], 0, sizeof(s->regs)); + s->regs[R_CFG1] =3D 0x80000000; + s->regs[R_CFG2] =3D 0x00007000; + s->regs[R_IFG] =3D 0x40605060; + s->regs[R_HALF_DUPLEX] =3D 0x00A1F037; + s->regs[R_MAX_FRAME_LENGTH] =3D 0x00000600; + s->regs[R_FIFO_CFG5] =3D 0X3FFFF; + + msf2_phy_reset(s); +} + +static uint64_t emac_read(void *opaque, hwaddr addr, unsigned int size) +{ + MSF2EmacState *s =3D opaque; + uint32_t r =3D 0; + + addr >>=3D 2; + + switch (addr) { + case R_DMA_IRQ: + r =3D emac_get_isr(s); + break; + default: + if (addr >=3D ARRAY_SIZE(s->regs)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, + addr * 4); + return r; + } + r =3D s->regs[addr]; + break; + } + return r; +} + +static void emac_write(void *opaque, hwaddr addr, uint64_t val64, + unsigned int size) +{ + MSF2EmacState *s =3D opaque; + uint32_t value =3D val64; + uint32_t enreqbits; + uint8_t pktcnt; + + addr >>=3D 2; + switch (addr) { + case R_DMA_TX_CTL: + s->regs[addr] =3D value; + if (value & R_DMA_TX_CTL_EN_MASK) { + msf2_dma_tx(s); + } + break; + case R_DMA_RX_CTL: + s->regs[addr] =3D value; + if (value & R_DMA_RX_CTL_EN_MASK) { + s->rx_desc =3D s->regs[R_DMA_RX_DESC]; + qemu_flush_queued_packets(qemu_get_queue(s->nic)); + } + break; + case R_CFG1: + s->regs[addr] =3D value; + if (value & R_CFG1_RESET_MASK) { + msf2_emac_do_reset(s); + } + break; + case R_FIFO_CFG0: + /* + * For our implementation, turning on modules is instantaneous, + * so the states requested via the *ENREQ bits appear in the + * *ENRPLY bits immediately. Also the reset bits to reset PE-MCXMAC + * module are not emulated here since it deals with start of frames, + * inter-packet gap and control frames. + */ + enreqbits =3D extract32(value, 8, 5); + s->regs[addr] =3D deposit32(value, 16, 5, enreqbits); + break; + case R_DMA_TX_DESC: + if (value & 0x3) { + qemu_log_mask(LOG_GUEST_ERROR, "Tx Descriptor address should b= e" + " 32 bit aligned\n"); + } + /* Ignore [1:0] bits */ + s->regs[addr] =3D value & ~3; + break; + case R_DMA_RX_DESC: + if (value & 0x3) { + qemu_log_mask(LOG_GUEST_ERROR, "Rx Descriptor address should b= e" + " 32 bit aligned\n"); + } + /* Ignore [1:0] bits */ + s->regs[addr] =3D value & ~3; + break; + case R_DMA_TX_STATUS: + if (value & R_DMA_TX_STATUS_UNDERRUN_MASK) { + s->regs[addr] &=3D ~R_DMA_TX_STATUS_UNDERRUN_MASK; + } + if (value & R_DMA_TX_STATUS_PKT_SENT_MASK) { + pktcnt =3D FIELD_EX32(s->regs[addr], DMA_TX_STATUS, PKTCNT); + pktcnt--; + s->regs[addr] =3D FIELD_DP32(s->regs[addr], DMA_TX_STATUS, + PKTCNT, pktcnt); + if (pktcnt =3D=3D 0) { + s->regs[addr] &=3D ~R_DMA_TX_STATUS_PKT_SENT_MASK; + } + } + break; + case R_DMA_RX_STATUS: + if (value & R_DMA_RX_STATUS_OVERFLOW_MASK) { + s->regs[addr] &=3D ~R_DMA_RX_STATUS_OVERFLOW_MASK; + } + if (value & R_DMA_RX_STATUS_PKT_RCVD_MASK) { + pktcnt =3D FIELD_EX32(s->regs[addr], DMA_RX_STATUS, PKTCNT); + pktcnt--; + s->regs[addr] =3D FIELD_DP32(s->regs[addr], DMA_RX_STATUS, + PKTCNT, pktcnt); + if (pktcnt =3D=3D 0) { + s->regs[addr] &=3D ~R_DMA_RX_STATUS_PKT_RCVD_MASK; + } + } + break; + case R_DMA_IRQ: + break; + case R_MII_CMD: + if (value & R_MII_CMD_READ_MASK) { + s->regs[R_MII_STS] =3D read_from_phy(s); + } + break; + case R_MII_CTL: + s->regs[addr] =3D value; + write_to_phy(s); + break; + case R_STA1: + s->regs[addr] =3D value; + /* + * R_STA1 [31:24] : octet 1 of mac address + * R_STA1 [23:16] : octet 2 of mac address + * R_STA1 [15:8] : octet 3 of mac address + * R_STA1 [7:0] : octet 4 of mac address + */ + stl_be_p(s->mac_addr, value); + break; + case R_STA2: + s->regs[addr] =3D value; + /* + * R_STA2 [31:24] : octet 5 of mac address + * R_STA2 [23:16] : octet 6 of mac address + */ + stw_be_p(s->mac_addr + 4, value >> 16); + break; + default: + if (addr >=3D ARRAY_SIZE(s->regs)) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Bad offset 0x%" HWADDR_PRIx "\n", __func__, + addr * 4); + return; + } + s->regs[addr] =3D value; + break; + } + emac_update_irq(s); +} + +static const MemoryRegionOps emac_ops =3D { + .read =3D emac_read, + .write =3D emac_write, + .endianness =3D DEVICE_NATIVE_ENDIAN, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 4 + } +}; + +static bool emac_can_rx(NetClientState *nc) +{ + MSF2EmacState *s =3D qemu_get_nic_opaque(nc); + + return (s->regs[R_CFG1] & R_CFG1_RX_EN_MASK) && + (s->regs[R_DMA_RX_CTL] & R_DMA_RX_CTL_EN_MASK); +} + +static bool addr_filter_ok(MSF2EmacState *s, const uint8_t *buf) +{ + /* The broadcast MAC address: FF:FF:FF:FF:FF:FF */ + const uint8_t broadcast_addr[] =3D { 0xFF, 0xFF, 0xFF, 0xFF, + 0xFF, 0xFF }; + bool bcast_en =3D true; + bool mcast_en =3D true; + + if (s->regs[R_FIFO_CFG5] & R_FIFO_CFG5_BCAST_MASK) { + bcast_en =3D true; /* Broadcast dont care for drop circuitry */ + } else if (s->regs[R_FIFO_CFG4] & R_FIFO_CFG4_BCAST_MASK) { + bcast_en =3D false; + } + + if (s->regs[R_FIFO_CFG5] & R_FIFO_CFG5_MCAST_MASK) { + mcast_en =3D true; /* Multicast dont care for drop circuitry */ + } else if (s->regs[R_FIFO_CFG4] & R_FIFO_CFG4_MCAST_MASK) { + mcast_en =3D false; + } + + if (!memcmp(buf, broadcast_addr, sizeof(broadcast_addr))) { + return bcast_en; + } + + if (buf[0] & 1) { + return mcast_en; + } + + return !memcmp(buf, s->mac_addr, sizeof(s->mac_addr)); +} + +static ssize_t emac_rx(NetClientState *nc, const uint8_t *buf, size_t size) +{ + MSF2EmacState *s =3D qemu_get_nic_opaque(nc); + EmacDesc d; + uint8_t pktcnt; + uint32_t status; + + if (size > (s->regs[R_MAX_FRAME_LENGTH] & 0xFFFF)) { + return size; + } + if (!addr_filter_ok(s, buf)) { + return size; + } + + emac_load_desc(s, &d, s->rx_desc); + + if (d.pktsize & EMPTY_MASK) { + address_space_write(&s->dma_as, d.pktaddr, MEMTXATTRS_UNSPECIFIED, + buf, size & PKT_SIZE); + d.pktsize =3D size & PKT_SIZE; + emac_store_desc(s, &d, s->rx_desc); + /* update received packets count */ + status =3D s->regs[R_DMA_RX_STATUS]; + pktcnt =3D FIELD_EX32(status, DMA_RX_STATUS, PKTCNT); + pktcnt++; + s->regs[R_DMA_RX_STATUS] =3D FIELD_DP32(status, DMA_RX_STATUS, + PKTCNT, pktcnt); + s->regs[R_DMA_RX_STATUS] |=3D R_DMA_RX_STATUS_PKT_RCVD_MASK; + s->rx_desc =3D d.next; + } else { + s->regs[R_DMA_RX_CTL] &=3D ~R_DMA_RX_CTL_EN_MASK; + s->regs[R_DMA_RX_STATUS] |=3D R_DMA_RX_STATUS_OVERFLOW_MASK; + } + emac_update_irq(s); + return size; +} + +static void msf2_emac_reset(DeviceState *dev) +{ + MSF2EmacState *s =3D MSS_EMAC(dev); + + msf2_emac_do_reset(s); +} + +static void emac_set_link(NetClientState *nc) +{ + MSF2EmacState *s =3D qemu_get_nic_opaque(nc); + + msf2_phy_update_link(s); +} + +static NetClientInfo net_msf2_emac_info =3D { + .type =3D NET_CLIENT_DRIVER_NIC, + .size =3D sizeof(NICState), + .can_receive =3D emac_can_rx, + .receive =3D emac_rx, + .link_status_changed =3D emac_set_link, +}; + +static void msf2_emac_realize(DeviceState *dev, Error **errp) +{ + MSF2EmacState *s =3D MSS_EMAC(dev); + + if (!s->dma_mr) { + error_setg(errp, "MSS_EMAC 'ahb-bus' link not set"); + return; + } + + address_space_init(&s->dma_as, s->dma_mr, "emac-ahb"); + + qemu_macaddr_default_if_unset(&s->conf.macaddr); + s->nic =3D qemu_new_nic(&net_msf2_emac_info, &s->conf, + object_get_typename(OBJECT(dev)), dev->id, s); + qemu_format_nic_info_str(qemu_get_queue(s->nic), s->conf.macaddr.a); +} + +static void msf2_emac_init(Object *obj) +{ + MSF2EmacState *s =3D MSS_EMAC(obj); + + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->irq); + + memory_region_init_io(&s->mmio, obj, &emac_ops, s, + "msf2-emac", R_MAX * 4); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); +} + +static Property msf2_emac_properties[] =3D { + DEFINE_PROP_LINK("ahb-bus", MSF2EmacState, dma_mr, + TYPE_MEMORY_REGION, MemoryRegion *), + DEFINE_NIC_PROPERTIES(MSF2EmacState, conf), + DEFINE_PROP_END_OF_LIST(), +}; + +static const VMStateDescription vmstate_msf2_emac =3D { + .name =3D TYPE_MSS_EMAC, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT8_ARRAY(mac_addr, MSF2EmacState, ETH_ALEN), + VMSTATE_UINT32(rx_desc, MSF2EmacState), + VMSTATE_UINT16_ARRAY(phy_regs, MSF2EmacState, PHY_MAX_REGS), + VMSTATE_UINT32_ARRAY(regs, MSF2EmacState, R_MAX), + VMSTATE_END_OF_LIST() + } +}; + +static void msf2_emac_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->realize =3D msf2_emac_realize; + dc->reset =3D msf2_emac_reset; + dc->vmsd =3D &vmstate_msf2_emac; + device_class_set_props(dc, msf2_emac_properties); +} + +static const TypeInfo msf2_emac_info =3D { + .name =3D TYPE_MSS_EMAC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(MSF2EmacState), + .instance_init =3D msf2_emac_init, + .class_init =3D msf2_emac_class_init, +}; + +static void msf2_emac_register_types(void) +{ + type_register_static(&msf2_emac_info); +} + +type_init(msf2_emac_register_types) diff --git a/MAINTAINERS b/MAINTAINERS index 8cbc1fac2bf..cea57331fe8 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -919,6 +919,8 @@ F: include/hw/arm/msf2-soc.h F: include/hw/misc/msf2-sysreg.h F: include/hw/timer/mss-timer.h F: include/hw/ssi/mss-spi.h +F: hw/net/msf2-emac.c +F: include/hw/net/msf2-emac.h =20 Emcraft M2S-FG484 M: Subbaraya Sundeep --=20 2.20.1 From nobody Thu May 2 02:03:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j22sm491518wre.84.2020.04.30.04.51.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 04:51:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=E6VqovrvHpgQrx8t2mX5Zs5JVaWsOq4hn1vYLIHJajw=; b=oVMjoUW/k8Bxe1ItZhqBkmLhKz+RGLhk98isVWoAjpXcl7doohab4OB7Rgbjz1j4b4 4FqxSwbfgNiqNV+UncUW0g9QotwsOfZA0zfsBLNn9dV9maTQwRCINUyYv0ATqesmuXDB woJQkwzpbRBrnAls+3GLn+WgfPENjD4b9eX48aCUf4yz+XnQq28d809kR0pYoORHBzLL is+Z7WvUEFsuoFgkWyXvkgULdDkFdpnaKxg8PirY7Bw8pnEWX5oaR/voRNlIuQ1yz5/Y fSDRuRnOD1gBPk3s4p0LLCuAcODb18EUu6YOLeRwC/4ZtfH4kiqiCkRsVLQFkLas/Ru4 d2rQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=E6VqovrvHpgQrx8t2mX5Zs5JVaWsOq4hn1vYLIHJajw=; b=oEBtBAyqaYqmD6QWPc2+5BsRUvZ+RwPEJzl1NR/jSM7MNN70WghGi/F4IT55piz6ii ag19Cwh0BjMH7qXv//WbgFl3k1dNOlxkVNB6AlJH+WebJrnesjJ9UfOOVc1NdZ01x5TT 3KG0WvLa8fzLY/dsahe/0zRSUwt2lv4r3qsGqrBZPrn1YRPZg325+NzOXrzWCPJlr59Z vqFYXrC5uEidusgtRpC9rvnqaEOMnQcJMNyBYpCK7a8MqWFQGKwCB423CNQnY0cfVTmd dilQuKn1M378lIftVyDpW1IlUIMsG5/NSkDfEVrGL5lFICrMhbrgvhzJuyJwqXPjD727 J2HQ== X-Gm-Message-State: AGi0PuapebpYPLhO47gV7u8XxO5gPQ167kFK126kgEXbMnXQcuFmXYqE D1bwP8OT7r9mwQ0lHQdbrxEn2VpcBIITOg== X-Google-Smtp-Source: APiQypKitfEk37QGTQwWq95EJVrf+vw01IZiB91q6Jt3lOWE6na/6VX2BSwmcw/wntVpqx3X8n40qA== X-Received: by 2002:a7b:c250:: with SMTP id b16mr2683559wmj.100.1588247511952; Thu, 30 Apr 2020 04:51:51 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/31] msf2: Add EMAC block to SmartFusion2 SoC Date: Thu, 30 Apr 2020 12:51:18 +0100 Message-Id: <20200430115142.13430-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200430115142.13430-1-peter.maydell@linaro.org> References: <20200430115142.13430-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x343.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Subbaraya Sundeep With SmartFusion2 Ethernet MAC model in place this patch adds the same to SoC. Signed-off-by: Subbaraya Sundeep Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Message-id: 1587048891-30493-3-git-send-email-sundeep.lkml@gmail.com Signed-off-by: Peter Maydell --- include/hw/arm/msf2-soc.h | 2 ++ hw/arm/msf2-soc.c | 26 ++++++++++++++++++++++++-- 2 files changed, 26 insertions(+), 2 deletions(-) diff --git a/include/hw/arm/msf2-soc.h b/include/hw/arm/msf2-soc.h index 3cfe5c76ee2..c9cb214aa67 100644 --- a/include/hw/arm/msf2-soc.h +++ b/include/hw/arm/msf2-soc.h @@ -29,6 +29,7 @@ #include "hw/timer/mss-timer.h" #include "hw/misc/msf2-sysreg.h" #include "hw/ssi/mss-spi.h" +#include "hw/net/msf2-emac.h" =20 #define TYPE_MSF2_SOC "msf2-soc" #define MSF2_SOC(obj) OBJECT_CHECK(MSF2State, (obj), TYPE_MSF2_SOC) @@ -62,6 +63,7 @@ typedef struct MSF2State { MSF2SysregState sysreg; MSSTimerState timer; MSSSpiState spi[MSF2_NUM_SPIS]; + MSF2EmacState emac; } MSF2State; =20 #endif diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c index 588d643b8d2..a455b8831ff 100644 --- a/hw/arm/msf2-soc.c +++ b/hw/arm/msf2-soc.c @@ -1,7 +1,7 @@ /* * SmartFusion2 SoC emulation. * - * Copyright (c) 2017 Subbaraya Sundeep + * Copyright (c) 2017-2020 Subbaraya Sundeep * * Permission is hereby granted, free of charge, to any person obtaining a= copy * of this software and associated documentation files (the "Software"), t= o deal @@ -35,11 +35,14 @@ =20 #define MSF2_TIMER_BASE 0x40004000 #define MSF2_SYSREG_BASE 0x40038000 +#define MSF2_EMAC_BASE 0x40041000 =20 #define ENVM_BASE_ADDRESS 0x60000000 =20 #define SRAM_BASE_ADDRESS 0x20000000 =20 +#define MSF2_EMAC_IRQ 12 + #define MSF2_ENVM_MAX_SIZE (512 * KiB) =20 /* @@ -81,6 +84,13 @@ static void m2sxxx_soc_initfn(Object *obj) sysbus_init_child_obj(obj, "spi[*]", &s->spi[i], sizeof(s->spi[i]), TYPE_MSS_SPI); } + + sysbus_init_child_obj(obj, "emac", &s->emac, sizeof(s->emac), + TYPE_MSS_EMAC); + if (nd_table[0].used) { + qemu_check_nic_model(&nd_table[0], TYPE_MSS_EMAC); + qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]); + } } =20 static void m2sxxx_soc_realize(DeviceState *dev_soc, Error **errp) @@ -192,6 +202,19 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, E= rror **errp) g_free(bus_name); } =20 + dev =3D DEVICE(&s->emac); + object_property_set_link(OBJECT(&s->emac), OBJECT(get_system_memory()), + "ahb-bus", &error_abort); + object_property_set_bool(OBJECT(&s->emac), true, "realized", &err); + if (err !=3D NULL) { + error_propagate(errp, err); + return; + } + busdev =3D SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, MSF2_EMAC_BASE); + sysbus_connect_irq(busdev, 0, + qdev_get_gpio_in(armv7m, MSF2_EMAC_IRQ)); + /* Below devices are not modelled yet. */ create_unimplemented_device("i2c_0", 0x40002000, 0x1000); create_unimplemented_device("dma", 0x40003000, 0x1000); @@ -202,7 +225,6 @@ static void m2sxxx_soc_realize(DeviceState *dev_soc, Er= ror **errp) create_unimplemented_device("can", 0x40015000, 0x1000); create_unimplemented_device("rtc", 0x40017000, 0x1000); create_unimplemented_device("apb_config", 0x40020000, 0x10000); - create_unimplemented_device("emac", 0x40041000, 0x1000); create_unimplemented_device("usb", 0x40043000, 0x1000); } =20 --=20 2.20.1 From nobody Thu May 2 02:03:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1588247899; cv=none; d=zohomail.com; s=zohoarc; b=FBE0aiiw0gb0HbeAB1bnQysWXdPa0/Jg6h8CF/d+tVg6wRZCjvYhzJ1aSUhQeOMXdKYE8qM20JaG47a1/6FFHnQMszSH7QNDv1ddDLLvQdKscBuMNIMHUiNWz8pBFT2mmCFKF1Mijj1lYX8cI42QR62f4C5B/pMy2e9UK7vQlec= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588247899; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j22sm491518wre.84.2020.04.30.04.51.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 04:51:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ZY3oMjv55jr/fCB1Ius33wty91gBP4lyCC8NXchsQCk=; b=GW855yhiQ/G+Tgqu1ge2CJ73AllYTqSh1GYGxr993CJUpbw0FWIeqD/MfTNbB3OF5l JQyTYIf0MlRxGTc1X0exRDrHusKswylZap2YGlgUgEUto1NBxjXNRlZCotwuaeXLeoi3 wU5TRdsjqx7AOm6VN3WL6vQoLi58QrurOQapHAyv7KdE86F7jTGDBTuE2zh0qD6WIDlD 3ZrhhgdClmKZDr+jBgd/YSTA3Smy7wMLBaK72ZXNmVtM+sU5Jw2MVzzgC/2zn5FCXkzh 00Rsj/ELGFHTC3/Bjs2asADnOHFCPcFWFAKbsArht7nGoOTP+Icfw+k1Pg5VDsj6XoSi tEEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZY3oMjv55jr/fCB1Ius33wty91gBP4lyCC8NXchsQCk=; b=RBonOXnktXZik9+lysyStykfrIvQaLQ0mQJsLLWJzhKpEzquDzw7YtEJhDgEftK6jm GtdE3SsUxZimVhcCnuhQSz/tGWh2Qz8PEy+R9FXnaF9uGkEV+mDryfPKsDNeLsnlF1w6 MKoycj1sbHPr6oc7UuqsKBKWVcB0A/cRyHvpDHQsWuMKkzUmmFQsT+QDvW7Gvqljnk+5 lKYwhtM2P7xEyd1BJwZQT85DfpJL9ge3UOKiSuq03zuXu1m4GuiNWNpIUrK7y4EgWUGZ LR93J6sj3DsOACO2zIaG4k77Iac9EYsrO85SFBiTPZ3lzqqu+DID6Y5NZAJCmH/tsqRo HXZA== X-Gm-Message-State: AGi0Publdqm1LB7ihoeY0J6rS4mj1LhxUpbxM12lslt1gwZtCLYaWuY2 0MCboYYkp3aWcgbg/3R1m6fBJLu5Tf8/pQ== X-Google-Smtp-Source: APiQypIeF+WPRpvp5YyzXH2HwHUR2z6tjjiOoxFbD4x8xGODbW8YakA9zLroOpJNey5C5/tRE1VgCA== X-Received: by 2002:a05:600c:21ca:: with SMTP id x10mr2459382wmj.113.1588247513016; Thu, 30 Apr 2020 04:51:53 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/31] tests/boot_linux_console: Add ethernet test to SmartFusion2 Date: Thu, 30 Apr 2020 12:51:19 +0100 Message-Id: <20200430115142.13430-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200430115142.13430-1-peter.maydell@linaro.org> References: <20200430115142.13430-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::32b X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Subbaraya Sundeep In addition to simple serial test this patch uses ping to test the ethernet block modelled in SmartFusion2 SoC. Signed-off-by: Subbaraya Sundeep Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Message-id: 1587048891-30493-4-git-send-email-sundeep.lkml@gmail.com Signed-off-by: Peter Maydell --- tests/acceptance/boot_linux_console.py | 15 ++++++++++----- 1 file changed, 10 insertions(+), 5 deletions(-) diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot= _linux_console.py index f825cd9ef55..c6b06a1a138 100644 --- a/tests/acceptance/boot_linux_console.py +++ b/tests/acceptance/boot_linux_console.py @@ -336,13 +336,13 @@ class BootLinuxConsole(Test): """ uboot_url =3D ('https://raw.githubusercontent.com/' 'Subbaraya-Sundeep/qemu-test-binaries/' - 'fa030bd77a014a0b8e360d3b7011df89283a2f0b/u-boot') - uboot_hash =3D 'abba5d9c24cdd2d49cdc2a8aa92976cf20737eff' + 'fe371d32e50ca682391e1e70ab98c2942aeffb01/u-boot') + uboot_hash =3D 'cbb8cbab970f594bf6523b9855be209c08374ae2' uboot_path =3D self.fetch_asset(uboot_url, asset_hash=3Duboot_hash) spi_url =3D ('https://raw.githubusercontent.com/' 'Subbaraya-Sundeep/qemu-test-binaries/' - 'fa030bd77a014a0b8e360d3b7011df89283a2f0b/spi.bin') - spi_hash =3D '85f698329d38de63aea6e884a86fbde70890a78a' + 'fe371d32e50ca682391e1e70ab98c2942aeffb01/spi.bin') + spi_hash =3D '65523a1835949b6f4553be96dec1b6a38fb05501' spi_path =3D self.fetch_asset(spi_url, asset_hash=3Dspi_hash) =20 self.vm.set_console() @@ -352,7 +352,12 @@ class BootLinuxConsole(Test): '-drive', 'file=3D' + spi_path + ',if=3Dmtd,forma= t=3Draw', '-no-reboot') self.vm.launch() - self.wait_for_console_pattern('init started: BusyBox') + self.wait_for_console_pattern('Enter \'help\' for a list') + + exec_command_and_wait_for_pattern(self, 'ifconfig eth0 10.0.2.15', + 'eth0: link becomes ready= ') + exec_command_and_wait_for_pattern(self, 'ping -c 3 10.0.2.2', + '3 packets transmitted, 3 packets received, 0% packet loss') =20 def do_test_arm_raspi2(self, uart_id): """ --=20 2.20.1 From nobody Thu May 2 02:03:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1588247673; cv=none; d=zohomail.com; s=zohoarc; b=ae9TW45fA6k26LnFtiFEtxTY/syWhFDZ9AWJtnTp0xPP3vOpTY8MXO8FF4U9qhyWSiDvBgH7ee4TBy3XHsXxvi/tV09V/4sdEzBXqCrrQyC2fv3kgHSJgTFzFuR+Ws65AwDH5+hdwjWKiY946TPSfyDPg1TOrJjvkiyDstgyN/c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588247673; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=z48Jl8XNi25vJPB9v5ehJOLopLNYTyZOH6r0FLJ81ag=; b=a59JNmzZXv2qOpTD3ELpjWunGz+oZmocrIap9X9oQ6G+VwJEJ/T0fh6cEEweL35TwCebgQ8EIlJzyXiHJEW20+qWo4uZcDF1dt4cPgQeksKdjui+iaN5CAGHJ9yAUVqXUlVrE7pdtXcJwkZEnP3cegSJHyE7jbpjPuHmdsnaXZo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1588247672998836.1404797975304; Thu, 30 Apr 2020 04:54:32 -0700 (PDT) Received: from localhost ([::1]:43412 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU7lv-0007ww-Jb for importer@patchew.org; Thu, 30 Apr 2020 07:54:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33778) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU7jX-0002sC-RF for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:07 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.90_1) (envelope-from ) id 1jU7jU-0000Mb-7B for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:03 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:55905) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jU7jT-0000MD-BQ for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:51:59 -0400 Received: by mail-wm1-x336.google.com with SMTP id e26so1509146wmk.5 for ; Thu, 30 Apr 2020 04:51:58 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j22sm491518wre.84.2020.04.30.04.51.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 04:51:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=z48Jl8XNi25vJPB9v5ehJOLopLNYTyZOH6r0FLJ81ag=; b=yEyWGifOTqEjX/dkCDFH83szNND1rKp6dol01G414IZuFppeNTdSzMkCYDzh9Y9+KX 71egs29ey5IF07xxA/7cmWQCbIFG1kzfLGsBNrzShNOOKyK9CD5UJVjBmDHRC/lU5ZkK MOamOsPgUv2670SVIWQsKF0WEh8DOVyO72xZjxVeXu4F32qQ0JQ4DDPORpkef4yoqGvl E6+Z94LmfuZT7sJNSlqUnJ0nmeOZBn0XRI+YEO6JPNmD6ijIR6BZPiZ3TgIimIbc/brT p1JKs/JASUmydeFUZZWeyLaS4lic3xaSeSFgXTNvQk9IPcYVd9DaiirHkto8qYRPUW+r v1VA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=z48Jl8XNi25vJPB9v5ehJOLopLNYTyZOH6r0FLJ81ag=; b=C6n14Pnh84tAi8y3UaCOX6bePUOCAdiUIJuOSD9d6E6JtuhhJjiTD1/5pbxqYWVMsP +BoJYcrZF6fh9TKNCRAgbRDeI3gEfsq/M+E0SKHBJJ17MDNC0uD+sKFwRLGP3jQTHUFy XHY733u0G7S8/0mbAaCanbR7exDjLtfVsSTOv7xJQie+TB8siHjbWLbprl7855a4HoWi NFFZP9fuHKlvpqlzf9TcQMvVqfs3QzEhMqxEYb1iqDpEGxU88iKE9fjQ7v1wwiLWFT2A hxVGzWKlf7as5EV0dLfGBVkz/GkE9dd7E7+VAJFWr0MD7mHfapaUhz37BVBN44idYQ9N pGLw== X-Gm-Message-State: AGi0PuYuFV19+7fmh6QYOlENSK/7787Wc0v2JO2ZtDMswcC6CRbABFHH tzZKfGcT3MT0wUx4nLDw+dp56cXo7CIOyA== X-Google-Smtp-Source: APiQypK6hxVhci54lwKhNPoD4yEEvod7p7XYnNbfB+R3TFA+HUTwXfXLt9VkQYL6Dqx3SzT2Ix6fxw== X-Received: by 2002:a1c:9e43:: with SMTP id h64mr2565948wme.0.1588247514294; Thu, 30 Apr 2020 04:51:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/31] hw/core/clock: introduce clock object Date: Thu, 30 Apr 2020 12:51:20 +0100 Message-Id: <20200430115142.13430-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200430115142.13430-1-peter.maydell@linaro.org> References: <20200430115142.13430-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::336 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This object may be used to represent a clock inside a clock tree. A clock may be connected to another clock so that it receives update, through a callback, whenever the source/parent clock is updated. Although only the root clock of a clock tree controls the values (represented as periods) of all clocks in tree, each clock holds a local state containing the current value so that it can be fetched independently. It will allows us to fullfill migration requirements by migrating each clock independently of others. This is based on the original work of Frederic Konrad. Signed-off-by: Damien Hedde Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Message-id: 20200406135251.157596-2-damien.hedde@greensocs.com [PMM: Use uint64_t rather than unsigned long long in trace events; the dtrace backend can't handle the latter] Signed-off-by: Peter Maydell --- hw/core/Makefile.objs | 1 + include/hw/clock.h | 216 ++++++++++++++++++++++++++++++++++++++++++ hw/core/clock.c | 130 +++++++++++++++++++++++++ hw/core/trace-events | 7 ++ 4 files changed, 354 insertions(+) create mode 100644 include/hw/clock.h create mode 100644 hw/core/clock.c diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs index 6215e7c2085..1d9b0aa2057 100644 --- a/hw/core/Makefile.objs +++ b/hw/core/Makefile.objs @@ -7,6 +7,7 @@ common-obj-y +=3D hotplug.o common-obj-y +=3D vmstate-if.o # irq.o needed for qdev GPIO handling: common-obj-y +=3D irq.o +common-obj-y +=3D clock.o =20 common-obj-$(CONFIG_SOFTMMU) +=3D reset.o common-obj-$(CONFIG_SOFTMMU) +=3D qdev-fw.o diff --git a/include/hw/clock.h b/include/hw/clock.h new file mode 100644 index 00000000000..82a7f3c6982 --- /dev/null +++ b/include/hw/clock.h @@ -0,0 +1,216 @@ +/* + * Hardware Clocks + * + * Copyright GreenSocs 2016-2020 + * + * Authors: + * Frederic Konrad + * Damien Hedde + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef QEMU_HW_CLOCK_H +#define QEMU_HW_CLOCK_H + +#include "qom/object.h" +#include "qemu/queue.h" + +#define TYPE_CLOCK "clock" +#define CLOCK(obj) OBJECT_CHECK(Clock, (obj), TYPE_CLOCK) + +typedef void ClockCallback(void *opaque); + +/* + * clock store a value representing the clock's period in 2^-32ns unit. + * It can represent: + * + periods from 2^-32ns up to 4seconds + * + frequency from ~0.25Hz 2e10Ghz + * Resolution of frequency representation decreases with frequency: + * + at 100MHz, resolution is ~2mHz + * + at 1Ghz, resolution is ~0.2Hz + * + at 10Ghz, resolution is ~20Hz + */ +#define CLOCK_SECOND (1000000000llu << 32) + +/* + * macro helpers to convert to hertz / nanosecond + */ +#define CLOCK_PERIOD_FROM_NS(ns) ((ns) * (CLOCK_SECOND / 1000000000llu)) +#define CLOCK_PERIOD_TO_NS(per) ((per) / (CLOCK_SECOND / 1000000000llu)) +#define CLOCK_PERIOD_FROM_HZ(hz) (((hz) !=3D 0) ? CLOCK_SECOND / (hz) : 0u) +#define CLOCK_PERIOD_TO_HZ(per) (((per) !=3D 0) ? CLOCK_SECOND / (per) : 0= u) + +/** + * Clock: + * @parent_obj: parent class + * @period: unsigned integer representing the period of the clock + * @canonical_path: clock path string cache (used for trace purpose) + * @callback: called when clock changes + * @callback_opaque: argument for @callback + * @source: source (or parent in clock tree) of the clock + * @children: list of clocks connected to this one (it is their source) + * @sibling: structure used to form a clock list + */ + +typedef struct Clock Clock; + +struct Clock { + /*< private >*/ + Object parent_obj; + + /* all fields are private and should not be modified directly */ + + /* fields */ + uint64_t period; + char *canonical_path; + ClockCallback *callback; + void *callback_opaque; + + /* Clocks are organized in a clock tree */ + Clock *source; + QLIST_HEAD(, Clock) children; + QLIST_ENTRY(Clock) sibling; +}; + +/** + * clock_setup_canonical_path: + * @clk: clock + * + * compute the canonical path of the clock (used by log messages) + */ +void clock_setup_canonical_path(Clock *clk); + +/** + * clock_set_callback: + * @clk: the clock to register the callback into + * @cb: the callback function + * @opaque: the argument to the callback + * + * Register a callback called on every clock update. + */ +void clock_set_callback(Clock *clk, ClockCallback *cb, void *opaque); + +/** + * clock_clear_callback: + * @clk: the clock to delete the callback from + * + * Unregister the callback registered with clock_set_callback. + */ +void clock_clear_callback(Clock *clk); + +/** + * clock_set_source: + * @clk: the clock. + * @src: the source clock + * + * Setup @src as the clock source of @clk. The current @src period + * value is also copied to @clk and its subtree but no callback is + * called. + * Further @src update will be propagated to @clk and its subtree. + */ +void clock_set_source(Clock *clk, Clock *src); + +/** + * clock_set: + * @clk: the clock to initialize. + * @value: the clock's value, 0 means unclocked + * + * Set the local cached period value of @clk to @value. + */ +void clock_set(Clock *clk, uint64_t value); + +static inline void clock_set_hz(Clock *clk, unsigned hz) +{ + clock_set(clk, CLOCK_PERIOD_FROM_HZ(hz)); +} + +static inline void clock_set_ns(Clock *clk, unsigned ns) +{ + clock_set(clk, CLOCK_PERIOD_FROM_NS(ns)); +} + +/** + * clock_propagate: + * @clk: the clock + * + * Propagate the clock period that has been previously configured using + * @clock_set(). This will update recursively all connected clocks. + * It is an error to call this function on a clock which has a source. + * Note: this function must not be called during device inititialization + * or migration. + */ +void clock_propagate(Clock *clk); + +/** + * clock_update: + * @clk: the clock to update. + * @value: the new clock's value, 0 means unclocked + * + * Update the @clk to the new @value. All connected clocks will be informed + * of this update. This is equivalent to call @clock_set() then + * @clock_propagate(). + */ +static inline void clock_update(Clock *clk, uint64_t value) +{ + clock_set(clk, value); + clock_propagate(clk); +} + +static inline void clock_update_hz(Clock *clk, unsigned hz) +{ + clock_update(clk, CLOCK_PERIOD_FROM_HZ(hz)); +} + +static inline void clock_update_ns(Clock *clk, unsigned ns) +{ + clock_update(clk, CLOCK_PERIOD_FROM_NS(ns)); +} + +/** + * clock_get: + * @clk: the clk to fetch the clock + * + * @return: the current period. + */ +static inline uint64_t clock_get(const Clock *clk) +{ + return clk->period; +} + +static inline unsigned clock_get_hz(Clock *clk) +{ + return CLOCK_PERIOD_TO_HZ(clock_get(clk)); +} + +static inline unsigned clock_get_ns(Clock *clk) +{ + return CLOCK_PERIOD_TO_NS(clock_get(clk)); +} + +/** + * clock_is_enabled: + * @clk: a clock + * + * @return: true if the clock is running. + */ +static inline bool clock_is_enabled(const Clock *clk) +{ + return clock_get(clk) !=3D 0; +} + +static inline void clock_init(Clock *clk, uint64_t value) +{ + clock_set(clk, value); +} +static inline void clock_init_hz(Clock *clk, uint64_t value) +{ + clock_set_hz(clk, value); +} +static inline void clock_init_ns(Clock *clk, uint64_t value) +{ + clock_set_ns(clk, value); +} + +#endif /* QEMU_HW_CLOCK_H */ diff --git a/hw/core/clock.c b/hw/core/clock.c new file mode 100644 index 00000000000..3c0daf7d4cf --- /dev/null +++ b/hw/core/clock.c @@ -0,0 +1,130 @@ +/* + * Hardware Clocks + * + * Copyright GreenSocs 2016-2020 + * + * Authors: + * Frederic Konrad + * Damien Hedde + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "hw/clock.h" +#include "trace.h" + +#define CLOCK_PATH(_clk) (_clk->canonical_path) + +void clock_setup_canonical_path(Clock *clk) +{ + g_free(clk->canonical_path); + clk->canonical_path =3D object_get_canonical_path(OBJECT(clk)); +} + +void clock_set_callback(Clock *clk, ClockCallback *cb, void *opaque) +{ + clk->callback =3D cb; + clk->callback_opaque =3D opaque; +} + +void clock_clear_callback(Clock *clk) +{ + clock_set_callback(clk, NULL, NULL); +} + +void clock_set(Clock *clk, uint64_t period) +{ + trace_clock_set(CLOCK_PATH(clk), CLOCK_PERIOD_TO_NS(clk->period), + CLOCK_PERIOD_TO_NS(period)); + clk->period =3D period; +} + +static void clock_propagate_period(Clock *clk, bool call_callbacks) +{ + Clock *child; + + QLIST_FOREACH(child, &clk->children, sibling) { + if (child->period !=3D clk->period) { + child->period =3D clk->period; + trace_clock_update(CLOCK_PATH(child), CLOCK_PATH(clk), + CLOCK_PERIOD_TO_NS(clk->period), + call_callbacks); + if (call_callbacks && child->callback) { + child->callback(child->callback_opaque); + } + clock_propagate_period(child, call_callbacks); + } + } +} + +void clock_propagate(Clock *clk) +{ + assert(clk->source =3D=3D NULL); + trace_clock_propagate(CLOCK_PATH(clk)); + clock_propagate_period(clk, true); +} + +void clock_set_source(Clock *clk, Clock *src) +{ + /* changing clock source is not supported */ + assert(!clk->source); + + trace_clock_set_source(CLOCK_PATH(clk), CLOCK_PATH(src)); + + clk->period =3D src->period; + QLIST_INSERT_HEAD(&src->children, clk, sibling); + clk->source =3D src; + clock_propagate_period(clk, false); +} + +static void clock_disconnect(Clock *clk) +{ + if (clk->source =3D=3D NULL) { + return; + } + + trace_clock_disconnect(CLOCK_PATH(clk)); + + clk->source =3D NULL; + QLIST_REMOVE(clk, sibling); +} + +static void clock_initfn(Object *obj) +{ + Clock *clk =3D CLOCK(obj); + + QLIST_INIT(&clk->children); +} + +static void clock_finalizefn(Object *obj) +{ + Clock *clk =3D CLOCK(obj); + Clock *child, *next; + + /* clear our list of children */ + QLIST_FOREACH_SAFE(child, &clk->children, sibling, next) { + clock_disconnect(child); + } + + /* remove us from source's children list */ + clock_disconnect(clk); + + g_free(clk->canonical_path); +} + +static const TypeInfo clock_info =3D { + .name =3D TYPE_CLOCK, + .parent =3D TYPE_OBJECT, + .instance_size =3D sizeof(Clock), + .instance_init =3D clock_initfn, + .instance_finalize =3D clock_finalizefn, +}; + +static void clock_register_types(void) +{ + type_register_static(&clock_info); +} + +type_init(clock_register_types) diff --git a/hw/core/trace-events b/hw/core/trace-events index aecd8e160eb..1ac60ede6b7 100644 --- a/hw/core/trace-events +++ b/hw/core/trace-events @@ -27,3 +27,10 @@ resettable_phase_exit_begin(void *obj, const char *objty= pe, unsigned count, int resettable_phase_exit_exec(void *obj, const char *objtype, int has_method)= "obj=3D%p(%s) method=3D%d" resettable_phase_exit_end(void *obj, const char *objtype, unsigned count) = "obj=3D%p(%s) count=3D%d" resettable_transitional_function(void *obj, const char *objtype) "obj=3D%p= (%s)" + +# clock.c +clock_set_source(const char *clk, const char *src) "'%s', src=3D'%s'" +clock_disconnect(const char *clk) "'%s'" +clock_set(const char *clk, uint64_t old, uint64_t new) "'%s', ns=3D%"PRIu6= 4"->%"PRIu64 +clock_propagate(const char *clk) "'%s'" +clock_update(const char *clk, const char *src, uint64_t val, int cb) "'%s'= , src=3D'%s', ns=3D%"PRIu64", cb=3D%d" --=20 2.20.1 From nobody Thu May 2 02:03:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Damien Hedde Signed-off-by: Damien Hedde Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Message-id: 20200406135251.157596-3-damien.hedde@greensocs.com Signed-off-by: Peter Maydell --- hw/core/Makefile.objs | 1 + include/hw/clock.h | 9 +++++++++ hw/core/clock-vmstate.c | 25 +++++++++++++++++++++++++ 3 files changed, 35 insertions(+) create mode 100644 hw/core/clock-vmstate.c diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs index 1d9b0aa2057..115df550874 100644 --- a/hw/core/Makefile.objs +++ b/hw/core/Makefile.objs @@ -21,6 +21,7 @@ common-obj-$(CONFIG_SOFTMMU) +=3D null-machine.o common-obj-$(CONFIG_SOFTMMU) +=3D loader.o common-obj-$(CONFIG_SOFTMMU) +=3D machine-hmp-cmds.o common-obj-$(CONFIG_SOFTMMU) +=3D numa.o +common-obj-$(CONFIG_SOFTMMU) +=3D clock-vmstate.o obj-$(CONFIG_SOFTMMU) +=3D machine-qmp-cmds.o =20 common-obj-$(CONFIG_EMPTY_SLOT) +=3D empty_slot.o diff --git a/include/hw/clock.h b/include/hw/clock.h index 82a7f3c6982..f3e44e9460c 100644 --- a/include/hw/clock.h +++ b/include/hw/clock.h @@ -74,6 +74,15 @@ struct Clock { QLIST_ENTRY(Clock) sibling; }; =20 +/* + * vmstate description entry to be added in device vmsd. + */ +extern const VMStateDescription vmstate_clock; +#define VMSTATE_CLOCK(field, state) \ + VMSTATE_CLOCK_V(field, state, 0) +#define VMSTATE_CLOCK_V(field, state, version) \ + VMSTATE_STRUCT_POINTER_V(field, state, version, vmstate_clock, Clock) + /** * clock_setup_canonical_path: * @clk: clock diff --git a/hw/core/clock-vmstate.c b/hw/core/clock-vmstate.c new file mode 100644 index 00000000000..260b13fc2c8 --- /dev/null +++ b/hw/core/clock-vmstate.c @@ -0,0 +1,25 @@ +/* + * Clock migration structure + * + * Copyright GreenSocs 2019-2020 + * + * Authors: + * Damien Hedde + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "migration/vmstate.h" +#include "hw/clock.h" + +const VMStateDescription vmstate_clock =3D { + .name =3D "clock", + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(period, Clock), + VMSTATE_END_OF_LIST() + } +}; --=20 2.20.1 From nobody Thu May 2 02:03:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1588247940; cv=none; d=zohomail.com; s=zohoarc; b=d23NAmHvJkd2DI9UByJ5xvLOqhM39geJ0HHy+Mh807Kx+ihJWe9XInQaczfOlrdpRkhy5x7K5r3sdWYMNKDWkfDKzep8+PUG/gpyOOarpX7rGQhyNuKJPDPlEEOnrZblFvnfBuSiRmxkjpYxNvRG9VwyjZR+0XFyx/R5+uV+Bls= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588247940; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1e9mqY9kw1A5MpQFjMDnQ9ZYdH5jolAxvUg1fANxwL8=; b=IuQ08Kn+HBKA2QIU9B9UeQvLI8W/khpWvAlAM/SZpG1r6KVuoOF3s8DA/osQSZleAotfVzQUIF30EqzArOF3WJgWUniWsc6pv++5cGqbwaYjoEq+CQ2g12FHzpyeJWKVC9WWRmFt2Tem9yVJorYDO59CxE0mawX/KzMk9jkHPyE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1588247940109117.98354740607658; Thu, 30 Apr 2020 04:59:00 -0700 (PDT) Received: from localhost ([::1]:35282 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU7qE-0000EN-MF for importer@patchew.org; Thu, 30 Apr 2020 07:58:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33758) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU7jV-0002qu-Ng for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.90_1) (envelope-from ) id 1jU7jU-0000MZ-6j for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:01 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:33185) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jU7jT-0000M8-7y for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:51:59 -0400 Received: by mail-wm1-x334.google.com with SMTP id v8so7290406wma.0 for ; Thu, 30 Apr 2020 04:51:58 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j22sm491518wre.84.2020.04.30.04.51.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 04:51:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=1e9mqY9kw1A5MpQFjMDnQ9ZYdH5jolAxvUg1fANxwL8=; b=uRpH3EzFSBQF8ydeJwQ5myYTcDVmmQHthH4l0/ltCn/c8gIZ9OBy1e1ytCUdPFtYPT dKYEUs5odas3iI/Te9gPpKedYiMQuGeK0jsd2veCp5LYYOy8bKWJGkvGnBmVCPpXNlxZ r3WvTTOFqgj99tiV1/edhNYwjoAS9pdyf/CZeT6bhBnHdmNWh/nrvGeZzmXzvvI13LOD EvM+rJ2lnvNgikO+YgLKR9khBE2PlSzPhWeEZxKdhGfRkVH33IU4KSLhzPEB3HM1irjo 4KTFV1Mvw9PjMQleFmWSWpPfHt/L/v+FEvlI92wGF46Z62OqBBa5DhXpDXrJmQJQU9Pn Y17A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1e9mqY9kw1A5MpQFjMDnQ9ZYdH5jolAxvUg1fANxwL8=; b=cbXSXFqhpAEOsFdTQpcWv4ZIAiWFY/lVHnZf8AX+1VFW1OP1VAE6iw+m8EoigQd7pl vSVOs5BfVddv69f6K9+edUqDxlZwjPd4uYnmt6/u0Cu556+vwoYqY0kI7Vmbze8UIdqC A0fA1RS3fSTtCYKZVP6+WQRPlH5o+1dHjFtZg7Mz2CDvj/0ujti3I6DF0jBnKYryCaLf yoH8yrlWzunKLZEuhUKhLYGnux42be1czv+bbijOGCh6VveSDrPK+TX/Y/I2Nn8am25A 77KqYVqT+rmqv41WxqiZXWQcJy4vnZl+73op7QAI9EupUc6dPeHbUalsVqgQdCRJz9IE 0wzg== X-Gm-Message-State: AGi0PuaYoZ/p9YKt+g97jvWl5xW559PQQhKTbujsn7DIDV0Pbu5bXkJ7 NTqmNunfZdVBHzo9Q9cp1oYsdhnfNJn6dg== X-Google-Smtp-Source: APiQypJOQidEyAitEMkZZ/p4Fcr7A7LTrsLjD5n/rYQIvod+owFRX2hL+uNfxNkTrIyTrxILedIyTg== X-Received: by 2002:a7b:c755:: with SMTP id w21mr2545507wmk.120.1588247516387; Thu, 30 Apr 2020 04:51:56 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/31] qdev: add clock input&output support to devices. Date: Thu, 30 Apr 2020 12:51:22 +0100 Message-Id: <20200430115142.13430-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200430115142.13430-1-peter.maydell@linaro.org> References: <20200430115142.13430-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::334 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Damien Hedde Add functions to easily handle clocks with devices. Clock inputs and outputs should be used to handle clock propagation between devices. The API is very similar the GPIO API. This is based on the original work of Frederic Konrad. Signed-off-by: Damien Hedde Reviewed-by: Edgar E. Iglesias Reviewed-by: Alistair Francis Message-id: 20200406135251.157596-4-damien.hedde@greensocs.com Signed-off-by: Peter Maydell --- hw/core/Makefile.objs | 2 +- tests/Makefile.include | 1 + include/hw/qdev-clock.h | 104 +++++++++++++++++++++++++ include/hw/qdev-core.h | 12 +++ hw/core/qdev-clock.c | 168 ++++++++++++++++++++++++++++++++++++++++ hw/core/qdev.c | 12 +++ 6 files changed, 298 insertions(+), 1 deletion(-) create mode 100644 include/hw/qdev-clock.h create mode 100644 hw/core/qdev-clock.c diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs index 115df550874..1d540ed6e78 100644 --- a/hw/core/Makefile.objs +++ b/hw/core/Makefile.objs @@ -7,7 +7,7 @@ common-obj-y +=3D hotplug.o common-obj-y +=3D vmstate-if.o # irq.o needed for qdev GPIO handling: common-obj-y +=3D irq.o -common-obj-y +=3D clock.o +common-obj-y +=3D clock.o qdev-clock.o =20 common-obj-$(CONFIG_SOFTMMU) +=3D reset.o common-obj-$(CONFIG_SOFTMMU) +=3D qdev-fw.o diff --git a/tests/Makefile.include b/tests/Makefile.include index 51de6762983..03a74b60f6b 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -439,6 +439,7 @@ tests/test-qdev-global-props$(EXESUF): tests/test-qdev-= global-props.o \ hw/core/fw-path-provider.o \ hw/core/reset.o \ hw/core/vmstate-if.o \ + hw/core/clock.o hw/core/qdev-clock.o \ $(test-qapi-obj-y) tests/test-vmstate$(EXESUF): tests/test-vmstate.o \ migration/vmstate.o migration/vmstate-types.o migration/qemu-file.o \ diff --git a/include/hw/qdev-clock.h b/include/hw/qdev-clock.h new file mode 100644 index 00000000000..b3b3a3e021c --- /dev/null +++ b/include/hw/qdev-clock.h @@ -0,0 +1,104 @@ +/* + * Device's clock input and output + * + * Copyright GreenSocs 2016-2020 + * + * Authors: + * Frederic Konrad + * Damien Hedde + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef QDEV_CLOCK_H +#define QDEV_CLOCK_H + +#include "hw/clock.h" + +/** + * qdev_init_clock_in: + * @dev: the device to add an input clock to + * @name: the name of the clock (can't be NULL). + * @callback: optional callback to be called on update or NULL. + * @opaque: argument for the callback + * @returns: a pointer to the newly added clock + * + * Add an input clock to device @dev as a clock named @name. + * This adds a child<> property. + * The callback will be called with @opaque as opaque parameter. + */ +Clock *qdev_init_clock_in(DeviceState *dev, const char *name, + ClockCallback *callback, void *opaque); + +/** + * qdev_init_clock_out: + * @dev: the device to add an output clock to + * @name: the name of the clock (can't be NULL). + * @returns: a pointer to the newly added clock + * + * Add an output clock to device @dev as a clock named @name. + * This adds a child<> property. + */ +Clock *qdev_init_clock_out(DeviceState *dev, const char *name); + +/** + * qdev_get_clock_in: + * @dev: the device which has the clock + * @name: the name of the clock (can't be NULL). + * @returns: a pointer to the clock + * + * Get the input clock @name from @dev or NULL if does not exist. + */ +Clock *qdev_get_clock_in(DeviceState *dev, const char *name); + +/** + * qdev_get_clock_out: + * @dev: the device which has the clock + * @name: the name of the clock (can't be NULL). + * @returns: a pointer to the clock + * + * Get the output clock @name from @dev or NULL if does not exist. + */ +Clock *qdev_get_clock_out(DeviceState *dev, const char *name); + +/** + * qdev_connect_clock_in: + * @dev: a device + * @name: the name of an input clock in @dev + * @source: the source clock (an output clock of another device for exampl= e) + * + * Set the source clock of input clock @name of device @dev to @source. + * @source period update will be propagated to @name clock. + */ +static inline void qdev_connect_clock_in(DeviceState *dev, const char *nam= e, + Clock *source) +{ + clock_set_source(qdev_get_clock_in(dev, name), source); +} + +/** + * qdev_alias_clock: + * @dev: the device which has the clock + * @name: the name of the clock in @dev (can't be NULL) + * @alias_dev: the device to add the clock + * @alias_name: the name of the clock in @container + * @returns: a pointer to the clock + * + * Add a clock @alias_name in @alias_dev which is an alias of the clock @n= ame + * in @dev. The direction _in_ or _out_ will the same as the original. + * An alias clock must not be modified or used by @alias_dev and should + * typically be only only for device composition purpose. + */ +Clock *qdev_alias_clock(DeviceState *dev, const char *name, + DeviceState *alias_dev, const char *alias_name); + +/** + * qdev_finalize_clocklist: + * @dev: the device being finalized + * + * Clear the clocklist from @dev. Only used internally in qdev. + */ +void qdev_finalize_clocklist(DeviceState *dev); + +#endif /* QDEV_CLOCK_H */ diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index 1405b8a990a..d87d989e72a 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -149,6 +149,17 @@ struct NamedGPIOList { QLIST_ENTRY(NamedGPIOList) node; }; =20 +typedef struct Clock Clock; +typedef struct NamedClockList NamedClockList; + +struct NamedClockList { + char *name; + Clock *clock; + bool output; + bool alias; + QLIST_ENTRY(NamedClockList) node; +}; + /** * DeviceState: * @realized: Indicates whether the device has been fully constructed. @@ -171,6 +182,7 @@ struct DeviceState { bool allow_unplug_during_migration; BusState *parent_bus; QLIST_HEAD(, NamedGPIOList) gpios; + QLIST_HEAD(, NamedClockList) clocks; QLIST_HEAD(, BusState) child_bus; int num_child_bus; int instance_id_alias; diff --git a/hw/core/qdev-clock.c b/hw/core/qdev-clock.c new file mode 100644 index 00000000000..62035aef830 --- /dev/null +++ b/hw/core/qdev-clock.c @@ -0,0 +1,168 @@ +/* + * Device's clock input and output + * + * Copyright GreenSocs 2016-2020 + * + * Authors: + * Frederic Konrad + * Damien Hedde + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "hw/qdev-clock.h" +#include "hw/qdev-core.h" +#include "qapi/error.h" + +/* + * qdev_init_clocklist: + * Add a new clock in a device + */ +static NamedClockList *qdev_init_clocklist(DeviceState *dev, const char *n= ame, + bool output, Clock *clk) +{ + NamedClockList *ncl; + + /* + * Clock must be added before realize() so that we can compute the + * clock's canonical path during device_realize(). + */ + assert(!dev->realized); + + /* + * The ncl structure is freed by qdev_finalize_clocklist() which will + * be called during @dev's device_finalize(). + */ + ncl =3D g_new0(NamedClockList, 1); + ncl->name =3D g_strdup(name); + ncl->output =3D output; + ncl->alias =3D (clk !=3D NULL); + + /* + * Trying to create a clock whose name clashes with some other + * clock or property is a bug in the caller and we will abort(). + */ + if (clk =3D=3D NULL) { + clk =3D CLOCK(object_new(TYPE_CLOCK)); + object_property_add_child(OBJECT(dev), name, OBJECT(clk), &error_a= bort); + if (output) { + /* + * Remove object_new()'s initial reference. + * Note that for inputs, the reference created by object_new() + * will be deleted in qdev_finalize_clocklist(). + */ + object_unref(OBJECT(clk)); + } + } else { + object_property_add_link(OBJECT(dev), name, + object_get_typename(OBJECT(clk)), + (Object **) &ncl->clock, + NULL, OBJ_PROP_LINK_STRONG, &error_abort); + } + + ncl->clock =3D clk; + + QLIST_INSERT_HEAD(&dev->clocks, ncl, node); + return ncl; +} + +void qdev_finalize_clocklist(DeviceState *dev) +{ + /* called by @dev's device_finalize() */ + NamedClockList *ncl, *ncl_next; + + QLIST_FOREACH_SAFE(ncl, &dev->clocks, node, ncl_next) { + QLIST_REMOVE(ncl, node); + if (!ncl->output && !ncl->alias) { + /* + * We kept a reference on the input clock to ensure it lives u= p to + * this point so we can safely remove the callback. + * It avoids having a callback to a deleted object if ncl->clo= ck + * is still referenced somewhere else (eg: by a clock output). + */ + clock_clear_callback(ncl->clock); + object_unref(OBJECT(ncl->clock)); + } + g_free(ncl->name); + g_free(ncl); + } +} + +Clock *qdev_init_clock_out(DeviceState *dev, const char *name) +{ + NamedClockList *ncl; + + assert(name); + + ncl =3D qdev_init_clocklist(dev, name, true, NULL); + + return ncl->clock; +} + +Clock *qdev_init_clock_in(DeviceState *dev, const char *name, + ClockCallback *callback, void *opaque) +{ + NamedClockList *ncl; + + assert(name); + + ncl =3D qdev_init_clocklist(dev, name, false, NULL); + + if (callback) { + clock_set_callback(ncl->clock, callback, opaque); + } + return ncl->clock; +} + +static NamedClockList *qdev_get_clocklist(DeviceState *dev, const char *na= me) +{ + NamedClockList *ncl; + + QLIST_FOREACH(ncl, &dev->clocks, node) { + if (strcmp(name, ncl->name) =3D=3D 0) { + return ncl; + } + } + + return NULL; +} + +Clock *qdev_get_clock_in(DeviceState *dev, const char *name) +{ + NamedClockList *ncl; + + assert(name); + + ncl =3D qdev_get_clocklist(dev, name); + assert(!ncl->output); + + return ncl->clock; +} + +Clock *qdev_get_clock_out(DeviceState *dev, const char *name) +{ + NamedClockList *ncl; + + assert(name); + + ncl =3D qdev_get_clocklist(dev, name); + assert(ncl->output); + + return ncl->clock; +} + +Clock *qdev_alias_clock(DeviceState *dev, const char *name, + DeviceState *alias_dev, const char *alias_name) +{ + NamedClockList *ncl; + + assert(name && alias_name); + + ncl =3D qdev_get_clocklist(dev, name); + + qdev_init_clocklist(alias_dev, alias_name, ncl->output, ncl->clock); + + return ncl->clock; +} diff --git a/hw/core/qdev.c b/hw/core/qdev.c index 85f062def72..dd77a560672 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -37,6 +37,7 @@ #include "hw/qdev-properties.h" #include "hw/boards.h" #include "hw/sysbus.h" +#include "hw/qdev-clock.h" #include "migration/vmstate.h" #include "trace.h" =20 @@ -855,6 +856,7 @@ static void device_set_realized(Object *obj, bool value= , Error **errp) DeviceClass *dc =3D DEVICE_GET_CLASS(dev); HotplugHandler *hotplug_ctrl; BusState *bus; + NamedClockList *ncl; Error *local_err =3D NULL; bool unattached_parent =3D false; static int unattached_count; @@ -902,6 +904,13 @@ static void device_set_realized(Object *obj, bool valu= e, Error **errp) */ g_free(dev->canonical_path); dev->canonical_path =3D object_get_canonical_path(OBJECT(dev)); + QLIST_FOREACH(ncl, &dev->clocks, node) { + if (ncl->alias) { + continue; + } else { + clock_setup_canonical_path(ncl->clock); + } + } =20 if (qdev_get_vmsd(dev)) { if (vmstate_register_with_alias_id(VMSTATE_IF(dev), @@ -1025,6 +1034,7 @@ static void device_initfn(Object *obj) dev->allow_unplug_during_migration =3D false; =20 QLIST_INIT(&dev->gpios); + QLIST_INIT(&dev->clocks); } =20 static void device_post_init(Object *obj) @@ -1054,6 +1064,8 @@ static void device_finalize(Object *obj) */ } =20 + qdev_finalize_clocklist(dev); + /* Only send event if the device had been completely realized */ if (dev->pending_deleted_event) { g_assert(dev->canonical_path); --=20 2.20.1 From nobody Thu May 2 02:03:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1588248070; cv=none; d=zohomail.com; s=zohoarc; b=E2cr/U6/dhObuCY/cEaalZNgFbXRHNhtSCCIZerXOvsIGmx6U3UGWLNQkThgPxyQNxTmoDVA9AX/yBT0HE3bmqmw1UWaq8Wgh3OUNrnBP89efZNVyfWsx0kU3glVM8TvLjZpVy1JrdTkPdfM2GEzApwk1QMxMps1CpfAsMxSCz0= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j22sm491518wre.84.2020.04.30.04.51.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 04:51:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=VXBXtqv3GitaXcVyiEVFZJrNpGUF5enLW1nUxgiyox0=; b=BKACY60dzGyalop3Fdykr4+lf1xfeK21azs6Wu+TUDexrG4+Wxqpd+t3LDT+Jl/pQZ ygT1pt4i8q4nF1Jug6zCLn9bVHATKUMOcuOhvyJy5PvwVBlZ0sjefbcjEBnhI4MMrG1c T+p3tGFjhyywKNSg4RB6JfYJjO8/CBuphJZDaHIUT2FKGr1eH42F4ncQslnMqSwaicRC ZeLpDgfeEmatC3M+Vqk+3BFc/axrrvJ/m8L+ieMa5yubpmAyfdsleUL5oGdqp0O4EO30 fulHfpQQJzYLK8JuSLwdpvH8Ounlkk+lGPha7NDdQ/tLmW3XgqI/Ssx1vwjy9Q2pIrh0 Rn1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VXBXtqv3GitaXcVyiEVFZJrNpGUF5enLW1nUxgiyox0=; b=ojaureRJ4COsslhib9lB2a2L92ZC5i9G0JFdFix1v/ptuylbZSzhLkrMMh6kEDAacw K3EsF80A2Fd4Noftx9y+Ky5ujuecyTGmfRl8YmLNxFkL2sPsaeRb1100IeD7s22mn43R urNCgYIvQoVpjVp/f7z0s+vtstuNejxYQCC+PGhxuHwYYSpbV5eAdpLnmH6FkMQrytMl +b4bNwn1kEjW30hh2lO5ImvDxPUrG6F7zivnBSHrXCZMg2/lIRlmEIvuURUIqUFTIhRa UITnduvRksH2Y6TC+nhbnQt+sHlsZea2xXKvfn89lqd8mgUskWr3kpmG22W8junERyWX Xf0Q== X-Gm-Message-State: AGi0Pua6/iKQi9N+1I2lHdnl2god+5lzNSEyfEpiPA/quPaqC9Iz1DZu 8vZxVtgWg3lhpi2Hpme6fyoACRpflW6OHA== X-Google-Smtp-Source: APiQypLXDrItqpA0QjI8TjkpJhr0Q2swIdQjL2ziFtqG0jlD/bojW/ALvQtuO9cKKDsxeI8EXDEM4A== X-Received: by 2002:a7b:c390:: with SMTP id s16mr2551630wmj.14.1588247517380; Thu, 30 Apr 2020 04:51:57 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/31] qdev-clock: introduce an init array to ease the device construction Date: Thu, 30 Apr 2020 12:51:23 +0100 Message-Id: <20200430115142.13430-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200430115142.13430-1-peter.maydell@linaro.org> References: <20200430115142.13430-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::336 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Damien Hedde Introduce a function and macro helpers to setup several clocks in a device from a static array description. An element of the array describes the clock (name and direction) as well as the related callback and an optional offset to store the created object pointer in the device state structure. The array must be terminated by a special element QDEV_CLOCK_END. This is based on the original work of Frederic Konrad. Signed-off-by: Damien Hedde Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Message-id: 20200406135251.157596-5-damien.hedde@greensocs.com Signed-off-by: Peter Maydell --- include/hw/qdev-clock.h | 55 +++++++++++++++++++++++++++++++++++++++++ hw/core/qdev-clock.c | 17 +++++++++++++ 2 files changed, 72 insertions(+) diff --git a/include/hw/qdev-clock.h b/include/hw/qdev-clock.h index b3b3a3e021c..a340f65ff90 100644 --- a/include/hw/qdev-clock.h +++ b/include/hw/qdev-clock.h @@ -101,4 +101,59 @@ Clock *qdev_alias_clock(DeviceState *dev, const char *= name, */ void qdev_finalize_clocklist(DeviceState *dev); =20 +/** + * ClockPortInitElem: + * @name: name of the clock (can't be NULL) + * @output: indicates whether the clock is input or output + * @callback: for inputs, optional callback to be called on clock's update + * with device as opaque + * @offset: optional offset to store the ClockIn or ClockOut pointer in de= vice + * state structure (0 means unused) + */ +struct ClockPortInitElem { + const char *name; + bool is_output; + ClockCallback *callback; + size_t offset; +}; + +#define clock_offset_value(devstate, field) \ + (offsetof(devstate, field) + \ + type_check(Clock *, typeof_field(devstate, field))) + +#define QDEV_CLOCK(out_not_in, devstate, field, cb) { \ + .name =3D (stringify(field)), \ + .is_output =3D out_not_in, \ + .callback =3D cb, \ + .offset =3D clock_offset_value(devstate, field), \ +} + +/** + * QDEV_CLOCK_(IN|OUT): + * @devstate: structure type. @dev argument of qdev_init_clocks below must= be + * a pointer to that same type. + * @field: a field in @_devstate (must be Clock*) + * @callback: (for input only) callback (or NULL) to be called with the de= vice + * state as argument + * + * The name of the clock will be derived from @field + */ +#define QDEV_CLOCK_IN(devstate, field, callback) \ + QDEV_CLOCK(false, devstate, field, callback) + +#define QDEV_CLOCK_OUT(devstate, field) \ + QDEV_CLOCK(true, devstate, field, NULL) + +#define QDEV_CLOCK_END { .name =3D NULL } + +typedef struct ClockPortInitElem ClockPortInitArray[]; + +/** + * qdev_init_clocks: + * @dev: the device to add clocks to + * @clocks: a QDEV_CLOCK_END-terminated array which contains the + * clocks information. + */ +void qdev_init_clocks(DeviceState *dev, const ClockPortInitArray clocks); + #endif /* QDEV_CLOCK_H */ diff --git a/hw/core/qdev-clock.c b/hw/core/qdev-clock.c index 62035aef830..a94cc444379 100644 --- a/hw/core/qdev-clock.c +++ b/hw/core/qdev-clock.c @@ -116,6 +116,23 @@ Clock *qdev_init_clock_in(DeviceState *dev, const char= *name, return ncl->clock; } =20 +void qdev_init_clocks(DeviceState *dev, const ClockPortInitArray clocks) +{ + const struct ClockPortInitElem *elem; + + for (elem =3D &clocks[0]; elem->name !=3D NULL; elem++) { + Clock **clkp; + /* offset cannot be inside the DeviceState part */ + assert(elem->offset > sizeof(DeviceState)); + clkp =3D (Clock **)(((void *) dev) + elem->offset); + if (elem->is_output) { + *clkp =3D qdev_init_clock_out(dev, elem->name); + } else { + *clkp =3D qdev_init_clock_in(dev, elem->name, elem->callback, = dev); + } + } +} + static NamedClockList *qdev_get_clocklist(DeviceState *dev, const char *na= me) { NamedClockList *ncl; --=20 2.20.1 From nobody Thu May 2 02:03:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1588247773; cv=none; d=zohomail.com; s=zohoarc; b=chuRTkEFisfoAlf0oDO0Io5UFXV0r7uUhVgICL8N3LdRqkJpa9YZb7o782ebnlVauyQB6r/jSZWAFUplXZNHdPemhI6XEXC5WIr4GCGf+FyPLPw19shf8NFFF4hE27e2cuDT0eSYwNknkfAVmpaWbw0YKVsWg9JgCier7sKuTWA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588247773; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5Ha2gvJ6Lz6JIzIjwUnkZaNBrlTY50iNH7waG0Y7ui0=; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j22sm491518wre.84.2020.04.30.04.51.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 04:51:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=5Ha2gvJ6Lz6JIzIjwUnkZaNBrlTY50iNH7waG0Y7ui0=; b=AV0bNcnSQUIdCextyCxxZ+F1WDwAtrr6ibftu4FNBZ/1X+TQIqHjasasc1yNxNUQo7 P2Zn3c39a8T0yBYzgWYoMpTguYTARnB4t7uR8UlDjcxjEqJPxTgCv6cwy4DKShjx1ASC n0SEolLmVfnYw2QP8Dzm8scTujRyC/u+rWnu73Wnp29NGXRHPnx/Ms/wF04jDRsLeqcE htB1aBMtpZeF/Jw3hm+4uNu/a86L7SUe6Qm2AT2ZRRo+YUCNmlKMMRuIU8YrQz0Ts2e1 2gsxXlApCnLXVB666yZb4df9moKLR/HVTkfnVZe5sDPj2biMWSProxLVh65xQBWMDbfi 5/YQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5Ha2gvJ6Lz6JIzIjwUnkZaNBrlTY50iNH7waG0Y7ui0=; b=BSZnQZDOvhuvyAh+xGPrvzHoOm0IrI0j6Tuxhko4B32HBr/EAHju4qGot+yd0cxdba ZbxcpZiQeHLHMToLXVHfsYMxS4K1x801XXzWhBfxZYsmaQg/9yqa5Pm5KARNfpm+mYQs 8T665Rc2qpQbjUOyIuCqZY+f/N23YA01eR/Qjz+ft9X5v/8LFTNU8rCzL0O//9zf34Ks IYNJVj5hf/ty1XOaHbAxu4gn0F0BRDE5cOZmhXFOhiZR7gvOfJ6hXZ3Mwy1P7ScYPzWN TT10VaDsUxrpKL1fipb3k/mgNbN4MhDLQcvisFgUjp8KBOAHhY/BwyhyP97jSeHlFUvr O76A== X-Gm-Message-State: AGi0PuaWdyDrqxUXfPgcPiQ1LbU5cWbmnnUSb7tbQbuM2OfqpH/WhUXU 5E+isNyz7BbeSf5ruo3Y1QjdwP1DqfIXMw== X-Google-Smtp-Source: APiQypKNRZryjwLt+4+p3S6iVIfAnBlL5ns7HH7yhp51SeDuzDjNgH2BDORl7Q4Qk7Eb70b9eEHR/w== X-Received: by 2002:a7b:c250:: with SMTP id b16mr2684033wmj.100.1588247519169; Thu, 30 Apr 2020 04:51:59 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/31] docs/clocks: add device's clock documentation Date: Thu, 30 Apr 2020 12:51:24 +0100 Message-Id: <20200430115142.13430-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200430115142.13430-1-peter.maydell@linaro.org> References: <20200430115142.13430-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::32b X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Add the documentation about the clock inputs and outputs in devices. This is based on the original work of Frederic Konrad. Signed-off-by: Damien Hedde Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Message-id: 20200406135251.157596-6-damien.hedde@greensocs.com [PMM: Editing pass for minor grammar, style and Sphinx formatting fixes] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- docs/devel/clocks.rst | 391 ++++++++++++++++++++++++++++++++++++++++++ docs/devel/index.rst | 1 + 2 files changed, 392 insertions(+) create mode 100644 docs/devel/clocks.rst diff --git a/docs/devel/clocks.rst b/docs/devel/clocks.rst new file mode 100644 index 00000000000..e5da28e2111 --- /dev/null +++ b/docs/devel/clocks.rst @@ -0,0 +1,391 @@ +Modelling a clock tree in QEMU +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D + +What are clocks? +---------------- + +Clocks are QOM objects developed for the purpose of modelling the +distribution of clocks in QEMU. + +They allow us to model the clock distribution of a platform and detect +configuration errors in the clock tree such as badly configured PLL, clock +source selection or disabled clock. + +The object is *Clock* and its QOM name is ``clock`` (in C code, the macro +``TYPE_CLOCK``). + +Clocks are typically used with devices where they are used to model inputs +and outputs. They are created in a similar way to GPIOs. Inputs and outputs +of different devices can be connected together. + +In these cases a Clock object is a child of a Device object, but this +is not a requirement. Clocks can be independent of devices. For +example it is possible to create a clock outside of any device to +model the main clock source of a machine. + +Here is an example of clocks:: + + +---------+ +----------------------+ +--------------+ + | Clock 1 | | Device B | | Device C | + | | | +-------+ +-------+ | | +-------+ | + | |>>-+-->>|Clock 2| |Clock 3|>>--->>|Clock 6| | + +---------+ | | | (in) | | (out) | | | | (in) | | + | | +-------+ +-------+ | | +-------+ | + | | +-------+ | +--------------+ + | | |Clock 4|>> + | | | (out) | | +--------------+ + | | +-------+ | | Device D | + | | +-------+ | | +-------+ | + | | |Clock 5|>>--->>|Clock 7| | + | | | (out) | | | | (in) | | + | | +-------+ | | +-------+ | + | +----------------------+ | | + | | +-------+ | + +----------------------------->>|Clock 8| | + | | (in) | | + | +-------+ | + +--------------+ + +Clocks are defined in the ``include/hw/clock.h`` header and device +related functions are defined in the ``include/hw/qdev-clock.h`` +header. + +The clock state +--------------- + +The state of a clock is its period; it is stored as an integer +representing it in units of 2 :sup:`-32` ns. The special value of 0 is use= d to +represent the clock being inactive or gated. The clocks do not model +the signal itself (pin toggling) or other properties such as the duty +cycle. + +All clocks contain this state: outputs as well as inputs. This allows +the current period of a clock to be fetched at any time. When a clock +is updated, the value is immediately propagated to all connected +clocks in the tree. + +To ease interaction with clocks, helpers with a unit suffix are defined for +every clock state setter or getter. The suffixes are: + +- ``_ns`` for handling periods in nanoseconds +- ``_hz`` for handling frequencies in hertz + +The 0 period value is converted to 0 in hertz and vice versa. 0 always mea= ns +that the clock is disabled. + +Adding a new clock +------------------ + +Adding clocks to a device must be done during the init method of the Device +instance. + +To add an input clock to a device, the function ``qdev_init_clock_in()`` +must be used. It takes the name, a callback and an opaque parameter +for the callback (this will be explained in a following section). +Output is simpler; only the name is required. Typically:: + + qdev_init_clock_in(DEVICE(dev), "clk_in", clk_in_callback, dev); + qdev_init_clock_out(DEVICE(dev), "clk_out"); + +Both functions return the created Clock pointer, which should be saved in = the +device's state structure for further use. + +These objects will be automatically deleted by the QOM reference mechanism. + +Note that it is possible to create a static array describing clock inputs = and +outputs. The function ``qdev_init_clocks()`` must be called with the array= as +parameter to initialize the clocks: it has the same behaviour as calling t= he +``qdev_init_clock_in/out()`` for each clock in the array. To ease the array +construction, some macros are defined in ``include/hw/qdev-clock.h``. +As an example, the following creates 2 clocks to a device: one input and o= ne +output. + +.. code-block:: c + + /* device structure containing pointers to the clock objects */ + typedef struct MyDeviceState { + DeviceState parent_obj; + Clock *clk_in; + Clock *clk_out; + } MyDeviceState; + + /* + * callback for the input clock (see "Callback on input clock + * change" section below for more information). + */ + static void clk_in_callback(void *opaque); + + /* + * static array describing clocks: + * + a clock input named "clk_in", whose pointer is stored in + * the clk_in field of a MyDeviceState structure with callback + * clk_in_callback. + * + a clock output named "clk_out" whose pointer is stored in + * the clk_out field of a MyDeviceState structure. + */ + static const ClockPortInitArray mydev_clocks =3D { + QDEV_CLOCK_IN(MyDeviceState, clk_in, clk_in_callback), + QDEV_CLOCK_OUT(MyDeviceState, clk_out), + QDEV_CLOCK_END + }; + + /* device initialization function */ + static void mydev_init(Object *obj) + { + /* cast to MyDeviceState */ + MyDeviceState *mydev =3D MYDEVICE(obj); + /* create and fill the pointer fields in the MyDeviceState */ + qdev_init_clocks(mydev, mydev_clocks); + [...] + } + +An alternative way to create a clock is to simply call +``object_new(TYPE_CLOCK)``. In that case the clock will neither be an +input nor an output of a device. After the whole QOM hierarchy of the +clock has been set ``clock_setup_canonical_path()`` should be called. + +At creation, the period of the clock is 0: the clock is disabled. You can +change it using ``clock_set_ns()`` or ``clock_set_hz()``. + +Note that if you are creating a clock with a fixed period which will never +change (for example the main clock source of a board), then you'll have +nothing else to do. This value will be propagated to other clocks when +connecting the clocks together and devices will fetch the right value duri= ng +the first reset. + +Retrieving clocks from a device +------------------------------- + +``qdev_get_clock_in()`` and ``dev_get_clock_out()`` are available to +get the clock inputs or outputs of a device. For example: + +.. code-block:: c + + Clock *clk =3D qdev_get_clock_in(DEVICE(mydev), "clk_in"); + +or: + +.. code-block:: c + + Clock *clk =3D qdev_get_clock_out(DEVICE(mydev), "clk_out"); + +Connecting two clocks together +------------------------------ + +To connect two clocks together, use the ``clock_set_source()`` function. +Given two clocks ``clk1``, and ``clk2``, ``clock_set_source(clk2, clk1);`` +configures ``clk2`` to follow the ``clk1`` period changes. Every time ``cl= k1`` +is updated, ``clk2`` will be updated too. + +When connecting clock between devices, prefer using the +``qdev_connect_clock_in()`` function to set the source of an input +device clock. For example, to connect the input clock ``clk2`` of +``devB`` to the output clock ``clk1`` of ``devA``, do: + +.. code-block:: c + + qdev_connect_clock_in(devB, "clk2", qdev_get_clock_out(devA, "clk1")) + +We used ``qdev_get_clock_out()`` above, but any clock can drive an +input clock, even another input clock. The following diagram shows +some examples of connections. Note also that a clock can drive several +other clocks. + +:: + + +------------+ +--------------------------------------------------+ + | Device A | | Device B | + | | | +---------------------+ | + | | | | Device C | | + | +-------+ | | +-------+ | +-------+ +-------+ | +-------+ | + | |Clock 1|>>-->>|Clock 2|>>+-->>|Clock 3| |Clock 5|>>>>|Clock 6|>> + | | (out) | | | | (in) | | | | (in) | | (out) | | | (out) | | + | +-------+ | | +-------+ | | +-------+ +-------+ | +-------+ | + +------------+ | | +---------------------+ | + | | | + | | +--------------+ | + | | | Device D | | + | | | +-------+ | | + | +-->>|Clock 4| | | + | | | (in) | | | + | | +-------+ | | + | +--------------+ | + +--------------------------------------------------+ + +In the above example, when *Clock 1* is updated by *Device A*, three +clocks get the new clock period value: *Clock 2*, *Clock 3* and *Clock 4*. + +It is not possible to disconnect a clock or to change the clock connection +after it is connected. + +Unconnected input clocks +------------------------ + +A newly created input clock is disabled (period of 0). This means the +clock will be considered as disabled until the period is updated. If +the clock remains unconnected it will always keep its initial value +of 0. If this is not the desired behaviour, ``clock_set()``, +``clock_set_ns()`` or ``clock_set_hz()`` should be called on the Clock +object during device instance init. For example: + +.. code-block:: c + + clk =3D qdev_init_clock_in(DEVICE(dev), "clk-in", clk_in_callback, + dev); + /* set initial value to 10ns / 100MHz */ + clock_set_ns(clk, 10); + +Fetching clock frequency/period +------------------------------- + +To get the current state of a clock, use the functions ``clock_get()``, +``clock_get_ns()`` or ``clock_get_hz()``. + +It is also possible to register a callback on clock frequency changes. +Here is an example: + +.. code-block:: c + + void clock_callback(void *opaque) { + MyDeviceState *s =3D (MyDeviceState *) opaque; + /* + * 'opaque' is the argument passed to qdev_init_clock_in(); + * usually this will be the device state pointer. + */ + + /* do something with the new period */ + fprintf(stdout, "device new period is %" PRIu64 "ns\n", + clock_get_ns(dev->my_clk_input)); + } + +Changing a clock period +----------------------- + +A device can change its outputs using the ``clock_update()``, +``clock_update_ns()`` or ``clock_update_hz()`` function. It will trigger +updates on every connected input. + +For example, let's say that we have an output clock *clkout* and we +have a pointer to it in the device state because we did the following +in init phase: + +.. code-block:: c + + dev->clkout =3D qdev_init_clock_out(DEVICE(dev), "clkout"); + +Then at any time (apart from the cases listed below), it is possible to +change the clock value by doing: + +.. code-block:: c + + clock_update_hz(dev->clkout, 1000 * 1000 * 1000); /* 1GHz */ + +Because updating a clock may trigger any side effects through +connected clocks and their callbacks, this operation must be done +while holding the qemu io lock. + +For the same reason, one can update clocks only when it is allowed to have +side effects on other objects. In consequence, it is forbidden: + +* during migration, +* and in the enter phase of reset. + +Note that calling ``clock_update[_ns|_hz]()`` is equivalent to calling +``clock_set[_ns|_hz]()`` (with the same arguments) then +``clock_propagate()`` on the clock. Thus, setting the clock value can +be separated from triggering the side-effects. This is often required +to factorize code to handle reset and migration in devices. + +Aliasing clocks +--------------- + +Sometimes, one needs to forward, or inherit, a clock from another +device. Typically, when doing device composition, a device might +expose a sub-device's clock without interfering with it. The function +``qdev_alias_clock()`` can be used to achieve this behaviour. Note +that it is possible to expose the clock under a different name. +``qdev_alias_clock()`` works for both input and output clocks. + +For example, if device B is a child of device A, +``device_a_instance_init()`` may do something like this: + +.. code-block:: c + + void device_a_instance_init(Object *obj) + { + AState *A =3D DEVICE_A(obj); + BState *B; + /* create object B as child of A */ + [...] + qdev_alias_clock(B, "clk", A, "b_clk"); + /* + * Now A has a clock "b_clk" which is an alias to + * the clock "clk" of its child B. + */ + } + +This function does not return any clock object. The new clock has the +same direction (input or output) as the original one. This function +only adds a link to the existing clock. In the above example, object B +remains the only object allowed to use the clock and device A must not +try to change the clock period or set a callback to the clock. This +diagram describes the example with an input clock:: + + +--------------------------+ + | Device A | + | +--------------+ | + | | Device B | | + | | +-------+ | | + >>"b_clk">>>| "clk" | | | + | (in) | | (in) | | | + | | +-------+ | | + | +--------------+ | + +--------------------------+ + +Migration +--------- + +Clock state is not migrated automatically. Every device must handle its +clock migration. Alias clocks must not be migrated. + +To ensure clock states are restored correctly during migration, there +are two solutions. + +Clock states can be migrated by adding an entry into the device +vmstate description. You should use the ``VMSTATE_CLOCK`` macro for this. +This is typically used to migrate an input clock state. For example: + +.. code-block:: c + + MyDeviceState { + DeviceState parent_obj; + [...] /* some fields */ + Clock *clk; + }; + + VMStateDescription my_device_vmstate =3D { + .name =3D "my_device", + .fields =3D (VMStateField[]) { + [...], /* other migrated fields */ + VMSTATE_CLOCK(clk, MyDeviceState), + VMSTATE_END_OF_LIST() + } + }; + +The second solution is to restore the clock state using information already +at our disposal. This can be used to restore output clock states using the +device state. The functions ``clock_set[_ns|_hz]()`` can be used during the +``post_load()`` migration callback. + +When adding clock support to an existing device, if you care about +migration compatibility you will need to be careful, as simply adding +a ``VMSTATE_CLOCK()`` line will break compatibility. Instead, you can +put the ``VMSTATE_CLOCK()`` line into a vmstate subsection with a +suitable ``needed`` function, and use ``clock_set()`` in a +``pre_load()`` function to set the default value that will be used if +the source virtual machine in the migration does not send the clock +state. + +Care should be taken not to use ``clock_update[_ns|_hz]()`` or +``clock_propagate()`` during the whole migration procedure because it +will trigger side effects to other devices in an unknown state. diff --git a/docs/devel/index.rst b/docs/devel/index.rst index a9e1200dff3..bb8238c5d6d 100644 --- a/docs/devel/index.rst +++ b/docs/devel/index.rst @@ -27,3 +27,4 @@ Contents: bitops reset s390-dasd-ipl + clocks --=20 2.20.1 From nobody Thu May 2 02:03:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1588248082; cv=none; d=zohomail.com; s=zohoarc; b=WoKizihFZt/fcEje0nKSJ8RB1NPqCS3Mbw/u43QfX9lQ8EAl63F7qk2Zyew0YLKrCtJ4wS7ISsNm1Zv1LXmSBeejVek3V3d7NkDD0LpFgCVH1AAnECLMqAlMbNLjg3ccy2D03S0UtK97lGSqGe4qqp6776CG7MJeYxMPHmebKF8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588248082; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=AJXfL2jqd2Dghtxu48PtxiUOw3gg5pYzLqvjsbDeTtM=; b=L1IUKNXxMhhaxkCnDxOm8seJUu0R7tk+W77CcvTz5pyf8Al/8SbnPFMk8E1i1qEmj5WT9Sw1id7p6aFbyjmM76MvgDcVge3tepxDBZASHO44V51w2ARcn2VFdX00PnLmKg/nAwP9z3x6kX6rrcLe05X9BEkptMH5CLwL/BZjTRg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1588248082249452.7356222485321; Thu, 30 Apr 2020 05:01:22 -0700 (PDT) Received: from localhost ([::1]:44140 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU7sW-00046l-Gm for importer@patchew.org; Thu, 30 Apr 2020 08:01:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33804) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU7jZ-0002xY-Se for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.90_1) (envelope-from ) id 1jU7jX-0000Nr-Tb for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:05 -0400 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:37854) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jU7jX-0000My-BF for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:03 -0400 Received: by mail-wm1-x344.google.com with SMTP id z6so1552879wml.2 for ; Thu, 30 Apr 2020 04:52:01 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j22sm491518wre.84.2020.04.30.04.51.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 04:51:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=AJXfL2jqd2Dghtxu48PtxiUOw3gg5pYzLqvjsbDeTtM=; b=bR2Guo3cmsKHeNGDvjTWtUudMl7Zwk+ALqx4uYrj8z0TM591a8TkX6wTnJfqeW3rLQ tS9MvX3rAAFbjo7+Zs3//YHvwr9OfPaSu3x7wZpzIVG0+DNapDdqMWIyA5v6POaJQbGB vttOXgIRb0mIqFVV883mAX4gzxmXvOI44suJtBKCbn8hsZEjF5vBAMpeiSh8sUbpVWVL xL5fP3Y5QqZuWRjRbjOfeuwS1qTj5og5XOsh7oiQhExWg/OlS62CAK+te0b1cnEh7NxT ARs0waWPKHXYuUa3TKqUwUiV2aCo4NN8cCnf+Em8l5bBv58grX2H4AP3hGSxmTsg22j8 ZoBQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AJXfL2jqd2Dghtxu48PtxiUOw3gg5pYzLqvjsbDeTtM=; b=ZlZ+QaNzJJ7kNzLpK/X4KWZdV5HMXLWnGKxJ9cbraU/rCTO3GS9VqUz6l2Ss3x0Ees dEdGIPVL+xGygRaWZORjnG5/i6QVopeeRh2K16a7Ngd1fLoUhch5NcugUEW5DF/RZAFa BmfjcAdIuYg8tnA32XlCuNT+TBmRaUkzpxCqEWnMyNFHrlYIbTEHOndOMmZQEU5SWcRb 2Nmb5YNW9sFHZ/uJhXSlwyplHfNOzJZRzesZ/HduHoekG1WlziPJJZYYlGlTh+QOzdnT OKNOB6HyONOjPe/iLeOVWfm5+Q2H1okKsvSZmVmMd6OJ2PFNedWoV9/WVuxEyQPmsgop UMAQ== X-Gm-Message-State: AGi0PuaR6rlJkD3EJpJV5S3QhRvfoX2YKYnmdKYds8gc6xobN0GZrsk1 rZMnSAdaG7wZ/Vi4xCGXGY1j9gZa5ZGTLA== X-Google-Smtp-Source: APiQypIG1roLGNJ8l8EAirmy+i/A2hW9SaJQVr7TLsaM0uh9SNNoEQ4/xsCNVtpgrjJUxUfj9SeynQ== X-Received: by 2002:a05:600c:21ca:: with SMTP id x10mr2459835wmj.113.1588247520173; Thu, 30 Apr 2020 04:52:00 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/31] hw/misc/zynq_slcr: add clock generation for uarts Date: Thu, 30 Apr 2020 12:51:25 +0100 Message-Id: <20200430115142.13430-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200430115142.13430-1-peter.maydell@linaro.org> References: <20200430115142.13430-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::344; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x344.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Damien Hedde Add some clocks to zynq_slcr + the main input clock (ps_clk) + the reference clock outputs for each uart (uart0 & 1) This commit also transitional the slcr to multi-phase reset as it is required to initialize the clocks correctly. The clock frequencies are computed using the internal pll & uart configurat= ion registers and the input ps_clk frequency. Signed-off-by: Damien Hedde Reviewed-by: Edgar E. Iglesias Acked-by: Alistair Francis Message-id: 20200406135251.157596-7-damien.hedde@greensocs.com Signed-off-by: Peter Maydell --- hw/misc/zynq_slcr.c | 172 ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 168 insertions(+), 4 deletions(-) diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index b9a38272d96..f7472d1f3c0 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -22,6 +22,7 @@ #include "qemu/log.h" #include "qemu/module.h" #include "hw/registerfields.h" +#include "hw/qdev-clock.h" =20 #ifndef ZYNQ_SLCR_ERR_DEBUG #define ZYNQ_SLCR_ERR_DEBUG 0 @@ -45,6 +46,12 @@ REG32(LOCKSTA, 0x00c) REG32(ARM_PLL_CTRL, 0x100) REG32(DDR_PLL_CTRL, 0x104) REG32(IO_PLL_CTRL, 0x108) +/* fields for [ARM|DDR|IO]_PLL_CTRL registers */ + FIELD(xxx_PLL_CTRL, PLL_RESET, 0, 1) + FIELD(xxx_PLL_CTRL, PLL_PWRDWN, 1, 1) + FIELD(xxx_PLL_CTRL, PLL_BYPASS_QUAL, 3, 1) + FIELD(xxx_PLL_CTRL, PLL_BYPASS_FORCE, 4, 1) + FIELD(xxx_PLL_CTRL, PLL_FPDIV, 12, 7) REG32(PLL_STATUS, 0x10c) REG32(ARM_PLL_CFG, 0x110) REG32(DDR_PLL_CFG, 0x114) @@ -64,6 +71,10 @@ REG32(SMC_CLK_CTRL, 0x148) REG32(LQSPI_CLK_CTRL, 0x14c) REG32(SDIO_CLK_CTRL, 0x150) REG32(UART_CLK_CTRL, 0x154) + FIELD(UART_CLK_CTRL, CLKACT0, 0, 1) + FIELD(UART_CLK_CTRL, CLKACT1, 1, 1) + FIELD(UART_CLK_CTRL, SRCSEL, 4, 2) + FIELD(UART_CLK_CTRL, DIVISOR, 8, 6) REG32(SPI_CLK_CTRL, 0x158) REG32(CAN_CLK_CTRL, 0x15c) REG32(CAN_MIOCLK_CTRL, 0x160) @@ -179,11 +190,127 @@ typedef struct ZynqSLCRState { MemoryRegion iomem; =20 uint32_t regs[ZYNQ_SLCR_NUM_REGS]; + + Clock *ps_clk; + Clock *uart0_ref_clk; + Clock *uart1_ref_clk; } ZynqSLCRState; =20 -static void zynq_slcr_reset(DeviceState *d) +/* + * return the output frequency of ARM/DDR/IO pll + * using input frequency and PLL_CTRL register + */ +static uint64_t zynq_slcr_compute_pll(uint64_t input, uint32_t ctrl_reg) { - ZynqSLCRState *s =3D ZYNQ_SLCR(d); + uint32_t mult =3D ((ctrl_reg & R_xxx_PLL_CTRL_PLL_FPDIV_MASK) >> + R_xxx_PLL_CTRL_PLL_FPDIV_SHIFT); + + /* first, check if pll is bypassed */ + if (ctrl_reg & R_xxx_PLL_CTRL_PLL_BYPASS_FORCE_MASK) { + return input; + } + + /* is pll disabled ? */ + if (ctrl_reg & (R_xxx_PLL_CTRL_PLL_RESET_MASK | + R_xxx_PLL_CTRL_PLL_PWRDWN_MASK)) { + return 0; + } + + /* frequency multiplier -> period division */ + return input / mult; +} + +/* + * return the output period of a clock given: + * + the periods in an array corresponding to input mux selector + * + the register xxx_CLK_CTRL value + * + enable bit index in ctrl register + * + * This function makes the assumption that the ctrl_reg value is organized= as + * follows: + * + bits[13:8] clock frequency divisor + * + bits[5:4] clock mux selector (index in array) + * + bits[index] clock enable + */ +static uint64_t zynq_slcr_compute_clock(const uint64_t periods[], + uint32_t ctrl_reg, + unsigned index) +{ + uint32_t srcsel =3D extract32(ctrl_reg, 4, 2); /* bits [5:4] */ + uint32_t divisor =3D extract32(ctrl_reg, 8, 6); /* bits [13:8] */ + + /* first, check if clock is disabled */ + if (((ctrl_reg >> index) & 1u) =3D=3D 0) { + return 0; + } + + /* + * according to the Zynq technical ref. manual UG585 v1.12.2 in + * Clocks chapter, section 25.10.1 page 705: + * "The 6-bit divider provides a divide range of 1 to 63" + * We follow here what is implemented in linux kernel and consider + * the 0 value as a bypass (no division). + */ + /* frequency divisor -> period multiplication */ + return periods[srcsel] * (divisor ? divisor : 1u); +} + +/* + * macro helper around zynq_slcr_compute_clock to avoid repeating + * the register name. + */ +#define ZYNQ_COMPUTE_CLK(state, plls, reg, enable_field) \ + zynq_slcr_compute_clock((plls), (state)->regs[reg], \ + reg ## _ ## enable_field ## _SHIFT) + +/** + * Compute and set the ouputs clocks periods. + * But do not propagate them further. Connected clocks + * will not receive any updates (See zynq_slcr_compute_clocks()) + */ +static void zynq_slcr_compute_clocks(ZynqSLCRState *s) +{ + uint64_t ps_clk =3D clock_get(s->ps_clk); + + /* consider outputs clocks are disabled while in reset */ + if (device_is_in_reset(DEVICE(s))) { + ps_clk =3D 0; + } + + uint64_t io_pll =3D zynq_slcr_compute_pll(ps_clk, s->regs[R_IO_PLL_CTR= L]); + uint64_t arm_pll =3D zynq_slcr_compute_pll(ps_clk, s->regs[R_ARM_PLL_C= TRL]); + uint64_t ddr_pll =3D zynq_slcr_compute_pll(ps_clk, s->regs[R_DDR_PLL_C= TRL]); + + uint64_t uart_mux[4] =3D {io_pll, io_pll, arm_pll, ddr_pll}; + + /* compute uartX reference clocks */ + clock_set(s->uart0_ref_clk, + ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT0)); + clock_set(s->uart1_ref_clk, + ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT1)); +} + +/** + * Propagate the outputs clocks. + * zynq_slcr_compute_clocks() should have been called before + * to configure them. + */ +static void zynq_slcr_propagate_clocks(ZynqSLCRState *s) +{ + clock_propagate(s->uart0_ref_clk); + clock_propagate(s->uart1_ref_clk); +} + +static void zynq_slcr_ps_clk_callback(void *opaque) +{ + ZynqSLCRState *s =3D (ZynqSLCRState *) opaque; + zynq_slcr_compute_clocks(s); + zynq_slcr_propagate_clocks(s); +} + +static void zynq_slcr_reset_init(Object *obj, ResetType type) +{ + ZynqSLCRState *s =3D ZYNQ_SLCR(obj); int i; =20 DB_PRINT("RESET\n"); @@ -277,6 +404,23 @@ static void zynq_slcr_reset(DeviceState *d) s->regs[R_DDRIOB + 12] =3D 0x00000021; } =20 +static void zynq_slcr_reset_hold(Object *obj) +{ + ZynqSLCRState *s =3D ZYNQ_SLCR(obj); + + /* will disable all output clocks */ + zynq_slcr_compute_clocks(s); + zynq_slcr_propagate_clocks(s); +} + +static void zynq_slcr_reset_exit(Object *obj) +{ + ZynqSLCRState *s =3D ZYNQ_SLCR(obj); + + /* will compute output clocks according to ps_clk and registers */ + zynq_slcr_compute_clocks(s); + zynq_slcr_propagate_clocks(s); +} =20 static bool zynq_slcr_check_offset(hwaddr offset, bool rnw) { @@ -409,6 +553,13 @@ static void zynq_slcr_write(void *opaque, hwaddr offse= t, qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); } break; + case R_IO_PLL_CTRL: + case R_ARM_PLL_CTRL: + case R_DDR_PLL_CTRL: + case R_UART_CLK_CTRL: + zynq_slcr_compute_clocks(s); + zynq_slcr_propagate_clocks(s); + break; } } =20 @@ -418,6 +569,13 @@ static const MemoryRegionOps slcr_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 +static const ClockPortInitArray zynq_slcr_clocks =3D { + QDEV_CLOCK_IN(ZynqSLCRState, ps_clk, zynq_slcr_ps_clk_callback), + QDEV_CLOCK_OUT(ZynqSLCRState, uart0_ref_clk), + QDEV_CLOCK_OUT(ZynqSLCRState, uart1_ref_clk), + QDEV_CLOCK_END +}; + static void zynq_slcr_init(Object *obj) { ZynqSLCRState *s =3D ZYNQ_SLCR(obj); @@ -425,14 +583,17 @@ static void zynq_slcr_init(Object *obj) memory_region_init_io(&s->iomem, obj, &slcr_ops, s, "slcr", ZYNQ_SLCR_MMIO_SIZE); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); + + qdev_init_clocks(DEVICE(obj), zynq_slcr_clocks); } =20 static const VMStateDescription vmstate_zynq_slcr =3D { .name =3D "zynq_slcr", - .version_id =3D 2, + .version_id =3D 3, .minimum_version_id =3D 2, .fields =3D (VMStateField[]) { VMSTATE_UINT32_ARRAY(regs, ZynqSLCRState, ZYNQ_SLCR_NUM_REGS), + VMSTATE_CLOCK_V(ps_clk, ZynqSLCRState, 3), VMSTATE_END_OF_LIST() } }; @@ -440,9 +601,12 @@ static const VMStateDescription vmstate_zynq_slcr =3D { static void zynq_slcr_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 dc->vmsd =3D &vmstate_zynq_slcr; - dc->reset =3D zynq_slcr_reset; + rc->phases.enter =3D zynq_slcr_reset_init; + rc->phases.hold =3D zynq_slcr_reset_hold; + rc->phases.exit =3D zynq_slcr_reset_exit; } =20 static const TypeInfo zynq_slcr_info =3D { --=20 2.20.1 From nobody Thu May 2 02:03:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1588247908; cv=none; d=zohomail.com; s=zohoarc; b=cae0Z7CzADHgw0bAVtmmRe0wtRz1Edbjz9hv0PxfE5Gun5GHc8MnJq87lZJEyjYL/SwGwipR9MyOy7y3PtYf+zEyQkP0TKfWWUZVHey5RVHTRfZdUPJWtGx7ONtciT74c/LI3K81KVN0P2K4HP0yw2wKjTAAwQhxiJSXAqvXkdA= ARC-Message-Signature: i=1; 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Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::331 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Damien Hedde Switch the cadence uart to multi-phase reset and add the reference clock input. The input clock frequency is added to the migration structure. The reference clock controls the baudrate generation. If it disabled, any input characters and events are ignored. If this clock remains unconnected, the uart behaves as before (it default to a 50MHz ref clock). Signed-off-by: Damien Hedde Reviewed-by: Edgar E. Iglesias Reviewed-by: Alistair Francis Message-id: 20200406135251.157596-8-damien.hedde@greensocs.com Signed-off-by: Peter Maydell --- include/hw/char/cadence_uart.h | 1 + hw/char/cadence_uart.c | 73 +++++++++++++++++++++++++++++----- hw/char/trace-events | 3 ++ 3 files changed, 67 insertions(+), 10 deletions(-) diff --git a/include/hw/char/cadence_uart.h b/include/hw/char/cadence_uart.h index 47cec956c4b..2a179a572fc 100644 --- a/include/hw/char/cadence_uart.h +++ b/include/hw/char/cadence_uart.h @@ -49,6 +49,7 @@ typedef struct { CharBackend chr; qemu_irq irq; QEMUTimer *fifo_trigger_handle; + Clock *refclk; } CadenceUARTState; =20 static inline DeviceState *cadence_uart_create(hwaddr addr, diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index 22e47972f15..e196906c923 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -31,6 +31,8 @@ #include "qemu/module.h" #include "hw/char/cadence_uart.h" #include "hw/irq.h" +#include "hw/qdev-clock.h" +#include "trace.h" =20 #ifdef CADENCE_UART_ERR_DEBUG #define DB_PRINT(...) do { \ @@ -97,7 +99,7 @@ #define LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SH) #define REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SH) =20 -#define UART_INPUT_CLK 50000000 +#define UART_DEFAULT_REF_CLK (50 * 1000 * 1000) =20 #define R_CR (0x00/4) #define R_MR (0x04/4) @@ -171,12 +173,15 @@ static void uart_send_breaks(CadenceUARTState *s) static void uart_parameters_setup(CadenceUARTState *s) { QEMUSerialSetParams ssp; - unsigned int baud_rate, packet_size; + unsigned int baud_rate, packet_size, input_clk; + input_clk =3D clock_get_hz(s->refclk); =20 - baud_rate =3D (s->r[R_MR] & UART_MR_CLKS) ? - UART_INPUT_CLK / 8 : UART_INPUT_CLK; + baud_rate =3D (s->r[R_MR] & UART_MR_CLKS) ? input_clk / 8 : input_clk; + baud_rate /=3D (s->r[R_BRGR] * (s->r[R_BDIV] + 1)); + trace_cadence_uart_baudrate(baud_rate); + + ssp.speed =3D baud_rate; =20 - ssp.speed =3D baud_rate / (s->r[R_BRGR] * (s->r[R_BDIV] + 1)); packet_size =3D 1; =20 switch (s->r[R_MR] & UART_MR_PAR) { @@ -215,6 +220,13 @@ static void uart_parameters_setup(CadenceUARTState *s) } =20 packet_size +=3D ssp.data_bits + ssp.stop_bits; + if (ssp.speed =3D=3D 0) { + /* + * Avoid division-by-zero below. + * TODO: find something better + */ + ssp.speed =3D 1; + } s->char_tx_time =3D (NANOSECONDS_PER_SECOND / ssp.speed) * packet_size; qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); } @@ -340,6 +352,11 @@ static void uart_receive(void *opaque, const uint8_t *= buf, int size) CadenceUARTState *s =3D opaque; uint32_t ch_mode =3D s->r[R_MR] & UART_MR_CHMODE; =20 + /* ignore characters when unclocked or in reset */ + if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) { + return; + } + if (ch_mode =3D=3D NORMAL_MODE || ch_mode =3D=3D ECHO_MODE) { uart_write_rx_fifo(opaque, buf, size); } @@ -353,6 +370,11 @@ static void uart_event(void *opaque, QEMUChrEvent even= t) CadenceUARTState *s =3D opaque; uint8_t buf =3D '\0'; =20 + /* ignore characters when unclocked or in reset */ + if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) { + return; + } + if (event =3D=3D CHR_EVENT_BREAK) { uart_write_rx_fifo(opaque, &buf, 1); } @@ -462,9 +484,9 @@ static const MemoryRegionOps uart_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 -static void cadence_uart_reset(DeviceState *dev) +static void cadence_uart_reset_init(Object *obj, ResetType type) { - CadenceUARTState *s =3D CADENCE_UART(dev); + CadenceUARTState *s =3D CADENCE_UART(obj); =20 s->r[R_CR] =3D 0x00000128; s->r[R_IMR] =3D 0; @@ -473,6 +495,11 @@ static void cadence_uart_reset(DeviceState *dev) s->r[R_BRGR] =3D 0x0000028B; s->r[R_BDIV] =3D 0x0000000F; s->r[R_TTRIG] =3D 0x00000020; +} + +static void cadence_uart_reset_hold(Object *obj) +{ + CadenceUARTState *s =3D CADENCE_UART(obj); =20 uart_rx_reset(s); uart_tx_reset(s); @@ -491,6 +518,14 @@ static void cadence_uart_realize(DeviceState *dev, Err= or **errp) uart_event, NULL, s, NULL, true); } =20 +static void cadence_uart_refclk_update(void *opaque) +{ + CadenceUARTState *s =3D opaque; + + /* recompute uart's speed on clock change */ + uart_parameters_setup(s); +} + static void cadence_uart_init(Object *obj) { SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); @@ -500,9 +535,23 @@ static void cadence_uart_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem); sysbus_init_irq(sbd, &s->irq); =20 + s->refclk =3D qdev_init_clock_in(DEVICE(obj), "refclk", + cadence_uart_refclk_update, s); + /* initialize the frequency in case the clock remains unconnected */ + clock_set_hz(s->refclk, UART_DEFAULT_REF_CLK); + s->char_tx_time =3D (NANOSECONDS_PER_SECOND / 9600) * 10; } =20 +static int cadence_uart_pre_load(void *opaque) +{ + CadenceUARTState *s =3D opaque; + + /* the frequency will be overriden if the refclk field is present */ + clock_set_hz(s->refclk, UART_DEFAULT_REF_CLK); + return 0; +} + static int cadence_uart_post_load(void *opaque, int version_id) { CadenceUARTState *s =3D opaque; @@ -521,8 +570,9 @@ static int cadence_uart_post_load(void *opaque, int ver= sion_id) =20 static const VMStateDescription vmstate_cadence_uart =3D { .name =3D "cadence_uart", - .version_id =3D 2, + .version_id =3D 3, .minimum_version_id =3D 2, + .pre_load =3D cadence_uart_pre_load, .post_load =3D cadence_uart_post_load, .fields =3D (VMStateField[]) { VMSTATE_UINT32_ARRAY(r, CadenceUARTState, CADENCE_UART_R_MAX), @@ -534,8 +584,9 @@ static const VMStateDescription vmstate_cadence_uart = =3D { VMSTATE_UINT32(tx_count, CadenceUARTState), VMSTATE_UINT32(rx_wpos, CadenceUARTState), VMSTATE_TIMER_PTR(fifo_trigger_handle, CadenceUARTState), + VMSTATE_CLOCK_V(refclk, CadenceUARTState, 3), VMSTATE_END_OF_LIST() - } + }, }; =20 static Property cadence_uart_properties[] =3D { @@ -546,10 +597,12 @@ static Property cadence_uart_properties[] =3D { static void cadence_uart_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 dc->realize =3D cadence_uart_realize; dc->vmsd =3D &vmstate_cadence_uart; - dc->reset =3D cadence_uart_reset; + rc->phases.enter =3D cadence_uart_reset_init; + rc->phases.hold =3D cadence_uart_reset_hold; device_class_set_props(dc, cadence_uart_properties); } =20 diff --git a/hw/char/trace-events b/hw/char/trace-events index 6f938301d98..d20eafd56f8 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -97,3 +97,6 @@ exynos_uart_wo_read(uint32_t channel, const char *name, u= int32_t reg) "UART%d: T exynos_uart_rxsize(uint32_t channel, uint32_t size) "UART%d: Rx FIFO size:= %d" exynos_uart_channel_error(uint32_t channel) "Wrong UART channel number: %d" exynos_uart_rx_timeout(uint32_t channel, uint32_t stat, uint32_t intsp) "U= ART%d: Rx timeout stat=3D0x%x intsp=3D0x%x" + +# hw/char/cadence_uart.c +cadence_uart_baudrate(unsigned baudrate) "baudrate %u" --=20 2.20.1 From nobody Thu May 2 02:03:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j22sm491518wre.84.2020.04.30.04.52.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 04:52:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=/JOpwnlKiYDdU9XInaBUbtyuT88O8qiGy04kfKAS7w8=; b=E0vWChsepRLNXmVk+DI/u6XpCvkKqovYV3OzIm04wE700TTJn2ztqeSv9JBEIWVN7n 1bEj9o8JMToKLF0CFB6h00H+rLhZ31INM78IPf7ajMc6A7zU4XAkxirpUDJLuLNH76IJ zIkVpNYwSI46VtLramFuk0WDpMwsO9MLZsPGayAue3jQPkDf4lWBYeEWKWlEHXnVJL9u yjM+xMP2fapHkuiqcKwOPZpi3Ev5tNTTc/yrfaMHRfkbteXPLkj0Wf0aSgzjkCFcSIci z82dEyau9ODMoWUFHhua+Bu9sqFY6AQBK/y4FSlhWZ29eBVhe9KFcmx2gW7OoFAqwwiZ Q2iw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/JOpwnlKiYDdU9XInaBUbtyuT88O8qiGy04kfKAS7w8=; b=iRelBI2jDhbFpjQJcdcRoiBzIg18zuTNpzEaDNzpybHVnlaFA5P9UzoTo5J2XwjoQz 93boUkFfOCFLLQkg2oWmjcmb/MWsp0poBTB7gZOpzxrzNRKEtZnTDIWSe1YyNxO+R5MH tPpAEuULuDyXju/IeDexA1ptsNKRr3OgLHZZBVyOXQXiX9URgUQqPDsj9AAR30L46lR2 Y6+f6/p6KZobszEAY7cZAphbyk4KXTaJ4n3S4UPo79k7YHyp9pc8jP28MbUxkRG6o7nq ufKjgURGtRDYZWjNLuaxxa6GeqNs7nnT7cevf/cd1Vw/wxhq+oeeJ8vBA0oczeFGkdSa Hosg== X-Gm-Message-State: AGi0PuYIXmwdhY7DTvcoF+iPLAZYYAx2dbr15/C3vOVSufHsE6tVr5tK 6fIDszc0TiNCDUTCjW6PdeZdnEy/U/vZWA== X-Google-Smtp-Source: APiQypJh0KmWp1c2rciu3V86ynqIC8zfkZ5VZ/av87IXFvOoT8EhW8RGcKKMr47CKn0XyGYRfpDaFQ== X-Received: by 2002:a1c:2d02:: with SMTP id t2mr2597783wmt.98.1588247522584; Thu, 30 Apr 2020 04:52:02 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/31] hw/arm/xilinx_zynq: connect uart clocks to slcr Date: Thu, 30 Apr 2020 12:51:27 +0100 Message-Id: <20200430115142.13430-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200430115142.13430-1-peter.maydell@linaro.org> References: <20200430115142.13430-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::32c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Damien Hedde Add the connection between the slcr's output clocks and the uarts inputs. Also add the main board clock 'ps_clk', which is hard-coded to 33.33MHz (the default frequency). This clock is used to feed the slcr's input clock. Signed-off-by: Damien Hedde Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Message-id: 20200406135251.157596-9-damien.hedde@greensocs.com Signed-off-by: Peter Maydell --- hw/arm/xilinx_zynq.c | 57 +++++++++++++++++++++++++++++++++++++------- 1 file changed, 49 insertions(+), 8 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 571cdcd599e..91b498dd5d3 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -35,6 +35,15 @@ #include "hw/char/cadence_uart.h" #include "hw/net/cadence_gem.h" #include "hw/cpu/a9mpcore.h" +#include "hw/qdev-clock.h" +#include "sysemu/reset.h" + +#define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9") +#define ZYNQ_MACHINE(obj) \ + OBJECT_CHECK(ZynqMachineState, (obj), TYPE_ZYNQ_MACHINE) + +/* board base frequency: 33.333333 MHz */ +#define PS_CLK_FREQUENCY (100 * 1000 * 1000 / 3) =20 #define NUM_SPI_FLASHES 4 #define NUM_QSPI_FLASHES 2 @@ -75,6 +84,11 @@ static const int dma_irqs[8] =3D { 0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \ 0xe5801000 + (addr) =20 +typedef struct ZynqMachineState { + MachineState parent; + Clock *ps_clk; +} ZynqMachineState; + static void zynq_write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info) { @@ -159,10 +173,11 @@ static inline void zynq_init_spi_flashes(uint32_t bas= e_addr, qemu_irq irq, =20 static void zynq_init(MachineState *machine) { + ZynqMachineState *zynq_machine =3D ZYNQ_MACHINE(machine); ARMCPU *cpu; MemoryRegion *address_space_mem =3D get_system_memory(); MemoryRegion *ocm_ram =3D g_new(MemoryRegion, 1); - DeviceState *dev; + DeviceState *dev, *slcr; SysBusDevice *busdev; qemu_irq pic[64]; int n; @@ -206,9 +221,18 @@ static void zynq_init(MachineState *machine) 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa, 0); =20 - dev =3D qdev_create(NULL, "xilinx,zynq_slcr"); - qdev_init_nofail(dev); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000); + /* Create slcr, keep a pointer to connect clocks */ + slcr =3D qdev_create(NULL, "xilinx,zynq_slcr"); + qdev_init_nofail(slcr); + sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000); + + /* Create the main clock source, and feed slcr with it */ + zynq_machine->ps_clk =3D CLOCK(object_new(TYPE_CLOCK)); + object_property_add_child(OBJECT(zynq_machine), "ps_clk", + OBJECT(zynq_machine->ps_clk), &error_abort); + object_unref(OBJECT(zynq_machine->ps_clk)); + clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY); + qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk); =20 dev =3D qdev_create(NULL, TYPE_A9MPCORE_PRIV); qdev_prop_set_uint32(dev, "num-cpu", 1); @@ -229,8 +253,12 @@ static void zynq_init(MachineState *machine) sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]); sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]); =20 - cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0)); - cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1)); + dev =3D cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_h= d(0)); + qdev_connect_clock_in(dev, "refclk", + qdev_get_clock_out(slcr, "uart0_ref_clk")); + dev =3D cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_h= d(1)); + qdev_connect_clock_in(dev, "refclk", + qdev_get_clock_out(slcr, "uart1_ref_clk")); =20 sysbus_create_varargs("cadence_ttc", 0xF8001000, pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NU= LL); @@ -308,8 +336,9 @@ static void zynq_init(MachineState *machine) arm_load_kernel(ARM_CPU(first_cpu), machine, &zynq_binfo); } =20 -static void zynq_machine_init(MachineClass *mc) +static void zynq_machine_class_init(ObjectClass *oc, void *data) { + MachineClass *mc =3D MACHINE_CLASS(oc); mc->desc =3D "Xilinx Zynq Platform Baseboard for Cortex-A9"; mc->init =3D zynq_init; mc->max_cpus =3D 1; @@ -319,4 +348,16 @@ static void zynq_machine_init(MachineClass *mc) mc->default_ram_id =3D "zynq.ext_ram"; } =20 -DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init) +static const TypeInfo zynq_machine_type =3D { + .name =3D TYPE_ZYNQ_MACHINE, + .parent =3D TYPE_MACHINE, + .class_init =3D zynq_machine_class_init, + .instance_size =3D sizeof(ZynqMachineState), +}; + +static void zynq_machine_register_types(void) +{ + type_register_static(&zynq_machine_type); +} + +type_init(zynq_machine_register_types) --=20 2.20.1 From nobody Thu May 2 02:03:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j22sm491518wre.84.2020.04.30.04.52.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 04:52:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=O3w8HyaAfJtw7bxuseWGtHyrXHMdqtOWwjxtX6t+QRI=; b=LJPm61l1x/msDMFCY74yUWnCfFx/MNcl3PkFuj5s+zascAqHwqTp8OD7chQhSzmnjM 3RDvMPOncTranY/LSuYGXfleOu57oSfY9wKll/C5PS1aU8SefBrR1rkArTkGZs5VamAh zoV05IDns1Ysq0HN6XhlLuGZwFhRvV88kvogRzpHO+9K3hy9yUV/Ndfze8yVAbMUDlKD 2anrl+AtVEwNxWAOTaEQ+blRNbb++fvcDj1jG2BDibsHvTe1Oe9BxQsz2DjdOeDwoUwg tE3bx1FF8JtKeWvo/fsq0cXmtodEELgIQdphYEdf4CKmQArgpBJ3gjfAsw9tzRG1DOO8 Tf0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=O3w8HyaAfJtw7bxuseWGtHyrXHMdqtOWwjxtX6t+QRI=; b=qmSMsNjI4gBVkbHX3CzJIsCopSaigl8MQhdmOxJOqRxbAQYLYLDnoygxW2mPcBgN6C QMGE3PZmWaTDs0UC7LEPxP+rg2dphFfQnHY4b+var1/uVb9VZXXYncOOTZEQC21UxP2M hD0Rw8Y+RAY7LVr7m2h9YU2qmz/qnUQmfO9jhqmoNl95o6AEI04GCjSx179MwPDUmEWy a0qSIS3kesiifa1TY7kbF+1ZQzoYp9psvJNEgNcJTf+OyP6a679QmdonVP6h23JV9heP wFQaQKgclCathuLt3x4lojyOQjgjyFYMHQhkBj51howMYtEvD5I515GG4g5E9WWyW4NS uGbQ== X-Gm-Message-State: AGi0PuZimHIYyga58u9WGCgHziyrsh5vcTTJGCpd0mDq77lu83ZePM/e QP2qTq50QpM0DmyoIiJvFjcKkn6w1N0jJw== X-Google-Smtp-Source: APiQypIIWj4n1YbzQSWfzwy94G17VcnmwYrO607JxjjtndZEsv1Ws6LhnCWxnTphPz/MYtlxW4auqQ== X-Received: by 2002:a7b:c104:: with SMTP id w4mr2606415wmi.8.1588247523570; Thu, 30 Apr 2020 04:52:03 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/31] qdev-monitor: print the device's clock with info qtree Date: Thu, 30 Apr 2020 12:51:28 +0100 Message-Id: <20200430115142.13430-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200430115142.13430-1-peter.maydell@linaro.org> References: <20200430115142.13430-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::32d X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Damien Hedde This prints the clocks attached to a DeviceState when using "info qtree" monitor command. For every clock, it displays the direction, the name and if the clock is forwarded. For input clock, it displays also the frequency. This is based on the original work of Frederic Konrad. Here follows a sample of `info qtree` output on xilinx_zynq machine after linux boot with only one uart clocked: > bus: main-system-bus > type System > [...] > dev: cadence_uart, id "" > gpio-out "sysbus-irq" 1 > clock-in "refclk" freq_hz=3D0.000000e+00 > chardev =3D "" > mmio 00000000e0001000/0000000000001000 > dev: cadence_uart, id "" > gpio-out "sysbus-irq" 1 > clock-in "refclk" freq_hz=3D1.375661e+07 > chardev =3D "serial0" > mmio 00000000e0000000/0000000000001000 > [...] > dev: xilinx,zynq_slcr, id "" > clock-out "uart1_ref_clk" freq_hz=3D0.000000e+00 > clock-out "uart0_ref_clk" freq_hz=3D1.375661e+07 > clock-in "ps_clk" freq_hz=3D3.333333e+07 > mmio 00000000f8000000/0000000000001000 Signed-off-by: Damien Hedde Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias Message-id: 20200406135251.157596-10-damien.hedde@greensocs.com Signed-off-by: Peter Maydell --- qdev-monitor.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/qdev-monitor.c b/qdev-monitor.c index 9833b335496..56cee1483fa 100644 --- a/qdev-monitor.c +++ b/qdev-monitor.c @@ -38,6 +38,7 @@ #include "migration/misc.h" #include "migration/migration.h" #include "qemu/cutils.h" +#include "hw/clock.h" =20 /* * Aliases were a bad idea from the start. Let's keep them @@ -737,6 +738,7 @@ static void qdev_print(Monitor *mon, DeviceState *dev, = int indent) ObjectClass *class; BusState *child; NamedGPIOList *ngl; + NamedClockList *ncl; =20 qdev_printf("dev: %s, id \"%s\"\n", object_get_typename(OBJECT(dev)), dev->id ? dev->id : ""); @@ -751,6 +753,13 @@ static void qdev_print(Monitor *mon, DeviceState *dev,= int indent) ngl->num_out); } } + QLIST_FOREACH(ncl, &dev->clocks, node) { + qdev_printf("clock-%s%s \"%s\" freq_hz=3D%e\n", + ncl->output ? "out" : "in", + ncl->alias ? " (alias)" : "", + ncl->name, + CLOCK_PERIOD_TO_HZ(1.0 * clock_get(ncl->clock))); + } class =3D object_get_class(OBJECT(dev)); do { qdev_print_props(mon, dev, DEVICE_CLASS(class)->props_, indent); --=20 2.20.1 From nobody Thu May 2 02:03:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1588248016; cv=none; d=zohomail.com; s=zohoarc; b=iXq6RK2mJa5d0/4TjIiDHxQVMYXtOwcHO9ZORI1vq09yHoqXE5RG1cPrdds+pBouLPPlRsOTiEaZ0OO8JLmeFrlRtisT4393pGGTS4z1Vwe89lon0xuiCrvmLhjDNmGECdN0ja9DUjMQ6R9KjNxFuHAH2lEZpP/EmhnC9GI+sKM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588248016; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=uf9EjZlK3PWSZbbcBZG8iV17wJ+d4IMJ5+LdrfTNYaM=; b=jf5EmmPJ6m5MIzcWXmCoZJMJ9g7mwiijY5YVSB+2IEOgJARApCZUC2NorD7dIiqrqRhGBDzrhYKsFPU5wh46vVPjyE7F3wrvi//ec+7HzPNpvcSJd57sU74y6yidT+nnvGMtrIkHBtbYj9VMoCduEXRQDvfISnt+AnCDP22tLs8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1588248016779897.5575447188966; Thu, 30 Apr 2020 05:00:16 -0700 (PDT) Received: from localhost ([::1]:41272 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU7rR-0002uc-Cs for importer@patchew.org; Thu, 30 Apr 2020 08:00:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33858) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU7jf-0003AA-1a for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:13 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.90_1) (envelope-from ) id 1jU7jb-0000PQ-1I for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:10 -0400 Received: from mail-wr1-x441.google.com ([2a00:1450:4864:20::441]:46955) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jU7ja-0000Oi-HO for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:06 -0400 Received: by mail-wr1-x441.google.com with SMTP id f13so6474361wrm.13 for ; Thu, 30 Apr 2020 04:52:06 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j22sm491518wre.84.2020.04.30.04.52.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 04:52:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=uf9EjZlK3PWSZbbcBZG8iV17wJ+d4IMJ5+LdrfTNYaM=; b=g4eFKGwKXdg6+ROOZwqokisERdUzIHLGcXlN+jRPv3Iy0hlBGih4whSamA3bAexaH2 7rc3OU3cIfURER3RDB29k3HTf5pRF2tywlcCoW6oq2EeNDdIORjFMmN2UMv0Bg8ogdJC wv5aRuEh1hIt6bM+cdGQ3YYqT3YWpRgD8I/KDEzgvxLwsW96Dfvd4fSBNWQ/9u59gPLB x4rrJh1NQxri9koZgWzaMOksUAflc8SyWcnYOuDxlhOvB2U1c+TWW+5R1H6eFmT8GC/4 cP6a4/8eko6EJ9wzIBoAZ/fJZfcMckk492uf6VEa5PLNpBAVxg9RU3ETKHOodekFXS9u msdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uf9EjZlK3PWSZbbcBZG8iV17wJ+d4IMJ5+LdrfTNYaM=; b=OK2jU0I25e69vvf01asuFAR5bVqW9eblM/hG3B09QsKAV+wxTW01nT1Eji9rIM7RAb +iX6xavdz6xZPMsaz0Gq7nQ2OX0XCuVPUTsPwxE5J1Q3HEjJnQkraJgPMbTIcwqa/fen acTAaHQI+1pewaLDOzMGlrbOtyIo3wVmg6E+8vBoKTmPH4ULMG/xiTmsLjDbUdqCQDnN ib/hGsUTaVMl7oQpAujE6JjaeThRJFYkeg7JXy9yCffmJx3vA87H7ycXw7nxQk+Abt3N hsTbussdoLXNNJDoj5eZi2RGvri8mIwZ9Pu2jZd0j+4Ik0V3ir+i34gDfG4/s34YyUR1 an1A== X-Gm-Message-State: AGi0PuZNWTrHNftUy4e+GZENGj/xr1hmPCKlbeJdeHbx8mn99mMmrzQ1 Rlk/e9XmtHNPa8CY9JjwLT5xdRqQWZqngw== X-Google-Smtp-Source: APiQypIP7DpDpu9KoX6vbk1eIvexpZCWundeZn90FMynVKI+cWM9YYvhi0TO0zVYofjKfDjlkmX0xw== X-Received: by 2002:adf:aa92:: with SMTP id h18mr3648312wrc.20.1588247524653; Thu, 30 Apr 2020 04:52:04 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/31] hw/arm: versal: Setup the ADMA with 128bit bus-width Date: Thu, 30 Apr 2020 12:51:29 +0100 Message-Id: <20200430115142.13430-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200430115142.13430-1-peter.maydell@linaro.org> References: <20200430115142.13430-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::441; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x441.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Setup the ADMA with 128bit bus-width. This matters when FIXED BURST mode is used. Signed-off-by: Edgar E. Iglesias Reviewed-by: Alistair Francis Reviewed-by: Luc Michel Message-id: 20200417153800.27399-2-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- hw/arm/xlnx-versal.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index cb0122a3a68..94460f2343b 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -205,6 +205,8 @@ static void versal_create_admas(Versal *s, qemu_irq *pi= c) =20 dev =3D qdev_create(NULL, "xlnx.zdma"); s->lpd.iou.adma[i] =3D SYS_BUS_DEVICE(dev); + object_property_set_int(OBJECT(s->lpd.iou.adma[i]), 128, "bus-widt= h", + &error_abort); object_property_add_child(OBJECT(s), name, OBJECT(dev), &error_fat= al); qdev_init_nofail(dev); =20 --=20 2.20.1 From nobody Thu May 2 02:03:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1588248362; cv=none; d=zohomail.com; s=zohoarc; b=e6DBpDfKXRgnClo9TqKjoW8FTr7L8KVZcxYnJekIs/H3mhlh9vkotHalefpAKI/K0G9V1I/E6dj7p/ts5OtnbraBB/PDaajqE2BmdhJ88xB0ErOewt+/GEXS0n0WYZW0g218fX+2LMTIOOSnqQaJ6G+Wb8DKwd5fMWAVqbtepMQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588248362; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=JuJOerU6YgiBx+PFXtHPe81yp45kyRPlfXNEXqsYBhk=; b=iQIGxXVXxCT0Nf0BLuMr6SmC9pUuOH1KomjCa1WRwWeqGIyutimV61mYJHTgkiTPHYFkd3l2HQN9Pj5geOR2tBPj3Yj4hfNUDgPCrS6c0JzGWdsMrUDGW6bpoA3IInTu3HKBP2KKh2da4NbsOnGSZKyFwk/SQXJmclg4lmdIj5A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1588248362434465.9216013433303; Thu, 30 Apr 2020 05:06:02 -0700 (PDT) Received: from localhost ([::1]:60884 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU7x3-00043Q-02 for importer@patchew.org; Thu, 30 Apr 2020 08:06:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33866) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU7jf-0003CA-R7 for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:14 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.90_1) (envelope-from ) id 1jU7jb-0000Po-UE for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:11 -0400 Received: from mail-wr1-x443.google.com ([2a00:1450:4864:20::443]:46957) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jU7jb-0000PG-FJ for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:07 -0400 Received: by mail-wr1-x443.google.com with SMTP id f13so6474430wrm.13 for ; Thu, 30 Apr 2020 04:52:07 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j22sm491518wre.84.2020.04.30.04.52.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 04:52:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=JuJOerU6YgiBx+PFXtHPe81yp45kyRPlfXNEXqsYBhk=; b=Hw4Aih1j0qnxIB51sU7fnDk4V/KbrlKtHcRFTtudDX439l+jEPN6E1Um6ek/6eFs61 OlcS/PgBt0RHZrwZ1A+15JpLSeKtj/Ukqm3m2nrj6SZDMlY4f4GmwLeBZScqas3TA7xr w/g3J97/xj0IcueFMJeYKKMPfECADnSUvfio0kZnraofXwwNC3brZEVHUy9BQjBi7DQn 1zWvBiTPxqhAzfjmiItGp0rxycHY1VzwLXz3fKWIsJ18lHur1odud9pXGnBDFIqU1CuW XztyMUXLGiQTqPrCLZ7Aivb5LQLPOUeO/ezIZL09sLEiCUKpz9T3bVT2veTPX1imJF5p uHkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JuJOerU6YgiBx+PFXtHPe81yp45kyRPlfXNEXqsYBhk=; b=Lec0OAMR9DrqCI+m9aQxpg5HNkKZ6K7brDhflndWB1mPLsZow64TI4vhR6HWZc9sNg K2OGbujX9B4gIBuUH4JnOaf8g5tbYGvTHpLGUEYk4MBbl+gKVWFKE8BQdaIgTVZicoBA /0/qbO2DOTXPlDz/NWKrIRDVKX6LnjewsSapPygQ6vgSNTDBeRad7Xzsu/uILptap+Zq UG4UaEgPlbTN9EXzloImuiF/w7Krdjr2uMkFIHQ9VSTJwB4FCU2Z3wZWdxCxO6f8IsYD YOkXMie9GKsHFuRWAROwXSKJEgzoKGfjizU11pp1TbpaTICFtczRN/rnNo54GuLEv5p7 Pzig== X-Gm-Message-State: AGi0Pubuk8hYAORtWDIqsXoSWB4IOZhdPZ17UVF86Hl6K5y6J5RlGwBT h/Y08ggRhPzEY6uZO3ITgzhru+qW89kNeQ== X-Google-Smtp-Source: APiQypIM0vR3lLpnWodUOE/KgXc41B1eP1VD/zr7MePdbGMIkwo1h47EPmZ8Hl1W6jek4hXSPLWwdg== X-Received: by 2002:a05:6000:1089:: with SMTP id y9mr1497285wrw.306.1588247525837; Thu, 30 Apr 2020 04:52:05 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/31] Cadence: gem: fix wraparound in 64bit descriptors Date: Thu, 30 Apr 2020 12:51:30 +0100 Message-Id: <20200430115142.13430-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200430115142.13430-1-peter.maydell@linaro.org> References: <20200430115142.13430-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::443; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x443.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Ramon Fried Wraparound of TX descriptor cyclic buffer only updated the low 32 bits of the descriptor. Fix that by checking if we're working with 64bit descriptors. Signed-off-by: Ramon Fried Reviewed-by: Edgar E. Iglesias Message-id: 20200417171736.441607-1-rfried.dev@gmail.com Signed-off-by: Peter Maydell --- hw/net/cadence_gem.c | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 51ec5a072d0..b7b7985bf26 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -1238,7 +1238,14 @@ static void gem_transmit(CadenceGEMState *s) /* read next descriptor */ if (tx_desc_get_wrap(desc)) { tx_desc_set_last(desc); - packet_desc_addr =3D s->regs[GEM_TXQBASE]; + + if (s->regs[GEM_DMACFG] & GEM_DMACFG_ADDR_64B) { + packet_desc_addr =3D s->regs[GEM_TBQPH]; + packet_desc_addr <<=3D 32; + } else { + packet_desc_addr =3D 0; + } + packet_desc_addr |=3D s->regs[GEM_TXQBASE]; } else { packet_desc_addr +=3D 4 * gem_get_desc_len(s, false); } --=20 2.20.1 From nobody Thu May 2 02:03:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1588248217; cv=none; d=zohomail.com; s=zohoarc; b=HBfiIZsS5dISeTWj5Yaj4KoKDfN9s8KETCVqsXdESCXYq9+D8VisrDFGqOfpfvGWhpR1KbXBBDjU5RId/4ifvP/a6yUXdidLj7ZXbWHYMfNK482HAft9W17lX17tz1ov34Q+B4jPs60pot0jKwdocvaOVmpKWNSEeNSpvFvCyqc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588248217; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zZWaiNYQl1jkJl1/u6IcLpSy6OiypfwYvSOe5TPvgPY=; b=LxqMJ8eziCUogJcqv8u0hX/cAk5TGwNGuBncdH6O8oO7y/yPsbejwU0A70pmNulogkFhi3rojhJ4sBw1xTlgJjuWU4md1HUfiwXI5pzQj0ny/8+tZIfctVZDBzt8yQnWJwmfXTioldCke2y803nU9ebwS2NMFh0H2MDsu9SWeZ4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1588248217274945.9875154876687; Thu, 30 Apr 2020 05:03:37 -0700 (PDT) Received: from localhost ([::1]:52798 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU7uh-0008Lk-Ow for importer@patchew.org; Thu, 30 Apr 2020 08:03:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33876) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU7jg-0003Ey-V6 for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:15 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.90_1) (envelope-from ) id 1jU7jd-0000QC-3A for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:12 -0400 Received: from mail-wm1-x343.google.com ([2a00:1450:4864:20::343]:40420) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jU7jc-0000Pk-Hx for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:08 -0400 Received: by mail-wm1-x343.google.com with SMTP id u16so1542429wmc.5 for ; Thu, 30 Apr 2020 04:52:08 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j22sm491518wre.84.2020.04.30.04.52.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 04:52:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=zZWaiNYQl1jkJl1/u6IcLpSy6OiypfwYvSOe5TPvgPY=; b=x+3xyXZDxl+LyZF2TYjFcrkjqvoa9/CXNc1QxCOk9PWqAdQjUTjjNyhZyjKvQjUKT1 ffX+1ZKxmfGX1UrxUE+bS5UAOoVkQb2gNBqYiOOwUwngBtvFW6uQ/rRMcaJ8PmBaAkvl 5+emvsMS+6+ogxmj8L4i9CoohSRwwSXZ93OE+FYECFDSqa6mgPWhreYTflGamwPdpi+5 WnOnGEZB2eKK2Wm5a3P+2E3G3WRc9RG4PabQ5KP3rKZ3m9Dr7pqFU7ZWT69VWgEO9FS+ qHlvDNeG9izV2KhkjZ7M8FxncT8h2zMSpxRgsLn6Xgn77UBByamxjmqALh9My73iBymq cePw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zZWaiNYQl1jkJl1/u6IcLpSy6OiypfwYvSOe5TPvgPY=; b=rtoBmXDvPmSi2hZZ+oPzRY8CSc0tXMCK9fuUGBTx9o9HfviW0mnXGdkgV6EglRSB9h MhY3HcfZOPHtVG7ErMXvuMsHYiTw42s+bPb3PD+oLzfw/44BY/cGkk/eYuLgZzjUJgsl PLrXHzOK8H1CHKDYBjyDat/HtK9cbaTQ/+N5EJjIj3Svwb82HAouzaIdiVFOYotPyiBU y3w02C/MZzVwgxzIdMxRtvo+G9R7MaW7/X/8A41H98eJa/QCwfoifSg7CxRCctjxQwQS nhpHcJzvLuY2m8ikt53AsVeKnqZnV/BY+U19Pqr1Vx/jhpLXP5z+Z8+JJgOyjrfhrdEK 7zvQ== X-Gm-Message-State: AGi0PuaQKLl+VqWUWF0huvwC8Z9N+YlvUwQt+l/vkBjb+n59sOGtr5uO 6BiLP895xt6j0erdkN3heMNCaz88aNzv2w== X-Google-Smtp-Source: APiQypIs/Y55VnIj10Smm6cHsFxP03Htvy43PPc6iWKnRB7yZhmoyybRfvBqzqlDFmz2nN6LayIFOw== X-Received: by 2002:a1c:7ed7:: with SMTP id z206mr2434347wmc.64.1588247526814; Thu, 30 Apr 2020 04:52:06 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/31] net: cadence_gem: clear RX control descriptor Date: Thu, 30 Apr 2020 12:51:31 +0100 Message-Id: <20200430115142.13430-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200430115142.13430-1-peter.maydell@linaro.org> References: <20200430115142.13430-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x343.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Ramon Fried The RX ring descriptors control field is used for setting SOF and EOF (start of frame and end of frame). The SOF and EOF weren't cleared from the previous descriptors, causing inconsistencies in ring buffer. Fix that by clearing the control field of every descriptors we're processing. Signed-off-by: Ramon Fried Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Edgar E. Iglesias Message-id: 20200418085145.489726-1-rfried.dev@gmail.com Signed-off-by: Peter Maydell --- hw/net/cadence_gem.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index b7b7985bf26..22a0b1b1f9a 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -411,6 +411,11 @@ static inline void rx_desc_set_sof(uint32_t *desc) desc[1] |=3D DESC_1_RX_SOF; } =20 +static inline void rx_desc_clear_control(uint32_t *desc) +{ + desc[1] =3D 0; +} + static inline void rx_desc_set_eof(uint32_t *desc) { desc[1] |=3D DESC_1_RX_EOF; @@ -999,6 +1004,8 @@ static ssize_t gem_receive(NetClientState *nc, const u= int8_t *buf, size_t size) rxbuf_ptr +=3D MIN(bytes_to_copy, rxbufsize); bytes_to_copy -=3D MIN(bytes_to_copy, rxbufsize); =20 + rx_desc_clear_control(s->rx_desc[q]); + /* Update the descriptor. */ if (first_desc) { rx_desc_set_sof(s->rx_desc[q]); --=20 2.20.1 From nobody Thu May 2 02:03:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1588248167; cv=none; d=zohomail.com; s=zohoarc; b=ANOEdIQuT4ryhwxF6ddFEqu6RPJFi2z8zqe0OFSK+VaGPuLczpdFzbSVDdq6J6fGZ0rnj1mrYULuu+pTssifDheOGfpHL2EAtU3k0Sj8Q8WVSOLslY1PnJifIDPCi+hNTdhSBlBovC9p8ZfDUwKbeB/S1NuSnyz1A4gCU3CdlqM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588248167; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gIfmeA/Ol4xu4zVzYnweED3oazdiJztpS/1A6SCoNmw=; b=Pq1+xZmv5rUN+qy7TZcek/SA6UPt9umd6APA9ZV/nAGJy+bybBXNb1Fz47Lr5c+SxuhTnp7SGcoomQ287NLBZ6Yv6cn62LW9IigtvFW3lIY1CvFUD8ppbGBDZo/GxHVQGD7xPgpAp/QPVZ/8Sp8/LII0zcXhQ5U44H/ieyXsNiA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1588248167460904.8007322478229; Thu, 30 Apr 2020 05:02:47 -0700 (PDT) Received: from localhost ([::1]:50032 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU7tu-0006yo-01 for importer@patchew.org; Thu, 30 Apr 2020 08:02:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33886) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU7ji-0003J5-EF for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.90_1) (envelope-from ) id 1jU7jf-0000Qm-5L for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:14 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:46377) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jU7je-0000QJ-Iw for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:10 -0400 Received: by mail-wr1-x435.google.com with SMTP id f13so6474627wrm.13 for ; Thu, 30 Apr 2020 04:52:10 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j22sm491518wre.84.2020.04.30.04.52.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 04:52:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=gIfmeA/Ol4xu4zVzYnweED3oazdiJztpS/1A6SCoNmw=; b=pwpxoUdU9KrJeZAMfp9w1UDThZKbe3aKhT4xV/am7cA6MmfTiYutGe4PxEabrxjVNF +KZy8nzdDlRbvTB19lEynVKxlN2obSAiA3Q9Sz8RphpWRXAl0HZ2zW54noeN6hmu+96g YEEg3M2VhfGAro7YsI50IaghHuS8mGRGwu40QGxRObuuSPIvAvieDIr4kLkaRgT3FBH4 Ti6BLetSVPuvwSIEUuk5z2HRWrg+4y1PoH/Y3FvpmtG5Lfk7RIPppUtlAxaMe2dck3Q+ /POD8x6lz8gq47P0izM5sjMuNCqiArOzPh/M0cowvaR9OBTILFhBluZvDKxtZwYhokGV qgbA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gIfmeA/Ol4xu4zVzYnweED3oazdiJztpS/1A6SCoNmw=; b=i6GYBPJCShPPo2ADSuorKZt9oUdYRgCuhnzEmQb3EVLWB7dbD5MBBLJvXuoG+THRHV 6il9roxeZTSEPNIK4edf78CGtMCTmjcegZLHiCBfUY7qYNaD2mbIJevAZE+DwrCWWTDX erZ+gsZQ9WGRKhEvhYWbUmttY1YwGyyHCPQHrwyhWPrOZU5P8J/GX7Baxp8/Z75BCMZ2 IuOeEcokAcu4aKKlblEnIaybg6mKYYKn2DbgQYYzg4tHHrMzlKvgFJKFUu5ggXdH6Zko xDW/YDKZrfexDGvzDFyvaoPnbGN1zSU4MZMMZ49FWb1Piv12cP5Oxu8XNZdzo70n8zhN P2QA== X-Gm-Message-State: AGi0Pub98dlsATRhfMzhNSHM+Kl2apJKY2/o/kh3xiV1ABVCjdGC5PlK h7BYQWnTcXI5NFDWweSsWCTaJVNZe0aLVA== X-Google-Smtp-Source: APiQypIW4CkgKDONbGNQe5c4kSnks+pNzQyO3DWlUJziPiyTOXVHVdfp6byTEugLREHx9LWNln6Z+Q== X-Received: by 2002:adf:ff82:: with SMTP id j2mr3801718wrr.96.1588247528359; Thu, 30 Apr 2020 04:52:08 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/31] target/arm: Vectorize integer comparison vs zero Date: Thu, 30 Apr 2020 12:51:32 +0100 Message-Id: <20200430115142.13430-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200430115142.13430-1-peter.maydell@linaro.org> References: <20200430115142.13430-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::435 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Richard Henderson These instructions are often used in glibc's string routines. They were the final uses of the 32-bit at a time neon helpers. Signed-off-by: Richard Henderson Message-id: 20200418162808.4680-1-richard.henderson@linaro.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- target/arm/helper.h | 27 ++-- target/arm/translate.h | 5 + target/arm/neon_helper.c | 24 ---- target/arm/translate-a64.c | 64 +++------- target/arm/translate.c | 256 +++++++++++++++++++++++++++++++------ target/arm/vec_helper.c | 25 ++++ 6 files changed, 278 insertions(+), 123 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index f37b8670a55..5817626b20b 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -275,19 +275,6 @@ DEF_HELPER_2(neon_hsub_u16, i32, i32, i32) DEF_HELPER_2(neon_hsub_s32, s32, s32, s32) DEF_HELPER_2(neon_hsub_u32, i32, i32, i32) =20 -DEF_HELPER_2(neon_cgt_u8, i32, i32, i32) -DEF_HELPER_2(neon_cgt_s8, i32, i32, i32) -DEF_HELPER_2(neon_cgt_u16, i32, i32, i32) -DEF_HELPER_2(neon_cgt_s16, i32, i32, i32) -DEF_HELPER_2(neon_cgt_u32, i32, i32, i32) -DEF_HELPER_2(neon_cgt_s32, i32, i32, i32) -DEF_HELPER_2(neon_cge_u8, i32, i32, i32) -DEF_HELPER_2(neon_cge_s8, i32, i32, i32) -DEF_HELPER_2(neon_cge_u16, i32, i32, i32) -DEF_HELPER_2(neon_cge_s16, i32, i32, i32) -DEF_HELPER_2(neon_cge_u32, i32, i32, i32) -DEF_HELPER_2(neon_cge_s32, i32, i32, i32) - DEF_HELPER_2(neon_pmin_u8, i32, i32, i32) DEF_HELPER_2(neon_pmin_s8, i32, i32, i32) DEF_HELPER_2(neon_pmin_u16, i32, i32, i32) @@ -347,9 +334,6 @@ DEF_HELPER_2(neon_mul_u16, i32, i32, i32) DEF_HELPER_2(neon_tst_u8, i32, i32, i32) DEF_HELPER_2(neon_tst_u16, i32, i32, i32) DEF_HELPER_2(neon_tst_u32, i32, i32, i32) -DEF_HELPER_2(neon_ceq_u8, i32, i32, i32) -DEF_HELPER_2(neon_ceq_u16, i32, i32, i32) -DEF_HELPER_2(neon_ceq_u32, i32, i32, i32) =20 DEF_HELPER_1(neon_clz_u8, i32, i32) DEF_HELPER_1(neon_clz_u16, i32, i32) @@ -686,6 +670,17 @@ DEF_HELPER_FLAGS_2(frint64_s, TCG_CALL_NO_RWG, f32, f3= 2, ptr) DEF_HELPER_FLAGS_2(frint32_d, TCG_CALL_NO_RWG, f64, f64, ptr) DEF_HELPER_FLAGS_2(frint64_d, TCG_CALL_NO_RWG, f64, f64, ptr) =20 +DEF_HELPER_FLAGS_3(gvec_ceq0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_ceq0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_clt0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_clt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_cle0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_cle0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_cgt0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_cgt0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_cge0_b, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(gvec_cge0_h, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + DEF_HELPER_FLAGS_4(gvec_sshl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_sshl_h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_4(gvec_ushl_b, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) diff --git a/target/arm/translate.h b/target/arm/translate.h index d9ea0c99cc8..98b319f3f69 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -275,6 +275,11 @@ static inline void gen_swstep_exception(DisasContext *= s, int isv, int ex) uint64_t vfp_expand_imm(int size, uint8_t imm8); =20 /* Vector operations shared between ARM and AArch64. */ +extern const GVecGen2 ceq0_op[4]; +extern const GVecGen2 clt0_op[4]; +extern const GVecGen2 cgt0_op[4]; +extern const GVecGen2 cle0_op[4]; +extern const GVecGen2 cge0_op[4]; extern const GVecGen3 mla_op[4]; extern const GVecGen3 mls_op[4]; extern const GVecGen3 cmtst_op[4]; diff --git a/target/arm/neon_helper.c b/target/arm/neon_helper.c index c7a8438b42a..448be93fa12 100644 --- a/target/arm/neon_helper.c +++ b/target/arm/neon_helper.c @@ -562,24 +562,6 @@ uint32_t HELPER(neon_hsub_u32)(uint32_t src1, uint32_t= src2) return dest; } =20 -#define NEON_FN(dest, src1, src2) dest =3D (src1 > src2) ? ~0 : 0 -NEON_VOP(cgt_s8, neon_s8, 4) -NEON_VOP(cgt_u8, neon_u8, 4) -NEON_VOP(cgt_s16, neon_s16, 2) -NEON_VOP(cgt_u16, neon_u16, 2) -NEON_VOP(cgt_s32, neon_s32, 1) -NEON_VOP(cgt_u32, neon_u32, 1) -#undef NEON_FN - -#define NEON_FN(dest, src1, src2) dest =3D (src1 >=3D src2) ? ~0 : 0 -NEON_VOP(cge_s8, neon_s8, 4) -NEON_VOP(cge_u8, neon_u8, 4) -NEON_VOP(cge_s16, neon_s16, 2) -NEON_VOP(cge_u16, neon_u16, 2) -NEON_VOP(cge_s32, neon_s32, 1) -NEON_VOP(cge_u32, neon_u32, 1) -#undef NEON_FN - #define NEON_FN(dest, src1, src2) dest =3D (src1 < src2) ? src1 : src2 NEON_POP(pmin_s8, neon_s8, 4) NEON_POP(pmin_u8, neon_u8, 4) @@ -1135,12 +1117,6 @@ NEON_VOP(tst_u16, neon_u16, 2) NEON_VOP(tst_u32, neon_u32, 1) #undef NEON_FN =20 -#define NEON_FN(dest, src1, src2) dest =3D (src1 =3D=3D src2) ? -1 : 0 -NEON_VOP(ceq_u8, neon_u8, 4) -NEON_VOP(ceq_u16, neon_u16, 2) -NEON_VOP(ceq_u32, neon_u32, 1) -#undef NEON_FN - /* Count Leading Sign/Zero Bits. */ static inline int do_clz8(uint8_t x) { diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 7580e463674..efb1c4adc4e 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -594,6 +594,14 @@ static void gen_gvec_fn4(DisasContext *s, bool is_q, i= nt rd, int rn, int rm, is_q ? 16 : 8, vec_full_reg_size(s)); } =20 +/* Expand a 2-operand AdvSIMD vector operation using an op descriptor. */ +static void gen_gvec_op2(DisasContext *s, bool is_q, int rd, + int rn, const GVecGen2 *gvec_op) +{ + tcg_gen_gvec_2(vec_full_reg_offset(s, rd), vec_full_reg_offset(s, rn), + is_q ? 16 : 8, vec_full_reg_size(s), gvec_op); +} + /* Expand a 2-operand + immediate AdvSIMD vector operation using * an op descriptor. */ @@ -12366,6 +12374,15 @@ static void disas_simd_two_reg_misc(DisasContext *= s, uint32_t insn) return; } break; + case 0x8: /* CMGT, CMGE */ + gen_gvec_op2(s, is_q, rd, rn, u ? &cge0_op[size] : &cgt0_op[size]); + return; + case 0x9: /* CMEQ, CMLE */ + gen_gvec_op2(s, is_q, rd, rn, u ? &cle0_op[size] : &ceq0_op[size]); + return; + case 0xa: /* CMLT */ + gen_gvec_op2(s, is_q, rd, rn, &clt0_op[size]); + return; case 0xb: if (u) { /* ABS, NEG */ gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_neg, size); @@ -12403,29 +12420,12 @@ static void disas_simd_two_reg_misc(DisasContext = *s, uint32_t insn) for (pass =3D 0; pass < (is_q ? 4 : 2); pass++) { TCGv_i32 tcg_op =3D tcg_temp_new_i32(); TCGv_i32 tcg_res =3D tcg_temp_new_i32(); - TCGCond cond; =20 read_vec_element_i32(s, tcg_op, rn, pass, MO_32); =20 if (size =3D=3D 2) { /* Special cases for 32 bit elements */ switch (opcode) { - case 0xa: /* CMLT */ - /* 32 bit integer comparison against zero, result is - * test ? (2^32 - 1) : 0. We implement via setcond(tes= t) - * and inverting. - */ - cond =3D TCG_COND_LT; - do_cmop: - tcg_gen_setcondi_i32(cond, tcg_res, tcg_op, 0); - tcg_gen_neg_i32(tcg_res, tcg_res); - break; - case 0x8: /* CMGT, CMGE */ - cond =3D u ? TCG_COND_GE : TCG_COND_GT; - goto do_cmop; - case 0x9: /* CMEQ, CMLE */ - cond =3D u ? TCG_COND_LE : TCG_COND_EQ; - goto do_cmop; case 0x4: /* CLS */ if (u) { tcg_gen_clzi_i32(tcg_res, tcg_op, 32); @@ -12522,36 +12522,6 @@ static void disas_simd_two_reg_misc(DisasContext *= s, uint32_t insn) genfn(tcg_res, cpu_env, tcg_op); break; } - case 0x8: /* CMGT, CMGE */ - case 0x9: /* CMEQ, CMLE */ - case 0xa: /* CMLT */ - { - static NeonGenTwoOpFn * const fns[3][2] =3D { - { gen_helper_neon_cgt_s8, gen_helper_neon_cgt_s16 = }, - { gen_helper_neon_cge_s8, gen_helper_neon_cge_s16 = }, - { gen_helper_neon_ceq_u8, gen_helper_neon_ceq_u16 = }, - }; - NeonGenTwoOpFn *genfn; - int comp; - bool reverse; - TCGv_i32 tcg_zero =3D tcg_const_i32(0); - - /* comp =3D index into [CMGT, CMGE, CMEQ, CMLE, CMLT] = */ - comp =3D (opcode - 0x8) * 2 + u; - /* ...but LE, LT are implemented as reverse GE, GT */ - reverse =3D (comp > 2); - if (reverse) { - comp =3D 4 - comp; - } - genfn =3D fns[comp][size]; - if (reverse) { - genfn(tcg_res, tcg_zero, tcg_op); - } else { - genfn(tcg_res, tcg_op, tcg_zero); - } - tcg_temp_free_i32(tcg_zero); - break; - } case 0x4: /* CLS, CLZ */ if (u) { if (size =3D=3D 0) { diff --git a/target/arm/translate.c b/target/arm/translate.c index 9f9f4e19e04..d4ad2028f12 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -3917,6 +3917,205 @@ static int do_v81_helper(DisasContext *s, gen_helpe= r_gvec_3_ptr *fn, return 1; } =20 +static void gen_ceq0_i32(TCGv_i32 d, TCGv_i32 a) +{ + tcg_gen_setcondi_i32(TCG_COND_EQ, d, a, 0); + tcg_gen_neg_i32(d, d); +} + +static void gen_ceq0_i64(TCGv_i64 d, TCGv_i64 a) +{ + tcg_gen_setcondi_i64(TCG_COND_EQ, d, a, 0); + tcg_gen_neg_i64(d, d); +} + +static void gen_ceq0_vec(unsigned vece, TCGv_vec d, TCGv_vec a) +{ + TCGv_vec zero =3D tcg_const_zeros_vec_matching(d); + tcg_gen_cmp_vec(TCG_COND_EQ, vece, d, a, zero); + tcg_temp_free_vec(zero); +} + +static const TCGOpcode vecop_list_cmp[] =3D { + INDEX_op_cmp_vec, 0 +}; + +const GVecGen2 ceq0_op[4] =3D { + { .fno =3D gen_helper_gvec_ceq0_b, + .fniv =3D gen_ceq0_vec, + .opt_opc =3D vecop_list_cmp, + .vece =3D MO_8 }, + { .fno =3D gen_helper_gvec_ceq0_h, + .fniv =3D gen_ceq0_vec, + .opt_opc =3D vecop_list_cmp, + .vece =3D MO_16 }, + { .fni4 =3D gen_ceq0_i32, + .fniv =3D gen_ceq0_vec, + .opt_opc =3D vecop_list_cmp, + .vece =3D MO_32 }, + { .fni8 =3D gen_ceq0_i64, + .fniv =3D gen_ceq0_vec, + .opt_opc =3D vecop_list_cmp, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .vece =3D MO_64 }, +}; + +static void gen_cle0_i32(TCGv_i32 d, TCGv_i32 a) +{ + tcg_gen_setcondi_i32(TCG_COND_LE, d, a, 0); + tcg_gen_neg_i32(d, d); +} + +static void gen_cle0_i64(TCGv_i64 d, TCGv_i64 a) +{ + tcg_gen_setcondi_i64(TCG_COND_LE, d, a, 0); + tcg_gen_neg_i64(d, d); +} + +static void gen_cle0_vec(unsigned vece, TCGv_vec d, TCGv_vec a) +{ + TCGv_vec zero =3D tcg_const_zeros_vec_matching(d); + tcg_gen_cmp_vec(TCG_COND_LE, vece, d, a, zero); + tcg_temp_free_vec(zero); +} + +const GVecGen2 cle0_op[4] =3D { + { .fno =3D gen_helper_gvec_cle0_b, + .fniv =3D gen_cle0_vec, + .opt_opc =3D vecop_list_cmp, + .vece =3D MO_8 }, + { .fno =3D gen_helper_gvec_cle0_h, + .fniv =3D gen_cle0_vec, + .opt_opc =3D vecop_list_cmp, + .vece =3D MO_16 }, + { .fni4 =3D gen_cle0_i32, + .fniv =3D gen_cle0_vec, + .opt_opc =3D vecop_list_cmp, + .vece =3D MO_32 }, + { .fni8 =3D gen_cle0_i64, + .fniv =3D gen_cle0_vec, + .opt_opc =3D vecop_list_cmp, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .vece =3D MO_64 }, +}; + +static void gen_cge0_i32(TCGv_i32 d, TCGv_i32 a) +{ + tcg_gen_setcondi_i32(TCG_COND_GE, d, a, 0); + tcg_gen_neg_i32(d, d); +} + +static void gen_cge0_i64(TCGv_i64 d, TCGv_i64 a) +{ + tcg_gen_setcondi_i64(TCG_COND_GE, d, a, 0); + tcg_gen_neg_i64(d, d); +} + +static void gen_cge0_vec(unsigned vece, TCGv_vec d, TCGv_vec a) +{ + TCGv_vec zero =3D tcg_const_zeros_vec_matching(d); + tcg_gen_cmp_vec(TCG_COND_GE, vece, d, a, zero); + tcg_temp_free_vec(zero); +} + +const GVecGen2 cge0_op[4] =3D { + { .fno =3D gen_helper_gvec_cge0_b, + .fniv =3D gen_cge0_vec, + .opt_opc =3D vecop_list_cmp, + .vece =3D MO_8 }, + { .fno =3D gen_helper_gvec_cge0_h, + .fniv =3D gen_cge0_vec, + .opt_opc =3D vecop_list_cmp, + .vece =3D MO_16 }, + { .fni4 =3D gen_cge0_i32, + .fniv =3D gen_cge0_vec, + .opt_opc =3D vecop_list_cmp, + .vece =3D MO_32 }, + { .fni8 =3D gen_cge0_i64, + .fniv =3D gen_cge0_vec, + .opt_opc =3D vecop_list_cmp, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .vece =3D MO_64 }, +}; + +static void gen_clt0_i32(TCGv_i32 d, TCGv_i32 a) +{ + tcg_gen_setcondi_i32(TCG_COND_LT, d, a, 0); + tcg_gen_neg_i32(d, d); +} + +static void gen_clt0_i64(TCGv_i64 d, TCGv_i64 a) +{ + tcg_gen_setcondi_i64(TCG_COND_LT, d, a, 0); + tcg_gen_neg_i64(d, d); +} + +static void gen_clt0_vec(unsigned vece, TCGv_vec d, TCGv_vec a) +{ + TCGv_vec zero =3D tcg_const_zeros_vec_matching(d); + tcg_gen_cmp_vec(TCG_COND_LT, vece, d, a, zero); + tcg_temp_free_vec(zero); +} + +const GVecGen2 clt0_op[4] =3D { + { .fno =3D gen_helper_gvec_clt0_b, + .fniv =3D gen_clt0_vec, + .opt_opc =3D vecop_list_cmp, + .vece =3D MO_8 }, + { .fno =3D gen_helper_gvec_clt0_h, + .fniv =3D gen_clt0_vec, + .opt_opc =3D vecop_list_cmp, + .vece =3D MO_16 }, + { .fni4 =3D gen_clt0_i32, + .fniv =3D gen_clt0_vec, + .opt_opc =3D vecop_list_cmp, + .vece =3D MO_32 }, + { .fni8 =3D gen_clt0_i64, + .fniv =3D gen_clt0_vec, + .opt_opc =3D vecop_list_cmp, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .vece =3D MO_64 }, +}; + +static void gen_cgt0_i32(TCGv_i32 d, TCGv_i32 a) +{ + tcg_gen_setcondi_i32(TCG_COND_GT, d, a, 0); + tcg_gen_neg_i32(d, d); +} + +static void gen_cgt0_i64(TCGv_i64 d, TCGv_i64 a) +{ + tcg_gen_setcondi_i64(TCG_COND_GT, d, a, 0); + tcg_gen_neg_i64(d, d); +} + +static void gen_cgt0_vec(unsigned vece, TCGv_vec d, TCGv_vec a) +{ + TCGv_vec zero =3D tcg_const_zeros_vec_matching(d); + tcg_gen_cmp_vec(TCG_COND_GT, vece, d, a, zero); + tcg_temp_free_vec(zero); +} + +const GVecGen2 cgt0_op[4] =3D { + { .fno =3D gen_helper_gvec_cgt0_b, + .fniv =3D gen_cgt0_vec, + .opt_opc =3D vecop_list_cmp, + .vece =3D MO_8 }, + { .fno =3D gen_helper_gvec_cgt0_h, + .fniv =3D gen_cgt0_vec, + .opt_opc =3D vecop_list_cmp, + .vece =3D MO_16 }, + { .fni4 =3D gen_cgt0_i32, + .fniv =3D gen_cgt0_vec, + .opt_opc =3D vecop_list_cmp, + .vece =3D MO_32 }, + { .fni8 =3D gen_cgt0_i64, + .fniv =3D gen_cgt0_vec, + .opt_opc =3D vecop_list_cmp, + .prefer_i64 =3D TCG_TARGET_REG_BITS =3D=3D 64, + .vece =3D MO_64 }, +}; + static void gen_ssra8_i64(TCGv_i64 d, TCGv_i64 a, int64_t shift) { tcg_gen_vec_sar8i_i64(a, a, shift); @@ -6481,6 +6680,27 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) tcg_gen_gvec_abs(size, rd_ofs, rm_ofs, vec_size, vec_s= ize); break; =20 + case NEON_2RM_VCEQ0: + tcg_gen_gvec_2(rd_ofs, rm_ofs, vec_size, + vec_size, &ceq0_op[size]); + break; + case NEON_2RM_VCGT0: + tcg_gen_gvec_2(rd_ofs, rm_ofs, vec_size, + vec_size, &cgt0_op[size]); + break; + case NEON_2RM_VCLE0: + tcg_gen_gvec_2(rd_ofs, rm_ofs, vec_size, + vec_size, &cle0_op[size]); + break; + case NEON_2RM_VCGE0: + tcg_gen_gvec_2(rd_ofs, rm_ofs, vec_size, + vec_size, &cge0_op[size]); + break; + case NEON_2RM_VCLT0: + tcg_gen_gvec_2(rd_ofs, rm_ofs, vec_size, + vec_size, &clt0_op[size]); + break; + default: elementwise: for (pass =3D 0; pass < (q ? 4 : 2); pass++) { @@ -6543,42 +6763,6 @@ static int disas_neon_data_insn(DisasContext *s, uin= t32_t insn) default: abort(); } break; - case NEON_2RM_VCGT0: case NEON_2RM_VCLE0: - tmp2 =3D tcg_const_i32(0); - switch(size) { - case 0: gen_helper_neon_cgt_s8(tmp, tmp, tmp2)= ; break; - case 1: gen_helper_neon_cgt_s16(tmp, tmp, tmp2= ); break; - case 2: gen_helper_neon_cgt_s32(tmp, tmp, tmp2= ); break; - default: abort(); - } - tcg_temp_free_i32(tmp2); - if (op =3D=3D NEON_2RM_VCLE0) { - tcg_gen_not_i32(tmp, tmp); - } - break; - case NEON_2RM_VCGE0: case NEON_2RM_VCLT0: - tmp2 =3D tcg_const_i32(0); - switch(size) { - case 0: gen_helper_neon_cge_s8(tmp, tmp, tmp2)= ; break; - case 1: gen_helper_neon_cge_s16(tmp, tmp, tmp2= ); break; - case 2: gen_helper_neon_cge_s32(tmp, tmp, tmp2= ); break; - default: abort(); - } - tcg_temp_free_i32(tmp2); - if (op =3D=3D NEON_2RM_VCLT0) { - tcg_gen_not_i32(tmp, tmp); - } - break; - case NEON_2RM_VCEQ0: - tmp2 =3D tcg_const_i32(0); - switch(size) { - case 0: gen_helper_neon_ceq_u8(tmp, tmp, tmp2)= ; break; - case 1: gen_helper_neon_ceq_u16(tmp, tmp, tmp2= ); break; - case 2: gen_helper_neon_ceq_u32(tmp, tmp, tmp2= ); break; - default: abort(); - } - tcg_temp_free_i32(tmp2); - break; case NEON_2RM_VCGT0_F: { TCGv_ptr fpstatus =3D get_fpstatus_ptr(1); diff --git a/target/arm/vec_helper.c b/target/arm/vec_helper.c index 8017bd88c4c..3d534188a8b 100644 --- a/target/arm/vec_helper.c +++ b/target/arm/vec_helper.c @@ -1257,3 +1257,28 @@ void HELPER(sve2_pmull_h)(void *vd, void *vn, void *= vm, uint32_t desc) } } #endif + +#define DO_CMP0(NAME, TYPE, OP) \ +void HELPER(NAME)(void *vd, void *vn, uint32_t desc) \ +{ \ + intptr_t i, opr_sz =3D simd_oprsz(desc); \ + for (i =3D 0; i < opr_sz; i +=3D sizeof(TYPE)) { \ + TYPE nn =3D *(TYPE *)(vn + i); \ + *(TYPE *)(vd + i) =3D -(nn OP 0); \ + } \ + clear_tail(vd, opr_sz, simd_maxsz(desc)); \ +} + +DO_CMP0(gvec_ceq0_b, int8_t, =3D=3D) +DO_CMP0(gvec_clt0_b, int8_t, <) +DO_CMP0(gvec_cle0_b, int8_t, <=3D) +DO_CMP0(gvec_cgt0_b, int8_t, >) +DO_CMP0(gvec_cge0_b, int8_t, >=3D) + +DO_CMP0(gvec_ceq0_h, int16_t, =3D=3D) +DO_CMP0(gvec_clt0_h, int16_t, <) +DO_CMP0(gvec_cle0_h, int16_t, <=3D) +DO_CMP0(gvec_cgt0_h, int16_t, >) +DO_CMP0(gvec_cge0_h, int16_t, >=3D) + +#undef DO_CMP0 --=20 2.20.1 From nobody Thu May 2 02:03:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1588248367; cv=none; d=zohomail.com; s=zohoarc; b=CYOgQco+Hu1KAjh9vo3iD5ZzaaCGUHOcYpmuImFXeGBshgNa0q9d+B3Gy/2tGY4wylVli5NXUuXvM2/GH7nvFlPvcf9nsD5egHZWmCOL7s8I3CWtEfMz0qAlX++2Ah/LzwrVpbqLOWO4I7bV+9CBmTdkdcqHaO+78TA5d85odgg= ARC-Message-Signature: i=1; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j22sm491518wre.84.2020.04.30.04.52.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 04:52:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ldO2tE9PLYd0GigcvjlBiYXaMzZxcyyWw/7hDoBADyU=; b=UcX1g7Rt05VLqU4ftMVwz9UUz3Oa382gumesSBYqw8HiIBBzVghDmDtNaFIw+JE+m8 nFg5Nhgrs/jztpuydoSxZ7jICyip9n0OE14uqLobP1txm20phWl7uUT3GWdeIEZdBq8l 3PYQOV5BxMvrxg/dSK3zYGRz1fvQRzrIep5WR4vkYZc+1I31UzF73oC8X0qbsXAc0O3G CNSFal+72paOIYjwLrNmA0hpCVQhjL8ftsDMRmKAZMqJR8+wdZ0vfYBYg1ZkHQlfM5iE 3rAQ+ZRTcfuO2odwdTtE6TIA7eDrL8e2i7nF2ER4B/4bg9CrOyLNkO4zl2gl6bsaD3ub Xx3A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ldO2tE9PLYd0GigcvjlBiYXaMzZxcyyWw/7hDoBADyU=; b=l45Kw7tB5bRDcdcRJ5ZM0MQj3TvZ4igkq2n7aP4BWkDgP4e3WqLVsH0uUfN2uDNIdn 2ea1ZJR4TwyUbnBBTtVsMB8YtXMF4u4oUOUnvHlroiC2+EsQM9Y3hC4NMdvNl/noEh2L z6fFcBWCggs+RNXqy6NFTYCK63UsWcvMi3F0H7C/+mtFUTc49fpA535/i4qHOqbJCzro qJwDCUKGlPpRwXTim2iO2q0KFqYFvfBI7bAxyrR95nV180Mwqgx8RZLLQXxzSAvjtYBw uGjbJ1MdQghQDWQF3Wrwhk1z6RTOejq5ZGYcbi5xjassqIubILWDgDrwwuVQQFvXnZIv mvAg== X-Gm-Message-State: AGi0PuYri1rKpjNaPjKIJ1Psp7+zDHBmrFLDe+mf3fmuj61VJa2SpGyZ QA7/2ukNfWjxs9T6aaZz6KSnZloW0Q1HNw== X-Google-Smtp-Source: APiQypItvsTYYdro7NGrJL4ADdQn2ej2D0OLF689DaApILcOjeCepuyfanCgPVt0LL722Or8cUpPjw== X-Received: by 2002:adf:e944:: with SMTP id m4mr3452365wrn.366.1588247529322; Thu, 30 Apr 2020 04:52:09 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/31] hw/arm/virt: dt: move creation of /secure-chosen to create_fdt() Date: Thu, 30 Apr 2020 12:51:33 +0100 Message-Id: <20200430115142.13430-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200430115142.13430-1-peter.maydell@linaro.org> References: <20200430115142.13430-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::42b X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Jerome Forissier The /secure-chosen node is currently used only by create_uart(), but this will change. Therefore move the creation of this node to create_fdt(). Signed-off-by: Jerome Forissier Message-id: 20200420121807.8204-2-jerome@forissier.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/virt.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index cca53162563..0d92674f32b 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -234,6 +234,10 @@ static void create_fdt(VirtMachineState *vms) /* /chosen must exist for load_dtb to fill in necessary properties lat= er */ qemu_fdt_add_subnode(fdt, "/chosen"); =20 + if (vms->secure) { + qemu_fdt_add_subnode(fdt, "/secure-chosen"); + } + /* Clock node, for the benefit of the UART. The kernel device tree * binding documentation claims the PL011 node clock properties are * optional but in practice if you omit them the kernel refuses to @@ -761,7 +765,6 @@ static void create_uart(const VirtMachineState *vms, in= t uart, qemu_fdt_setprop_string(vms->fdt, nodename, "status", "disabled"); qemu_fdt_setprop_string(vms->fdt, nodename, "secure-status", "okay= "); =20 - qemu_fdt_add_subnode(vms->fdt, "/secure-chosen"); qemu_fdt_setprop_string(vms->fdt, "/secure-chosen", "stdout-path", nodename); } --=20 2.20.1 From nobody Thu May 2 02:03:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1588247923; cv=none; d=zohomail.com; s=zohoarc; b=f8xCHYxJcH9+WBUF8MZqsKTuMUcEHaWUryIqEC78aTDJ/5jOfoBlC+ipQpGuCy5I3oHi9U6jRrMqZHM7lNqavZuP8eM0N8YP7PXFwVjVb7fjofIOd9p+sOKVPUj3JdFP2GKNt3aMG+ApGOLFxkaP4t1NLKZkIe2KHN46pPtEJpc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588247923; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DnVZE8yCIv33a+1icgwUYG6BXiHGdO/aR7fwaOKWJV4=; b=iBPeY8agG7ZJdSVRFoocTQjb2pq6Ba13ZbY7fUf/U4RaH+3xTnZ3L7RbIrL1lPiCmh6cOPdY5vThMt2t7gBbuOlIl54i/qqjdB1xlCGRz+at2V5KjnIeP3DHqLvLIg3xeLjLwm7/Qe/Z8xhzkd5KspDB2AvAKHLp+TyLP6a44jg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1588247923366479.3735096472217; Thu, 30 Apr 2020 04:58:43 -0700 (PDT) Received: from localhost ([::1]:33764 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU7px-0007sm-VH for importer@patchew.org; Thu, 30 Apr 2020 07:58:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33902) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU7jk-0003NV-21 for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.90_1) (envelope-from ) id 1jU7jg-0000RL-Ex for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:15 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:40088) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jU7jf-0000Qk-Vh for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:12 -0400 Received: by mail-wm1-x32e.google.com with SMTP id u16so1542589wmc.5 for ; Thu, 30 Apr 2020 04:52:11 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j22sm491518wre.84.2020.04.30.04.52.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 04:52:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=DnVZE8yCIv33a+1icgwUYG6BXiHGdO/aR7fwaOKWJV4=; b=gNsxh2GjbHn4Fk4CkuG/Pays6Bud3qziAXhVj+RnFuuRxKUtHcerToyd4GwwQTekpU rF7FLE5M+thgXhPaLxjCuvQ0P6aOzcKg4L8MXY7fF32spJcsRR996+Qdftrapzw7IEiU 9fdZYQpURHm+LEq50p1OaMBiLOFDAOUxPv5O4aPHgickPJ8yW7Kf6UbVCw0aNQv6QK+z FcvJDfSeql9b0Ia58VelJ9GtLVcSWg0uGTXgjhnmVJpnwKRvdZaxu0GBfE3eUUafAiXz OEkIeZ7nBa9vJbvta9hYSZqFHmG4VnI84muyFN2hm0vM/mxF3mn3w680+pnOjOINx2td qndQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DnVZE8yCIv33a+1icgwUYG6BXiHGdO/aR7fwaOKWJV4=; b=g8INtj4F4XMJ1l1Ia/Gz0Bnd4ufnkd06mLZnZ2HnMrLBZcRjC19O9Ktgc91IIugJlk Wzm267VOmBV+3OPtThxTsNy06UcYFJNcLYnTLaXe/Hpme6DPc7funesY+K2iCeBhng5l nG7n+Mf56LTGvkRNvZYFfuzfzVfZ7BkUr0bNSuLjpbGjpzS3AK2Oe+RAtVpAT7CFspPm DqJldTrkXajj7LDbKN+ov64Z+JWKvc89yIAQ7+vGKbTsooJmeNJo/9Ta/UVMlPpWutfI wuKMd93ZU7qW8COwywyr9RKei5xyqHHCE/xU6gOeasgFxIvUmq1o+idtHS4hlRuorCwC jNLQ== X-Gm-Message-State: AGi0PuaXY9JoDf4R9dk6OfGOB1P0KMbGnPIh40iBBg/04zJcHKBE70v+ /cd5wd6nT4pcx++NHKEV8Zb1w/GKBzf13A== X-Google-Smtp-Source: APiQypKke2OcmTsrW5cDqbXyBo9mUH7a/KTfYn7FuBdMpOw5gn5uQs7Ij4n5WVXQLSugSSN4fzmt/g== X-Received: by 2002:a1c:2dc7:: with SMTP id t190mr2450037wmt.129.1588247530299; Thu, 30 Apr 2020 04:52:10 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/31] hw/arm/virt: dt: add kaslr-seed property Date: Thu, 30 Apr 2020 12:51:34 +0100 Message-Id: <20200430115142.13430-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200430115142.13430-1-peter.maydell@linaro.org> References: <20200430115142.13430-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::32e X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: Jerome Forissier Generate random seeds to be used by the non-secure and/or secure OSes for ASLR. The seeds are 64-bit random values exported via the DT properties /chosen/kaslr-seed [1] and /secure-chosen/kaslr-seed, the latter being used by OP-TEE [2]. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/comm= it/?id=3De5bc0c37c97e1 [2] https://github.com/OP-TEE/optee_os/commit/ef262691fe0e Signed-off-by: Jerome Forissier Message-id: 20200420121807.8204-3-jerome@forissier.org Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/virt.c | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 0d92674f32b..626822554d5 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -77,6 +77,7 @@ #include "hw/acpi/generic_event_device.h" #include "hw/virtio/virtio-iommu.h" #include "hw/char/pl011.h" +#include "qemu/guest-random.h" =20 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ @@ -213,6 +214,18 @@ static bool cpu_type_valid(const char *cpu) return false; } =20 +static void create_kaslr_seed(VirtMachineState *vms, const char *node) +{ + Error *err =3D NULL; + uint64_t seed; + + if (qemu_guest_getrandom(&seed, sizeof(seed), &err)) { + error_free(err); + return; + } + qemu_fdt_setprop_u64(vms->fdt, node, "kaslr-seed", seed); +} + static void create_fdt(VirtMachineState *vms) { MachineState *ms =3D MACHINE(vms); @@ -233,9 +246,11 @@ static void create_fdt(VirtMachineState *vms) =20 /* /chosen must exist for load_dtb to fill in necessary properties lat= er */ qemu_fdt_add_subnode(fdt, "/chosen"); + create_kaslr_seed(vms, "/chosen"); =20 if (vms->secure) { qemu_fdt_add_subnode(fdt, "/secure-chosen"); + create_kaslr_seed(vms, "/secure-chosen"); } =20 /* Clock node, for the benefit of the UART. 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j22sm491518wre.84.2020.04.30.04.52.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 04:52:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=6V9ucxOOBLKRqrUEKQVPivd5c5ZGx+aM8Gyykmmx1TE=; b=dNlLLcRP/mtF7S5cyXVnI4YAf0kKkiuNP0G/aSll3+bs5npRAHE1yJMjyH5EAVZo2k ezED8ODNbIpnQ+NCvyZFI1NRc0mMMnbfwO/yCKYOJfNX3UA7NJ0KwEbygqXAd3iltH52 YeqZf72SOJ5OBtBYKLDHpdnZkay2XLFkIrkJeQAlQuJlSbnOipIPweYQUmP6nTQ1Y7tA pLv/Uc4LFsPiHZUQm8b2ITTrsBOaz0wVxvyKzRZqqleR2aH75kRxIFJXtx5PqgbgGpjY m1yCAp3VWdQkETPFf9e9Miutm+N/laoOSDYmKTQemT6Jn/zLDse69cuh70dxEGle0W3z 5fOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6V9ucxOOBLKRqrUEKQVPivd5c5ZGx+aM8Gyykmmx1TE=; b=KKWtCubp6vG7dkJo2p+GKGyWkqvOdC4JWjLflO7sPSa4z+RixkTFA1OfT+Fb/whrpW PjjyhpjEuA/1bYKNtlPpTlOFA+hXRfLLEcqzoqvCMG/FHzLtRkGGNZwdQVyhcQa9wW1g D0KBpSThjTFS214wIIm1gUOebot3PRVJMohyH4vTuFLmvVV9jX87tMqv4KyeeYr8nTXh mRaCcUPz1BWLKxIINalP15GFyylWuGGmfkRlcMYlR6vpPUoNZ/gQFi00ZUPyNqCn1kA5 MFkr1JbgYPBP1vh6osZLpEW8m8WuDTtZCZVUz8z8MXGMKbaY4TuEhpbgTwD6qWxMUOPc T5ng== X-Gm-Message-State: AGi0PuZ58ScI6zS4hYkTzrPIL6TvtF+0X/1UxTwV2Y4cgeFPaKOTEq/A lY7ie4cJefSPj4u8xxkNUT0c+c5f8VEduA== X-Google-Smtp-Source: APiQypLIB2A3x7BGl3ZHmFwQ2a7NcQozUBcTEJg1JMDNsO0gtuOqFBZ5JnZl857PZ10DE6sWyFhDRA== X-Received: by 2002:adf:d088:: with SMTP id y8mr580739wrh.23.1588247531305; Thu, 30 Apr 2020 04:52:11 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/31] target/arm: Restrict the Address Translate write operation to TCG accel Date: Thu, 30 Apr 2020 12:51:35 +0100 Message-Id: <20200430115142.13430-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200430115142.13430-1-peter.maydell@linaro.org> References: <20200430115142.13430-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::436 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Philippe Mathieu-Daud=C3=A9 Under KVM these registers are written by the hardware. Restrict the writefn handlers to TCG to avoid when building without TCG: LINK aarch64-softmmu/qemu-system-aarch64 target/arm/helper.o: In function `do_ats_write': target/arm/helper.c:3524: undefined reference to `raise_exception' Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20200423073358.27155-2-philmd@redhat.com Signed-off-by: Peter Maydell --- target/arm/helper.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7e9ea5d20fa..dfefb9b3d9b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3442,6 +3442,7 @@ static CPAccessResult ats_access(CPUARMState *env, co= nst ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 +#ifdef CONFIG_TCG static uint64_t do_ats_write(CPUARMState *env, uint64_t value, MMUAccessType access_type, ARMMMUIdx mmu_idx) { @@ -3602,9 +3603,11 @@ static uint64_t do_ats_write(CPUARMState *env, uint6= 4_t value, } return par64; } +#endif /* CONFIG_TCG */ =20 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) { +#ifdef CONFIG_TCG MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA= _LOAD; uint64_t par64; ARMMMUIdx mmu_idx; @@ -3664,17 +3667,26 @@ static void ats_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) par64 =3D do_ats_write(env, value, access_type, mmu_idx); =20 A32_BANKED_CURRENT_REG_SET(env, par, par64); +#else + /* Handled by hardware accelerator. */ + g_assert_not_reached(); +#endif /* CONFIG_TCG */ } =20 static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { +#ifdef CONFIG_TCG MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA= _LOAD; uint64_t par64; =20 par64 =3D do_ats_write(env, value, access_type, ARMMMUIdx_E2); =20 A32_BANKED_CURRENT_REG_SET(env, par, par64); +#else + /* Handled by hardware accelerator. */ + g_assert_not_reached(); +#endif /* CONFIG_TCG */ } =20 static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo = *ri, @@ -3689,6 +3701,7 @@ static CPAccessResult at_s1e2_access(CPUARMState *env= , const ARMCPRegInfo *ri, static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { +#ifdef CONFIG_TCG MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA= _LOAD; ARMMMUIdx mmu_idx; int secure =3D arm_is_secure_below_el3(env); @@ -3728,6 +3741,10 @@ static void ats_write64(CPUARMState *env, const ARMC= PRegInfo *ri, } =20 env->cp15.par_el[1] =3D do_ats_write(env, value, access_type, mmu_idx); +#else + /* Handled by hardware accelerator. */ + g_assert_not_reached(); +#endif /* CONFIG_TCG */ } #endif =20 --=20 2.20.1 From nobody Thu May 2 02:03:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1588248472; cv=none; d=zohomail.com; s=zohoarc; b=RqSq+GkxLMc5Xa0n8ffLUGvrTYPsyR7EFq7s9Fzp46UliGrZpxRHMo3Pzc4pKOAzoesncroNLLZK80yGigDkBqZRTPQY5qjTRmweddUE/PnGHf/pd9Z1Nvkjtu0E+C6Gubrg5sNC1FHHGLjxwb7Qr5YwjbZ96KswJV6kNa5WHVU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588248472; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pPIQv9n40IDAcbCAwAaYgpIvcVu9gJFTvPCQZjCwLHE=; b=fo+701hdo2q3w7DERdfmEOYUZ4o1oK1nfq2YvXcXqpbzKnOwHiPB1UZZ9mNsc0oxjn9jpxXdJYqlzSyelZ1f25LCZurB14EXhibMuP2u911x4kvUC1zul1CmSRa1P5FeDUFL0omjgTcv54iz4+fkazE8oMfJortD71mWZkAoP3I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1588248472142833.582212874956; Thu, 30 Apr 2020 05:07:52 -0700 (PDT) Received: from localhost ([::1]:41090 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU7yo-0007dD-Tw for importer@patchew.org; Thu, 30 Apr 2020 08:07:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33912) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU7jk-0003Ow-Nu for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.90_1) (envelope-from ) id 1jU7ji-0000Rt-Ie for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:16 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:44998) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jU7ji-0000RY-0l for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:14 -0400 Received: by mail-wr1-x435.google.com with SMTP id d17so6484964wrg.11 for ; Thu, 30 Apr 2020 04:52:13 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j22sm491518wre.84.2020.04.30.04.52.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 04:52:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=pPIQv9n40IDAcbCAwAaYgpIvcVu9gJFTvPCQZjCwLHE=; b=kMO4+tRCX2FfHRngSazbYawNYtRKNqa3v3pg8RwZyda2QpkQB97DAmelmA36n8fokw FC29oQbcrEkda2i/lu1jUrz5MAqxK0UpppwXK5T/a6mliZw06wPLYBp2L0k9Mv30lf0C 0qTYVIT1E3jns/xHOHOj4HPZGMqi2MaKYg/4mBfKQzk1956pzL2MkB+I++jCPqKKXKnz arzw6mQKQoC4z7UjxoxBIScqhLyY8XlfTANT+ZkLprO+PO0a45UVd83UH02sK9YNkJcc Rro21S7dXcl7qMOe6c1i7ZWkWSYJSlPRoli1EtA9K8CPLGE3fM1tQpLwZpiRxsXbCRfv ig7Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pPIQv9n40IDAcbCAwAaYgpIvcVu9gJFTvPCQZjCwLHE=; b=Zr6X7286Q/rTp9hlJXGn2WnqFQBVuZbPKe7M8uEByq0PsHe9C3OhqL0Zs5yhaCNc57 X+A0R2xuSwCOZ3dB/9qp8LELF2P+9RHRh9QWz7eWrXiuAiwlSg3ioHksfFNd2Sij48+B /WCDtM62hCvbsF9QKiZFd3R33UbgUxVk77WsaEs9PWdkBy5mE860xgpReS/FWUvSkRM4 haIeHzIQjwHqihbBBkfzIWAp5VF5Fh1KPv6ZxhyuIRoYBwNkp9Ss836cfseuGUYSNa3W ywDDDrizrBUhenH4U/xW0vjYwCYEtJ/wt5jDpWD4QgVRiU2KqS6v1NICYT1aSI1i+hVQ GMRw== X-Gm-Message-State: AGi0PuZh9ol3szb+itWwQQZfQsSuDdc6/kYzHkv61SwiBOUf01tuKzGG cTUKFcBTPt4LqDoaZQyHYCiRR8XDvlKLGQ== X-Google-Smtp-Source: APiQypKd4cJlafn55Qk+POaK96pQ5lyCcmUTTjbYTXx/HrrOkOn314wGFgL4YIyg13Qz0Jv3wjadKw== X-Received: by 2002:a5d:5147:: with SMTP id u7mr3392889wrt.290.1588247532356; Thu, 30 Apr 2020 04:52:12 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/31] target/arm: Make cpu_register() available for other files Date: Thu, 30 Apr 2020 12:51:36 +0100 Message-Id: <20200430115142.13430-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200430115142.13430-1-peter.maydell@linaro.org> References: <20200430115142.13430-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::435 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Thomas Huth Make cpu_register() (renamed to arm_cpu_register()) available from internals.h so we can register CPUs also from other files in the future. Signed-off-by: Thomas Huth Reviewed-by: Richard Henderson Reviewed-by: Eric Auger Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20200423073358.27155-3-philmd@redhat.com Message-ID: <20190921150420.30743-2-thuth@redhat.com> [PMD: Only take cpu_register() from Thomas's patch] Signed-off-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Peter Maydell --- target/arm/cpu-qom.h | 9 ++++++++- target/arm/cpu.c | 10 ++-------- target/arm/cpu64.c | 8 +------- 3 files changed, 11 insertions(+), 16 deletions(-) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index d95568bf052..56395b87f62 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -35,7 +35,14 @@ struct arm_boot_info; =20 #define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU =20 -typedef struct ARMCPUInfo ARMCPUInfo; +typedef struct ARMCPUInfo { + const char *name; + void (*initfn)(Object *obj); + void (*class_init)(ObjectClass *oc, void *data); +} ARMCPUInfo; + +void arm_cpu_register(const ARMCPUInfo *info); +void aarch64_cpu_register(const ARMCPUInfo *info); =20 /** * ARMCPUClass: diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a79f233b170..47e35400da2 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2693,12 +2693,6 @@ static void arm_max_initfn(Object *obj) =20 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ =20 -struct ARMCPUInfo { - const char *name; - void (*initfn)(Object *obj); - void (*class_init)(ObjectClass *oc, void *data); -}; - static const ARMCPUInfo arm_cpus[] =3D { #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) { .name =3D "arm926", .initfn =3D arm926_initfn }, @@ -2864,7 +2858,7 @@ static void cpu_register_class_init(ObjectClass *oc, = void *data) acc->info =3D data; } =20 -static void cpu_register(const ARMCPUInfo *info) +void arm_cpu_register(const ARMCPUInfo *info) { TypeInfo type_info =3D { .parent =3D TYPE_ARM_CPU, @@ -2905,7 +2899,7 @@ static void arm_cpu_register_types(void) type_register_static(&idau_interface_type_info); =20 while (info->name) { - cpu_register(info); + arm_cpu_register(info); info++; } =20 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 95d0c8c101a..74afc28d537 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -737,12 +737,6 @@ static void aarch64_max_initfn(Object *obj) cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal); } =20 -struct ARMCPUInfo { - const char *name; - void (*initfn)(Object *obj); - void (*class_init)(ObjectClass *oc, void *data); -}; - static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a57", .initfn =3D aarch64_a57_initfn }, { .name =3D "cortex-a53", .initfn =3D aarch64_a53_initfn }, @@ -825,7 +819,7 @@ static void cpu_register_class_init(ObjectClass *oc, vo= id *data) acc->info =3D data; } =20 -static void aarch64_cpu_register(const ARMCPUInfo *info) +void aarch64_cpu_register(const ARMCPUInfo *info) { TypeInfo type_info =3D { .parent =3D TYPE_AARCH64_CPU, --=20 2.20.1 From nobody Thu May 2 02:03:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j22sm491518wre.84.2020.04.30.04.52.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 04:52:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=RCca2W4lwjdzEpAu/gQsnddTCCmaj3klMrOHk+9dWSk=; b=aeEeQAr8VBAx9n24ThCp5ebWUh4vi2a5sCZlQwsvRzgpleLR9stUw1UuMFxKT/CBRl 7+gTnn3P50N+v2zzi9BQAAQprNSFOaH42XF1K7YeqIoKcvC0GTXFbFxKnDNNk4K/MPX6 seiYTp8qmqtsGiF1pHgPWhU+gCrWkXAAPqLDDAOdNBLkOH5M70AKPRF3Mwy6qO9rVthB 2iTawhlHanvS5U1PlnGRuLfuAD+tGiGXxR2ubxCbAqDVbbGWseZhCuyNDikeqpwM6463 0RVjnDERzK5G0htZHxH2U+tin9j00VfRhUtbyohuR3IPFMCy05xpK61fcGyfIxf34ry4 iRGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RCca2W4lwjdzEpAu/gQsnddTCCmaj3klMrOHk+9dWSk=; b=otnpwP7I1Q/uVXomafBQaEk4aLWiIXmOC89Z3AdaZZmtcI7GzF5lU2wgnduv1W3yhi nHkzqy7upJxLiMsHKOBDiDnIDgd4UDBBxEUuDnYFPYWLQQI9ELfgpPVa8CAyZYRy+LCo wZZBKkDwJeARw9IoImrDoIQoA0knLXJyYkPcFpQGFBMk/3eV3a4FIMBR18XQjc8mmhYO JLaLRytj1IHqwnTd10onNa6RXi38d1jvFHNdrOn9Dx8QXa1/Y/0k3GHdR0P2ftw1eJtk 7dYKuYMd/sFj2CgkFC0S7cGCMFnugKDP1KVn7JtY/hvQshLBtXuWxoVRtjtsuCVWvPes eCPg== X-Gm-Message-State: AGi0PubeDwOCeMh3sp5lOQskaF0WYb8vpXkP5R+QyebrMDxS6fdCz5xg VBzZ3vSuTNIkHs183/gGhRvKhdyplvIO5g== X-Google-Smtp-Source: APiQypJZbKGjMN5I0Qx70Gbvr2IR3EDbOQI3dTRk09lPpxdTzEYKpD+Bb2vRKx81y9ZHi4fEV5AwnA== X-Received: by 2002:adf:f0ca:: with SMTP id x10mr2258511wro.112.1588247533476; Thu, 30 Apr 2020 04:52:13 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/31] target/arm/cpu: Use ARRAY_SIZE() to iterate over ARMCPUInfo[] Date: Thu, 30 Apr 2020 12:51:37 +0100 Message-Id: <20200430115142.13430-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200430115142.13430-1-peter.maydell@linaro.org> References: <20200430115142.13430-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::436 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Philippe Mathieu-Daud=C3=A9 Suggested-by: Richard Henderson Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20200423073358.27155-4-philmd@redhat.com Signed-off-by: Peter Maydell --- target/arm/cpu.c | 8 +++----- target/arm/cpu64.c | 8 +++----- 2 files changed, 6 insertions(+), 10 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 47e35400da2..30e961f7754 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2745,7 +2745,6 @@ static const ARMCPUInfo arm_cpus[] =3D { { .name =3D "any", .initfn =3D arm_max_initfn }, #endif #endif - { .name =3D NULL } }; =20 static Property arm_cpu_properties[] =3D { @@ -2893,14 +2892,13 @@ static const TypeInfo idau_interface_type_info =3D { =20 static void arm_cpu_register_types(void) { - const ARMCPUInfo *info =3D arm_cpus; + size_t i; =20 type_register_static(&arm_cpu_type_info); type_register_static(&idau_interface_type_info); =20 - while (info->name) { - arm_cpu_register(info); - info++; + for (i =3D 0; i < ARRAY_SIZE(arm_cpus); ++i) { + arm_cpu_register(&arm_cpus[i]); } =20 #ifdef CONFIG_KVM diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 74afc28d537..b8177f59f5a 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -742,7 +742,6 @@ static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a53", .initfn =3D aarch64_a53_initfn }, { .name =3D "cortex-a72", .initfn =3D aarch64_a72_initfn }, { .name =3D "max", .initfn =3D aarch64_max_initfn }, - { .name =3D NULL } }; =20 static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) @@ -848,13 +847,12 @@ static const TypeInfo aarch64_cpu_type_info =3D { =20 static void aarch64_cpu_register_types(void) { - const ARMCPUInfo *info =3D aarch64_cpus; + size_t i; =20 type_register_static(&aarch64_cpu_type_info); =20 - while (info->name) { - aarch64_cpu_register(info); - info++; + for (i =3D 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { + aarch64_cpu_register(&aarch64_cpus[i]); } } =20 --=20 2.20.1 From nobody Thu May 2 02:03:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1588248232; cv=none; d=zohomail.com; s=zohoarc; b=AZ+YIgIMVj0PcvvOifK4FabO9mVNQGhPr7GU14cbds/7VLHYFdFdhVi5Nogukua+IwOWftQnvyhIvtQTy/Div6KaB4C3ED3vKQqif3IM9g2xg87c0yK+FLg5S73i2AtMvH0TwOa5LJHkY5kyCX0+dBO2PEB2TyNgtEDuvBD/ZAw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588248232; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wt7yqTcgLmF8JzV1SCxT47djUoUbTeewI0QoooN4y4U=; b=mFUTzaKj1HcQnwfcUQQn8OTNs0UkFW7W8a+QzAmtgdSpKwcFkhW6I/LcVkIEoLjA4LKtLWD0c9mVPj7GqiVcfr7UImDjuP+kVZRq2a1VSh5LoiGoDaW/4vwUeG2y8fqx4FmASJ6SmTgfz5tpLmOAa7FXaMlBoYJw2GFxly3+AUQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1588248232758239.22134161792872; Thu, 30 Apr 2020 05:03:52 -0700 (PDT) Received: from localhost ([::1]:53882 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU7uw-0000SK-Vp for importer@patchew.org; Thu, 30 Apr 2020 08:03:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33936) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU7jn-0003VM-A6 for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:21 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.90_1) (envelope-from ) id 1jU7jk-0000Sf-J5 for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:19 -0400 Received: from mail-wm1-x32d.google.com ([2a00:1450:4864:20::32d]:50837) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jU7jk-0000S8-5f for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:16 -0400 Received: by mail-wm1-x32d.google.com with SMTP id x25so1516707wmc.0 for ; Thu, 30 Apr 2020 04:52:15 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j22sm491518wre.84.2020.04.30.04.52.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 04:52:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=wt7yqTcgLmF8JzV1SCxT47djUoUbTeewI0QoooN4y4U=; b=t629mrB1Igtt1yuc0y8PjYGlnrtr4RJ9rbE2WScZ/U+cxmHplriamrEgxvhfG7WfTr NyqCdhR2oIHlm57iyNVTr/akpfpP85P4vAw+Vas02I0UyfS2Dg+Ul47ZO6IgRr19hKMW SOBk8tbRJal+IaZRieGrVvLZwD5hgNLQ4K2DFSm3lwCiuGCJNHxCtNHnCNrdWntrU+4B HfnGgcvml8dAKNlzNuR9hWuRCoSd0lm5wWzmOGG7MgOExC7X2vfPM7hRqpNmyJA1NcS2 uLVNCvHpDsoxAcqghWlF3CAc0FQnhKNA6LtYQWGzdoL7I19+FpyvSdBGJT/ndW3bKbGP 1Dbw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wt7yqTcgLmF8JzV1SCxT47djUoUbTeewI0QoooN4y4U=; b=NNZGl0dBafph7qygJuuP3apslt1BSNTMQWOeP60x00erRj7fHBjOIbyXGcfyzEM5eA hKNT3Qcv2s1POSrrGX/AmGo1k6CiB7k7f7MMX6f49FNHP0a8oKUHRF4CYFUy37FFOkwz ZhmqxVsLLBqMHDfRcsQZy6jiBeKaOS998leEf9A2wI/Ffwf7zxfFJLIK0xscYbw69/RV bxTviMgS9wxVAu8B6o5iZunqxEJh562AS80avWlEQ5sUvCRybyqAELmpwWuB6u4JP3mX 3ZYP570fSBvn4LyGcpoNPUlkZLdtn8RW+W3DlQjrfENWxVcqOAse5NdvAMfFbjVR7JPP S4iw== X-Gm-Message-State: AGi0PuZFXuMX2CfHHcW2XeXAlPaEHHKBDxZjRzmuszpPkY0M8GCPqNtJ +GABN42Qau59SzijbfyOvA2CY+zdCsXghg== X-Google-Smtp-Source: APiQypJZiMd7WesfSIN4WOwclYf2u2Zczw5Whe5qzKlk/C9r/OmQW2AfeqfZ44bgGRjjkHYYNSKSSA== X-Received: by 2002:a1c:4304:: with SMTP id q4mr2757248wma.152.1588247534493; Thu, 30 Apr 2020 04:52:14 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/31] target/arm/cpu: Update coding style to make checkpatch.pl happy Date: Thu, 30 Apr 2020 12:51:38 +0100 Message-Id: <20200430115142.13430-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200430115142.13430-1-peter.maydell@linaro.org> References: <20200430115142.13430-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32d; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32d.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::32d X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: Philippe Mathieu-Daud=C3=A9 We will move this code in the next commit. Clean it up first to avoid checkpatch.pl errors. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-id: 20200423073358.27155-5-philmd@redhat.com Signed-off-by: Peter Maydell --- target/arm/cpu.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 30e961f7754..a1e38b38ba1 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -582,7 +582,8 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, in= t interrupt_request) CPUARMState *env =3D &cpu->env; bool ret =3D false; =20 - /* ARMv7-M interrupt masking works differently than -A or -R. + /* + * ARMv7-M interrupt masking works differently than -A or -R. * There is no FIQ/IRQ distinction. Instead of I and F bits * masking FIQ and IRQ interrupts, an exception is taken only * if it is higher priority than the current execution priority @@ -1912,7 +1913,8 @@ static void arm1026_initfn(Object *obj) static void arm1136_r2_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); - /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an + /* + * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an * older core than plain "arm1136". In particular this does not * have the v6K features. * These ID register values are correct for 1136 but may be wrong @@ -2698,7 +2700,8 @@ static const ARMCPUInfo arm_cpus[] =3D { { .name =3D "arm926", .initfn =3D arm926_initfn }, { .name =3D "arm946", .initfn =3D arm946_initfn }, { .name =3D "arm1026", .initfn =3D arm1026_initfn }, - /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an + /* + * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an * older core than plain "arm1136". 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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id j22sm491518wre.84.2020.04.30.04.52.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 04:52:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=8hi1p3eL3t21N4txt/xDnw2kNSKZMQWnLiLJ53KEUd4=; b=tbsVtx2/lE3Z8HBRsS3iPBc/MmKHtGrmQsX4gVkMiBDkAKCUlDfzV0hX+/A1f3Ldc+ iRiIH52p8FvHmcdKhWscrtj+2cAz4llCWHeE7uD2QIIbRTaCnyWQ47y5k1ud0gDmYg1Z QOURsT847VVhN7IY0+LFM33uiVIrUCAWfGbSWsguvcLP/3PQbKizT62ILG3Fy635gI7S KrgrtzUiNh25UgaDJnWdekyHlTV7eJsYX5E7pTT6lySgXyRrBnfiy48XCAJFiOPGu/nF xjJMq0wKVS/tohxxyjYg6utCy2CVjXf8m82prydmh5As5QKYUsHzR6MgQzKcBL40UXhR XXyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8hi1p3eL3t21N4txt/xDnw2kNSKZMQWnLiLJ53KEUd4=; b=ZUKqdN+YSstWM5nnPkye5oI0K9QCulyPGXCMUvr7DxZOnSAOhVjc+HBdpMA4H8G39V 441mYimkupE6npZaWVj2//Q9O3dYDyLNDS4WclmZss4IRfitCT72PAtwwuhNfh6Xcz6X cJrN4J83KfGYw5ZJBFXGvMmBBuJfmPt/lrCVGQluLYQl8hcl83oiavN/PcJU/VyeVRX4 jWgsYPoRciP2RmacP4PpeLyJ4T5QpVzdPLAQHFCfQJM2PGCvCE09VZFpNrsrsuAhWFaM sRV1VlHtttJEj6Yzn6sRRmnSyexat3vlBK1stuhazdr4UuScJwVim62LDYzbycfsSeZ3 ROSA== X-Gm-Message-State: AGi0PubKGJe67LZV9O1fb26h4sqyoj3LNO2/575XLL2GieBkM9zK21cG cZzVbQe4DCqOb5plTcwjv/+KG3eFyWtbIw== X-Google-Smtp-Source: APiQypLIJCwX40C/RA44RlhQBMuXOdL6DxLM2bj7VrhO40yue7APIjS+4EsGk2kRPwlXz5srpO10Qg== X-Received: by 2002:adf:f704:: with SMTP id r4mr3579382wrp.5.1588247535393; Thu, 30 Apr 2020 04:52:15 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/31] device_tree: Allow name wildcards in qemu_fdt_node_path() Date: Thu, 30 Apr 2020 12:51:39 +0100 Message-Id: <20200430115142.13430-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200430115142.13430-1-peter.maydell@linaro.org> References: <20200430115142.13430-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::429 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Allow name wildcards in qemu_fdt_node_path(). This is useful to find all nodes with a given compatibility string. Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias Message-id: 20200423121114.4274-2-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- include/sysemu/device_tree.h | 3 +++ device_tree.c | 2 +- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/include/sysemu/device_tree.h b/include/sysemu/device_tree.h index c16fd69bc0b..7c53ef76345 100644 --- a/include/sysemu/device_tree.h +++ b/include/sysemu/device_tree.h @@ -39,6 +39,9 @@ void *load_device_tree_from_sysfs(void); * NULL. If there is no error but no matching node was found, the * returned array contains a single element equal to NULL. If an error * was encountered when parsing the blob, the function returns NULL + * + * @name may be NULL to wildcard names and only match compatibility + * strings. */ char **qemu_fdt_node_path(void *fdt, const char *name, char *compat, Error **errp); diff --git a/device_tree.c b/device_tree.c index bba6cc21641..f5b4699aedb 100644 --- a/device_tree.c +++ b/device_tree.c @@ -308,7 +308,7 @@ char **qemu_fdt_node_path(void *fdt, const char *name, = char *compat, offset =3D len; break; } - if (!strcmp(iter_name, name)) { + if (!name || !strcmp(iter_name, name)) { char *path; =20 path =3D g_malloc(path_len); --=20 2.20.1 From nobody Thu May 2 02:03:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1588248570; cv=none; d=zohomail.com; s=zohoarc; b=GWvXnl82GXrtKHBG6v2kpSo7KOwngQzvLsjrDSW5GFHJHnf+VNLr7gpF1vIePjwQ8D2319S4DA73IyzmWap3V+AlgjvWdjTevYj/ih6J1Wkj7bF4U3QQ+hhw6Xf+WMba5qWhUWvR1azUwAaHsTqKxS2UpVJOqqrBXYqtub8iDCI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588248570; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=AmiLI3uyw2TqnsUeUYVDfRNQU+o2aUltIEi9vudgVCE=; b=SPKxj2MPtVqIPqn7fl7dJP0bZYp+/pfrbDAgU5uBSz1RiMiUsUFpwkgynMCa2BeKhzfo87yB4XRKuvQSVRnkwZSE1I6rECtWHeTheUEdgMIdVlAzB6ww8OHIoIIp2EFRaEjKHlR798DeTPpFs0iLEB8zQLA9UHBSir61H4eYRo8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1588248570090541.8913804664057; Thu, 30 Apr 2020 05:09:30 -0700 (PDT) Received: from localhost ([::1]:46718 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU80O-00026a-Lf for importer@patchew.org; Thu, 30 Apr 2020 08:09:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33954) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU7jp-0003aG-7l for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.90_1) (envelope-from ) id 1jU7jm-0000TU-Ph for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:20 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:39342) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jU7jm-0000T7-AT for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:18 -0400 Received: by mail-wr1-x42a.google.com with SMTP id b11so6520215wrs.6 for ; Thu, 30 Apr 2020 04:52:17 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j22sm491518wre.84.2020.04.30.04.52.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 04:52:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=AmiLI3uyw2TqnsUeUYVDfRNQU+o2aUltIEi9vudgVCE=; b=E41tsTjxbtt0t/Mjpv0/VJoO8nMtiIm46h7eCKxBpC7iC/ZuOgs8Nf/1EdQ+gueHD9 +PoGf8YC2gK6/YUu6gxBii+UZttdhFzz6wNL9A2sOdpEPphBe3J1lC2I1GVzyuEk0oq+ FPYmSWFP3G9K2qKuTToRt5CSkfKcZO5WEqouX4wSQ7e9B1R/Y95j4NXbiOqQEdIB+EoH 3Wg647HVClZjm6CtdLfEN9rc209UYqTtSpoRzo+TrFkmysrdlfyxB48uLl8WNtRCdw2Q ss0KeaNNGqRw9C8tVpBIlXXzfrtD+abaniWuMNhwUdbjlD9C+aFRAdSU0Squr6m5b8GH MRcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AmiLI3uyw2TqnsUeUYVDfRNQU+o2aUltIEi9vudgVCE=; b=FufJ/GE9emHllcqkMhP+aGyqoSn9+/FfKAC8wBWt4HJo/BRJVqEdyD8bqWg9yxhv1v RT+rp91oQubwWSH8rBmxzRv51NkX/ZDAeMIrp42gaMOo7rlmhghummA7dKDdie+eXJAE +iS5OwZe4CiuNFxPc8/dG2KRdBgpMp0hYitYYggDjsdImZkYyYxU814xZmMajQI9Om4f gbnmTpvtnga3WK1yk+Mi7exbiXGi7JcUu38iiYSueCD1UMhBQ+EdEmjYuyAkZyhulIJm E9pNMxKKvT7l2IEjr+TKc5Oa8iAfIh5W1nSFJEErReK8yr/wOxPKZ0n0OVlfVbamn8hX CAPg== X-Gm-Message-State: AGi0PuYQNIZBgJ/TFa22anwBSQb2P1R9xmvXLm7YI0MhAPf45PrW1giK ftkduZtY1hgu6/0M7/zxzfTq8RUJsTk5RQ== X-Google-Smtp-Source: APiQypI7wUx+x7vBsc/AW17rvK9l7hEFkvrGRC4tlN3TSiWnMKe87PdDeKuUoYUcvVOXLuoP+VHxeQ== X-Received: by 2002:adf:e944:: with SMTP id m4mr3452919wrn.366.1588247536580; Thu, 30 Apr 2020 04:52:16 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/31] device_tree: Constify compat in qemu_fdt_node_path() Date: Thu, 30 Apr 2020 12:51:40 +0100 Message-Id: <20200430115142.13430-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200430115142.13430-1-peter.maydell@linaro.org> References: <20200430115142.13430-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::42a X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Make compat in qemu_fdt_node_path() const char *. Signed-off-by: Edgar E. Iglesias Message-id: 20200423121114.4274-3-edgar.iglesias@gmail.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/sysemu/device_tree.h | 2 +- device_tree.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/sysemu/device_tree.h b/include/sysemu/device_tree.h index 7c53ef76345..982c89345f8 100644 --- a/include/sysemu/device_tree.h +++ b/include/sysemu/device_tree.h @@ -43,7 +43,7 @@ void *load_device_tree_from_sysfs(void); * @name may be NULL to wildcard names and only match compatibility * strings. */ -char **qemu_fdt_node_path(void *fdt, const char *name, char *compat, +char **qemu_fdt_node_path(void *fdt, const char *name, const char *compat, Error **errp); =20 /** diff --git a/device_tree.c b/device_tree.c index f5b4699aedb..b335dae7075 100644 --- a/device_tree.c +++ b/device_tree.c @@ -291,7 +291,7 @@ char **qemu_fdt_node_unit_path(void *fdt, const char *n= ame, Error **errp) return path_array; } =20 -char **qemu_fdt_node_path(void *fdt, const char *name, char *compat, +char **qemu_fdt_node_path(void *fdt, const char *name, const char *compat, Error **errp) { int offset, len, ret; --=20 2.20.1 From nobody Thu May 2 02:03:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1588248388; cv=none; d=zohomail.com; s=zohoarc; b=koVTMuzaXjLDSQ2ygMDKtNqODbY1+D0c3r95Hd/fm2EXlw7udvsRKdx3GbZSJKYWZUHmSF9qZcpFe/7R+8j+C9HiBWJKufw5VNsXtX1nEJcw2Rmbyr06LsZUI3h74Uxv0IA5fArL3BWMjzP4GbsL/3SsS3BYUC0gtOkP29RNYtw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588248388; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5MreYDGc0zzBU/D/41w93auz/a1cW5LbSgeXIHJsmWA=; b=UL8702W5/jbKLb5BB4d0+E+pmG5NVURUaDnbYIptfbtS5sDVqRniDbLVW7/sotgPyRYH7bwxvmSWdVuMfeAtH9rdRXBhoWEhVA8X8TI9XOWv234pynk2KdpNt/LOXNXLMvWGZ5qXYgGWcoc7firFLmusCM3G34lVguv6g/KWxeg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15882483881601021.0309753767225; Thu, 30 Apr 2020 05:06:28 -0700 (PDT) Received: from localhost ([::1]:34274 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU7xR-0004on-Jl for importer@patchew.org; Thu, 30 Apr 2020 08:06:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33958) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU7jp-0003bo-TP for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.90_1) (envelope-from ) id 1jU7jn-0000Tm-Lx for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:21 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:36604) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jU7jn-0000TP-8l for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:19 -0400 Received: by mail-wr1-x432.google.com with SMTP id d15so6537699wrx.3 for ; Thu, 30 Apr 2020 04:52:18 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j22sm491518wre.84.2020.04.30.04.52.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 04:52:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=5MreYDGc0zzBU/D/41w93auz/a1cW5LbSgeXIHJsmWA=; b=F5N4U4tCRmGgV9G9Eka+Fuc2AdkBON+Wc+9U1z1aalUdaCuXxakBV9FzhNPzgsMk2j +ijSQ+6oB/q4v4IQxx1jZlfy+FOLLEOzCFLOJV30kGb34w0YilrysIxkjKWZ14h26iNN a2oHLGCltQ2fDcd9P/2ffQ0Ocn/B/s2MB4AjHBcfmV5E6b8gcgi4ZGhqaGHK2Q7tDCg6 f2xNXXmXUrd6K00Rh4Ei7BmtrnV4oyzGIDiXv6P3/ga62ZnqeTgHL9m0+WISFBC9s+7M 0eOjq6+dQ8avUjbhq//Y9tcE3VUuU5kHl0vwOC8mnmlhkiHBNSIsygHZfNDpuMj6DW0A hq/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5MreYDGc0zzBU/D/41w93auz/a1cW5LbSgeXIHJsmWA=; b=K+2thIfXJ/CSMbBrcuJtR56yr+ZzITNKbMgX+tx5lvMjUiFOWgznzfdW996TRZ/Oey O8LMOQ5wgwM9fiFJFYxF49o08Ef57yzqHQio1D0/97AAQr2IeCzm9vOw6lkUa+8kuNX7 EfTc6Cm1exj575+OnmiF5Y+i4oftSy5pOtU50hJc1p+kh04yKFopT3BsDoL9j4R74Eso D3WumtM/ItCyxpCNAG6MfsAft83Sy2Rgw0dG/Ry8adraZAY5w0RrPzZaNblp8Ya1lhGV ThFjjkfpB3wmV8OzPwKtyUUgiRazTphZf2pF5LuzJRbZkzQozK6CNG/Execxpu3tm35J e9nA== X-Gm-Message-State: AGi0PubPeGFo6ZWFStHZ86tvXjfKHkjwzOIjrlK15I+gHptp1MhVWV/S IgHR6wWifofmjegG8kRMxksg0VdQYI4hqw== X-Google-Smtp-Source: APiQypK+LKsTVKM/2daga9dP28KEgzwTK3W2nyGpXZnNnxp0+3NM/z7b/MslH4/n/rXS5uJ0SNPZqg== X-Received: by 2002:a5d:4109:: with SMTP id l9mr3514446wrp.300.1588247537651; Thu, 30 Apr 2020 04:52:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/31] hw/arm: xlnx-zcu102: Move arm_boot_info into XlnxZCU102 Date: Thu, 30 Apr 2020 12:51:41 +0100 Message-Id: <20200430115142.13430-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200430115142.13430-1-peter.maydell@linaro.org> References: <20200430115142.13430-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::432 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) From: "Edgar E. Iglesias" Move arm_boot_info into XlnxZCU102. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Edgar E. Iglesias Message-id: 20200423121114.4274-4-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- hw/arm/xlnx-zcu102.c | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index bd645ad8187..4eb117c755a 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -31,13 +31,14 @@ typedef struct XlnxZCU102 { =20 bool secure; bool virt; + + struct arm_boot_info binfo; } XlnxZCU102; =20 #define TYPE_ZCU102_MACHINE MACHINE_TYPE_NAME("xlnx-zcu102") #define ZCU102_MACHINE(obj) \ OBJECT_CHECK(XlnxZCU102, (obj), TYPE_ZCU102_MACHINE) =20 -static struct arm_boot_info xlnx_zcu102_binfo; =20 static bool zcu102_get_secure(Object *obj, Error **errp) { @@ -166,9 +167,9 @@ static void xlnx_zcu102_init(MachineState *machine) =20 /* TODO create and connect IDE devices for ide_drive_get() */ =20 - xlnx_zcu102_binfo.ram_size =3D ram_size; - xlnx_zcu102_binfo.loader_start =3D 0; - arm_load_kernel(s->soc.boot_cpu_ptr, machine, &xlnx_zcu102_binfo); + s->binfo.ram_size =3D ram_size; + s->binfo.loader_start =3D 0; + arm_load_kernel(s->soc.boot_cpu_ptr, machine, &s->binfo); } =20 static void xlnx_zcu102_machine_instance_init(Object *obj) --=20 2.20.1 From nobody Thu May 2 02:03:36 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1588248454; cv=none; d=zohomail.com; s=zohoarc; b=KJOINxzEzLgMNnDHqmNgWKJYasKMCeqTxZ6AlaIv+yjy7cFlZ+aejh2qrp8sqsQjGzpoxLBAS3lfM7VWYMttau7Q2PtDq7gSDbvL+jsY2Lw3cDE3MxzTQnZ+3nTjBjkQ6g3I7NeXozyEkIVN16G06fpakvFn6WG583M30KR9aVQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588248454; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VZsHlwetQydlsAkMRlAw7EDxgaTnzCyVqrqpBTTMf/c=; b=Y2aqv5ce+K0thRYfI/PNps+d60WnD1XWLEJGITXjlq1yCQZ2OYURm+h6dy0WCkPiyCjdmjwdsWBSXU/NyGliAvSipRM0J1n8oCFQ489fXBuRkYwL/2aYxkvdwcieQU5Tta0ICtjPrDpiSlqroeUH8NT9JUzkXh8bz0FBCK7f7Bg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1588248454404692.6671393361769; Thu, 30 Apr 2020 05:07:34 -0700 (PDT) Received: from localhost ([::1]:39404 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU7yX-0006rs-5p for importer@patchew.org; Thu, 30 Apr 2020 08:07:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33964) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU7jq-0003de-KD for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.90_1) (envelope-from ) id 1jU7jo-0000U5-UZ for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:22 -0400 Received: from mail-wm1-x342.google.com ([2a00:1450:4864:20::342]:51181) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jU7jo-0000Tk-FJ for qemu-devel@nongnu.org; Thu, 30 Apr 2020 07:52:20 -0400 Received: by mail-wm1-x342.google.com with SMTP id x25so1516912wmc.0 for ; Thu, 30 Apr 2020 04:52:20 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [81.2.115.148]) by smtp.gmail.com with ESMTPSA id j22sm491518wre.84.2020.04.30.04.52.17 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 30 Apr 2020 04:52:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=VZsHlwetQydlsAkMRlAw7EDxgaTnzCyVqrqpBTTMf/c=; b=JtVAIYRtFhqDdwotVAXgWuqjjVQWXK3S7kHnqDR9nNUI6oOBPSaWl17TG1FYklyeo/ BC0zpEKuS2H4GlutoLkbBP/be4g0db1+f6amIL3jeqng/fSm1R20siIVQqYTZaH7GZ8N cYFIn+mDOHjygCyzPa/C2Tb9rtJHi1MQJwAtHA4r5R0Jsohs0wWatfp1kIZ4R1eom2kB XULSySDN/D4PhE2IyXfLUp8VQXzHipOsQtTcCIqV+ZaMwjUDe5qURU85ZgZICO83onif jjHcgnUUHHDJIdqE43aRjaVaMx1b5DOUgHGm6Hm0ARDNGzzdBv2VUOpU7eHZmO1mVzBk DT/Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VZsHlwetQydlsAkMRlAw7EDxgaTnzCyVqrqpBTTMf/c=; b=i5v0vqOM7zYHiBmObEtKlXGo+ZPVS0ubU6gUP3IXfEvlaMukxU+RUM5vAFxSFNf7BT OsKPCarQVwQfWIX1A2iUqMikiRa5luHYhaZTUl7j+rnii+Gch0fiLfSUlbtxJT0YSUeu ob0fGs1zh0THY6LkgHBNy5AEbXzdR/gK0aclV/0aEtqdgFZfiNErSRF12SmmtgezLT7U K4ZeP50bOnd64PaecowcSBsE2BJKk1ZDBQnIuKBIktumDk9A78ZlFZLNJcfdzQ7yAmm7 evrRTWELqak0QROBLGW6MYLZ3wkDpa/ky3paDlWjR1P1COKuya2SIw2zXMXgIq/a/H5x jqAw== X-Gm-Message-State: AGi0PuZRxlUbWi6acaMIfbF7dK3padmF4JbQTMEwHyvq/DyBcdCDiI+2 WZTUrF3TKOFGw3JwewsFmSLKWX8RCe/TsQ== X-Google-Smtp-Source: APiQypJIn/2iluGTKXSAEhXjRZA47Wid20MRNxvPsEa9SI/yrqdPjO1s6MjS9c2o6MSY6YmND2VA5g== X-Received: by 2002:a7b:c0d5:: with SMTP id s21mr2569473wmh.107.1588247538758; Thu, 30 Apr 2020 04:52:18 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/31] hw/arm: xlnx-zcu102: Disable unsupported FDT firmware nodes Date: Thu, 30 Apr 2020 12:51:42 +0100 Message-Id: <20200430115142.13430-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200430115142.13430-1-peter.maydell@linaro.org> References: <20200430115142.13430-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::342; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x342.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::342 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Disable unsupported FDT firmware nodes if a user passes us a DTB with nodes enabled that the machine cannot support due to lack of EL3 or EL2 support. Reviewed-by: Alistair Francis Signed-off-by: Edgar E. Iglesias Message-id: 20200423121114.4274-5-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- hw/arm/xlnx-zcu102.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index 4eb117c755a..a798e228b79 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -23,6 +23,7 @@ #include "qemu/error-report.h" #include "qemu/log.h" #include "sysemu/qtest.h" +#include "sysemu/device_tree.h" =20 typedef struct XlnxZCU102 { MachineState parent_obj; @@ -68,6 +69,34 @@ static void zcu102_set_virt(Object *obj, bool value, Err= or **errp) s->virt =3D value; } =20 +static void zcu102_modify_dtb(const struct arm_boot_info *binfo, void *fdt) +{ + XlnxZCU102 *s =3D container_of(binfo, XlnxZCU102, binfo); + bool method_is_hvc; + char **node_path; + const char *r; + int prop_len; + int i; + + /* If EL3 is enabled, we keep all firmware nodes active. */ + if (!s->secure) { + node_path =3D qemu_fdt_node_path(fdt, NULL, "xlnx,zynqmp-firmware", + &error_fatal); + + for (i =3D 0; node_path && node_path[i]; i++) { + r =3D qemu_fdt_getprop(fdt, node_path[i], "method", &prop_len,= NULL); + method_is_hvc =3D r && !strcmp("hvc", r); + + /* Allow HVC based firmware if EL2 is enabled. */ + if (method_is_hvc && s->virt) { + continue; + } + qemu_fdt_setprop_string(fdt, node_path[i], "status", "disabled= "); + } + g_strfreev(node_path); + } +} + static void xlnx_zcu102_init(MachineState *machine) { XlnxZCU102 *s =3D ZCU102_MACHINE(machine); @@ -169,6 +198,7 @@ static void xlnx_zcu102_init(MachineState *machine) =20 s->binfo.ram_size =3D ram_size; s->binfo.loader_start =3D 0; + s->binfo.modify_dtb =3D zcu102_modify_dtb; arm_load_kernel(s->soc.boot_cpu_ptr, machine, &s->binfo); } =20 --=20 2.20.1