From nobody Fri Nov 14 15:21:07 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1588231605; cv=none; d=zohomail.com; s=zohoarc; b=SH3P7fBkwLX6FLhO/HLEH2+u2ZZQ0DieACpt/+CQcHX9+qZ41Xwjc5UlO3dCAQjkjqN5Od6jbvHPyjCzdiTLZdimrm3ZQjney/XFxS475AEPx41D6NIquPrUQpKzAAv7403Ny36H46ha9WU8ES9BMweI5eaMmDPczvZ/7jGUGIA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588231605; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VTO6EsLKSyS2MC+aQophla1eY1e/HFduXILoVkJamPk=; b=l3r8htRfMyL8qRkMMqrH3+bv1T+1gLXS9YfJiw/2Lf07CSLnNb7k+xGW7GLFivWV79OLQkyQQhV5KSbkrtCDfWL4Ojw/un7sGX5ACT5UhqGeiSGHlxHO98D7NypkPe1pi+w0z6Djd17EBygezvgbzN+ZHRm7ARvpBRqqNXcxpUI= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1588231605538717.3542921179819; Thu, 30 Apr 2020 00:26:45 -0700 (PDT) Received: from localhost ([::1]:33288 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU3am-0001tE-7A for importer@patchew.org; Thu, 30 Apr 2020 03:26:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34278) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU3XZ-0004ct-QN for qemu-devel@nongnu.org; Thu, 30 Apr 2020 03:23:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.90_1) (envelope-from ) id 1jU3W7-0006Yg-T2 for qemu-devel@nongnu.org; Thu, 30 Apr 2020 03:23:25 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:42105) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jU3W6-0006WV-Tx; Thu, 30 Apr 2020 03:21:55 -0400 Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.HQfovas_1588231302) by smtp.aliyun-inc.com(10.147.40.7); Thu, 30 Apr 2020 15:21:45 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436398|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0951211-0.00075412-0.904125; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03295; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.HQfovas_1588231302; From: LIU Zhiwei To: peter.maydell@linaro.org Subject: [RFC PATCH 4/8] riscv: Implement payload load interfaces Date: Thu, 30 Apr 2020 15:21:35 +0800 Message-Id: <20200430072139.4602-5-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200430072139.4602-1-zhiwei_liu@c-sky.com> References: <20200430072139.4602-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/30 03:21:44 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Received-From: 121.197.200.217 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com, wenmeng_zhang@c-sky.com, palmer@dabbelt.com, alistair23@gmail.com, alex.bennee@linaro.org, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei --- risu_reginfo_riscv64.c | 134 +++++++++++++++++++++++++++++++++++++++++ risu_riscv64.c | 47 +++++++++++++++ 2 files changed, 181 insertions(+) create mode 100644 risu_reginfo_riscv64.c create mode 100644 risu_riscv64.c diff --git a/risu_reginfo_riscv64.c b/risu_reginfo_riscv64.c new file mode 100644 index 0000000..cfa9889 --- /dev/null +++ b/risu_reginfo_riscv64.c @@ -0,0 +1,134 @@ +/*************************************************************************= ***** + * Copyright (c) 2020 PingTouGe Semiconductor + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * which accompanies this distribution, and is available at + * http://www.eclipse.org/legal/epl-v10.html + * + * Contributors: + * LIU Zhiwei (PingTouGe) - initial implementation + * based on Peter Maydell's risu_arm.c + *************************************************************************= ****/ + +#include +#include +#include +#include /* for FPSIMD_MAGIC */ +#include +#include +#include +#include +#include +#include + +#include "risu.h" +#include "risu_reginfo_riscv64.h" + +const struct option * const arch_long_opts; +const char * const arch_extra_help; + +void process_arch_opt(int opt, const char *arg) +{ + abort(); +} + +const int reginfo_size(void) +{ + return sizeof(struct reginfo); +} + +/* reginfo_init: initialize with a ucontext */ +void reginfo_init(struct reginfo *ri, ucontext_t *uc) +{ + int i; + union __riscv_mc_fp_state *fp; + /* necessary to be able to compare with memcmp later */ + memset(ri, 0, sizeof(*ri)); + + for (i =3D 0; i < 32; i++) { + ri->regs[i] =3D uc->uc_mcontext.__gregs[i]; + } + + ri->sp =3D 0xdeadbeefdeadbeef; + ri->regs[2] =3D 0xdeadbeefdeadbeef; + ri->regs[3] =3D 0xdeadbeefdeadbeef; + ri->regs[4] =3D 0xdeadbeefdeadbeef; + ri->pc =3D uc->uc_mcontext.__gregs[0] - image_start_address; + ri->faulting_insn =3D *((uint32_t *) uc->uc_mcontext.__gregs[0]); + fp =3D &uc->uc_mcontext.__fpregs; + ri->fcsr =3D fp->__d.__fcsr; + + for (i =3D 0; i < 32; i++) { + ri->fregs[i] =3D fp->__d.__f[i]; + } +} + +/* reginfo_is_eq: compare the reginfo structs, returns nonzero if equal */ +int reginfo_is_eq(struct reginfo *r1, struct reginfo *r2) +{ + return memcmp(r1, r2, reginfo_size()) =3D=3D 0; +} + +/* reginfo_dump: print state to a stream, returns nonzero on success */ +int reginfo_dump(struct reginfo *ri, FILE * f) +{ + int i; + fprintf(f, " faulting insn %08x\n", ri->faulting_insn); + + for (i =3D 1; i < 32; i++) { + fprintf(f, " X%-2d : %016" PRIx64 "\n", i, ri->regs[i]); + } + + fprintf(f, " sp : %016" PRIx64 "\n", ri->sp); + fprintf(f, " pc : %016" PRIx64 "\n", ri->pc); + fprintf(f, " fcsr : %08x\n", ri->fcsr); + + for (i =3D 0; i < 32; i++) { + fprintf(f, " F%-2d : %016" PRIx64 "\n", i, ri->fregs[i]); + } + + return !ferror(f); +} + +/* reginfo_dump_mismatch: print mismatch details to a stream, ret nonzero= =3Dok */ +int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE * f) +{ + int i; + fprintf(f, "mismatch detail (master : apprentice):\n"); + if (m->faulting_insn !=3D a->faulting_insn) { + fprintf(f, " faulting insn mismatch %08x vs %08x\n", + m->faulting_insn, a->faulting_insn); + } + for (i =3D 1; i < 32; i++) { + if (m->regs[i] !=3D a->regs[i]) { + fprintf(f, " X%-2d : %016" PRIx64 " vs %016" PRIx64 "\n", + i, m->regs[i], a->regs[i]); + } + } + + if (m->sp !=3D a->sp) { + fprintf(f, " sp : %016" PRIx64 " vs %016" PRIx64 "\n", + m->sp, a->sp); + } + + if (m->pc !=3D a->pc) { + fprintf(f, " pc : %016" PRIx64 " vs %016" PRIx64 "\n", + m->pc, a->pc); + } + + if (m->fcsr !=3D a->fcsr) { + fprintf(f, " fcsr : %08x vs %08x\n", m->fcsr, a->fcsr); + } + + for (i =3D 0; i < 32; i++) { + if (m->fregs[i] !=3D a->fregs[i]) { + fprintf(f, " F%-2d : " + "%016" PRIx64 " vs " + "%016" PRIx64 "\n", i, + (uint64_t) m->fregs[i], + (uint64_t) a->fregs[i]); + } + } + + return !ferror(f); +} diff --git a/risu_riscv64.c b/risu_riscv64.c new file mode 100644 index 0000000..f742a40 --- /dev/null +++ b/risu_riscv64.c @@ -0,0 +1,47 @@ +/*************************************************************************= ***** + * Copyright (c) 2020 PingTouGe Semiconductor + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * which accompanies this distribution, and is available at + * http://www.eclipse.org/legal/epl-v10.html + * + * Contributors: + * LIU Zhiwei(Linaro) - initial implementation + * based on Peter Maydell's risu_arm.c + *************************************************************************= ****/ + +#include "risu.h" + +void advance_pc(void *vuc) +{ + ucontext_t *uc =3D vuc; + uc->uc_mcontext.__gregs[0] +=3D 4; +} + +void set_ucontext_paramreg(void *vuc, uint64_t value) +{ + ucontext_t *uc =3D vuc; + uc->uc_mcontext.__gregs[10] =3D value; +} + +uint64_t get_reginfo_paramreg(struct reginfo *ri) +{ + return ri->regs[10]; +} + +int get_risuop(struct reginfo *ri) +{ + /* Return the risuop we have been asked to do + * (or -1 if this was a SIGILL for a non-risuop insn) + */ + uint32_t insn =3D ri->faulting_insn; + uint32_t op =3D (insn & 0xf00) >> 8; + uint32_t key =3D insn & ~0xf00; + uint32_t risukey =3D 0x0000006b; + return (key !=3D risukey) ? -1 : op; +} + +uintptr_t get_pc(struct reginfo *ri) +{ + return ri->pc; +} --=20 2.23.0