From nobody Fri Nov 14 13:38:15 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1588231605; cv=none; d=zohomail.com; s=zohoarc; b=lTYH3G4QeTwccnCNL5oVOmaV7SzTHzgKjWIxDDnW77DeE6n89ogdDkwCR+wUx1eXd7fOTuMAaZn7d7cwrABHVV5343LrY8OTrn1U/XAgcHaPAXp6B4Gqlh/CkELOhfQjTbo6GpQLKKh7WF3rBE99FNYN9A1m5GcRXyqNe7A8JrE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588231605; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lm4e+zrp2V8siFcq+xMEudZnmDIxt16uJz70sgo0M9Q=; b=PY2QGPeRVrLkwBOdHELc4ivFyFPJU2lThhWoHzRhS5yCFnCtYDQfqWgV6b30YB6vTZelpGEgZ24lgS3i9q6x2P1PXgA3z041hYz8CNXcxyRTdzP+B0+Z/3XYyNU6heZ55A+SX2aDK2NeVBg45IXkKFOJb2DipyyiFNzV0pDUAf4= ARC-Authentication-Results: i=1; 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Thu, 30 Apr 2020 03:21:55 -0400 Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.HQfovas_1588231302) by smtp.aliyun-inc.com(10.147.40.7); Thu, 30 Apr 2020 15:21:43 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436282|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.704462-0.000721421-0.294816; FP=0|0|0|0|0|-1|-1|-1; HT=e01l07447; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.HQfovas_1588231302; From: LIU Zhiwei To: peter.maydell@linaro.org Subject: [RFC PATCH 1/8] riscv: Add RV64I instructions description Date: Thu, 30 Apr 2020 15:21:32 +0800 Message-Id: <20200430072139.4602-2-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200430072139.4602-1-zhiwei_liu@c-sky.com> References: <20200430072139.4602-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/30 03:21:44 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Received-From: 121.197.200.217 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com, wenmeng_zhang@c-sky.com, palmer@dabbelt.com, alistair23@gmail.com, alex.bennee@linaro.org, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei --- riscv64.risu | 141 +++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 141 insertions(+) create mode 100644 riscv64.risu diff --git a/riscv64.risu b/riscv64.risu new file mode 100644 index 0000000..98141ab --- /dev/null +++ b/riscv64.risu @@ -0,0 +1,141 @@ +# Input file for risugen defining RISC-V instructions +.mode riscv +@RV64I + +# x2 stack pointer, x3 global pointer, x4 thread pointer +# These registers should be reserved for signal handler. + +LUI RISCV imm:20 rd:5 0110111 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 } + +AUIPC RISCV imm:20 rd:5 0110111 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 } + +# Limit to current implementation, the base address register will be overi= de +LB RISCV imm:12 rs1:5 000 rd:5 0000011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 0 && $r= s1 !=3D 2 && $rs1 !=3D 3 && $rs1 !=3D 4 } \ +!memory { align(1); reg_plus_imm($rs1, sextract($imm, 12)); } + +LH RISCV imm:12 rs1:5 001 rd:5 0000011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 0 && $r= s1 !=3D 2 && $rs1 !=3D 3 && $rs1 !=3D 4 } \ +!memory { align(2); reg_plus_imm($rs1, sextract($imm, 12)); } + +LW RISCV imm:12 rs1:5 010 rd:5 0000011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 0 && $r= s1 !=3D 2 && $rs1 !=3D 3 && $rs1 !=3D 4 } \ +!memory { align(4); reg_plus_imm($rs1, sextract($imm, 12)); } + +LBU RISCV imm:12 rs1:5 100 rd:5 0000011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 0 && $r= s1 !=3D 2 && $rs1 !=3D 3 && $rs1 !=3D 4 } \ +!memory { align(1); reg_plus_imm($rs1, sextract($imm, 12)); } + +LHU RISCV imm:12 rs1:5 101 rd:5 0000011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 0 && $r= s1 !=3D 2 && $rs1 !=3D 3 && $rs1 !=3D 4 } \ +!memory { align(2); reg_plus_imm($rs1, sextract($imm, 12)); } + +SB RISCV imm5:7 rs2:5 rs1:5 000 imm:5 0100011 \ +!constraints { $rs1 !=3D 0 && $rs1 !=3D 2 && $rs1 !=3D3 && $rs1 !=3D 4 && = $rs2 !=3D 2 } \ +!memory { align(1); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); } + +SH RISCV imm5:7 rs2:5 rs1:5 001 imm:5 0100011 \ +!constraints { $rs1 !=3D 0 && $rs1 !=3D 2 && $rs1 !=3D3 && $rs1 !=3D 4 && = $rs2 !=3D 2 } \ +!memory { align(2); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); } + +SW RISCV imm5:7 rs2:5 rs1:5 010 imm:5 0100011 \ +!constraints { $rs1 !=3D 0 && $rs1 !=3D 2 && $rs1 !=3D3 && $rs1 !=3D 4 && = $rs2 !=3D 2 } \ +!memory { align(4); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); } + +ADDI RISCV imm:12 rs1:5 000 rd:5 0010011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 } + +SLTI RISCV imm:12 rs1:5 010 rd:5 0010011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 } + +SLTIU RISCV imm:12 rs1:5 011 rd:5 0010011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 } + +XORI RISCV imm:12 rs1:5 100 rd:5 0010011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 } + +ORI RISCV imm:12 rs1:5 110 rd:5 0010011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 } + +ANDI RISCV imm:12 rs1:5 111 rd:5 0010011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 } + +ADD RISCV 0000000 rs2:5 rs1:5 000 rd:5 0110011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 && $r= s2 !=3D 2 } + +SUB RISCV 0100000 rs2:5 rs1:5 000 rd:5 0110011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 && $r= s2 !=3D 2 } + +SLL RISCV 0000000 rs2:5 rs1:5 001 rd:5 0110011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 && $r= s2 !=3D 2 } + +SLT RISCV 0000000 rs2:5 rs1:5 010 rd:5 0110011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 && $r= s2 !=3D 2 } + +SLTU RISCV 0000000 rs2:5 rs1:5 011 rd:5 0110011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 && $r= s2 !=3D 2 } + +XOR RISCV 0000000 rs2:5 rs1:5 100 rd:5 0110011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 && $r= s2 !=3D 2 } + +SRL RISCV 0000000 rs2:5 rs1:5 101 rd:5 0110011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 && $r= s2 !=3D 2 } + +SRA RISCV 0100000 rs2:5 rs1:5 101 rd:5 0110011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 && $r= s2 !=3D 2 } + +OR RISCV 0000000 rs2:5 rs1:5 110 rd:5 0110011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 && $r= s2 !=3D 2 } + +AND RISCV 0000000 rs2:5 rs1:5 111 rd:5 0110011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 && $r= s2 !=3D 2 } + +LWU RISCV imm:12 rs1:5 110 rd:5 0000011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 0 && $r= s1 !=3D 2 && $rs1 !=3D 3 && $rs1 !=3D 4 } \ +!memory { align(4); reg_plus_imm($rs1, sextract($imm, 12)); } + +LD RISCV imm:12 rs1:5 011 rd:5 0000011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 0 && $r= s1 !=3D 2 && $rs1 !=3D 3 && $rs1 !=3D 4 } \ +!memory { align(8); reg_plus_imm($rs1, sextract($imm, 12)); } + +SD RISCV imm5:7 rs2:5 rs1:5 011 imm:5 0100011 \ +!constraints { $rs1 !=3D 0 && $rs1 !=3D 2 && $rs1 !=3D3 && $rs1 !=3D 4 && = $rs2 !=3D 2} \ +!memory { align(8); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); } + +SLLI RISCV 00000 sham5:7 rs1:5 001 rd:5 0010011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 } + +SRLI RISCV 00000 sham5:7 rs1:5 101 rd:5 0010011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 } + +SRAI RISCV 01000 sham5:7 rs1:5 101 rd:5 0010011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 } + +ADDIW RISCV imm:12 rs1:5 000 rd:5 0011011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 } + +SLLIW RISCV 0000000 shamt:5 rs1:5 001 rd:5 0011011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 } + +SRLIW RISCV 0000000 shamt:5 rs1:5 101 rd:5 0011011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 } + +SRAIW RISCV 0100000 shamt:5 rs1:5 101 rd:5 0011011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 } + +ADDW RISCV 0000000 rs2:5 rs1:5 000 rd:5 0011011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 } + +SUBW RISCV 0100000 rs2:5 rs1:5 000 rd:5 0011011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 } + +SLLW RISCV 0000000 rs2:5 rs1:5 001 rd:5 0011011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 } + +SRLW RISCV 0000000 rs2:5 rs1:5 101 rd:5 0011011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 } + +SRAW RISCV 0100000 rs2:5 rs1:5 101 rd:5 0011011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 } --=20 2.23.0 From nobody Fri Nov 14 13:38:15 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1588231689; cv=none; d=zohomail.com; s=zohoarc; b=EnKIvwVL6Lb5Y+tWLPOnDaWK8XTpXP4onRHGard9PdUYlVgMimAKBKeIKIsF6w4IoBbRgxlDPcecQ2FKb5phIBY1+PsRakuF8N0xnOLcGQqf8eSK0hH5LpwDIn0jY0TLwMtqhCbLKNwmL1P4GalMyIaTa1p6k4+S5Or1SKCsGn0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588231689; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+cS+ZIaAla30+g8InOuTW00Y5WtjHtmdHymd1Kua9PI=; b=ZjJurGVT3S5hVaf64QSR1bv8J298dHfDvgtGwDLlwJBSKspm3fcAqJkl0z6V8sApJe3yUFT5YZaRU59/xvj1In8JJdozEG3ZeVMeHcPw+EvpKgvWYgM/i1POyMG4OIR2jbX+4zA1Xv5DDjFKBKnlNwKWkWsuRqLwX+SxlU44DRA= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1588231689439166.22565994510796; Thu, 30 Apr 2020 00:28:09 -0700 (PDT) Received: from localhost ([::1]:40568 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU3c8-0004zB-5O for importer@patchew.org; Thu, 30 Apr 2020 03:28:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34286) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU3Xb-0004i1-Q1 for qemu-devel@nongnu.org; Thu, 30 Apr 2020 03:23:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.90_1) (envelope-from ) id 1jU3W8-0006Yu-49 for qemu-devel@nongnu.org; Thu, 30 Apr 2020 03:23:27 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:46114) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jU3W6-0006WR-Rn; Thu, 30 Apr 2020 03:21:55 -0400 Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.HQfovas_1588231302) by smtp.aliyun-inc.com(10.147.40.7); Thu, 30 Apr 2020 15:21:44 +0800 X-Alimail-AntiSpam: AC=PASS; BC=0.07436282|-1; BR=01201311R111ee; CH=green; DM=|CONTINUE|false|; DS=SPAM|spam_ad|0.906831-5.56391e-05-0.0931137; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03306; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.HQfovas_1588231302; From: LIU Zhiwei To: peter.maydell@linaro.org Subject: [RFC PATCH 2/8] riscv: Generate payload scripts Date: Thu, 30 Apr 2020 15:21:33 +0800 Message-Id: <20200430072139.4602-3-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200430072139.4602-1-zhiwei_liu@c-sky.com> References: <20200430072139.4602-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/30 03:21:44 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Received-From: 121.197.200.217 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com, wenmeng_zhang@c-sky.com, palmer@dabbelt.com, alistair23@gmail.com, alex.bennee@linaro.org, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei --- risugen_riscv.pm | 501 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 501 insertions(+) create mode 100644 risugen_riscv.pm diff --git a/risugen_riscv.pm b/risugen_riscv.pm new file mode 100644 index 0000000..092c246 --- /dev/null +++ b/risugen_riscv.pm @@ -0,0 +1,501 @@ +#!/usr/bin/perl -w +##########################################################################= ##### +# All rights reserved. This program and the accompanying materials +# are made available under the terms of the Eclipse Public License v1.0 +# which accompanies this distribution, and is available at +# http://www.eclipse.org/legal/epl-v10.html +# +# Contributors: +# LIU Zhiwei (PingTouGe) - RISC-V implementation +# based on Peter Maydell (Linaro) - initial implementation +##########################################################################= ##### + +# risugen -- generate a test binary file for use with risu +# See 'risugen --help' for usage information. +package risugen_riscv; + +use strict; +use warnings; + +use risugen_common; + +require Exporter; + +our @ISA =3D qw(Exporter); +our @EXPORT =3D qw(write_test_code); + +my $periodic_reg_random =3D 1; + +# +# Maximum alignment restriction permitted for a memory op. +my $MAXALIGN =3D 64; +sub ctz($) +{ + my ($imm) =3D @_; + my $cnt =3D 0; + + if ($imm =3D=3D 0) { + return 0; + } + while (($imm & 1) =3D=3D 0) { + $cnt++; + $imm =3D $imm >> 1; + } + return $cnt; +} + +sub decode_li($) +{ + my ($imm) =3D @_; + my $cnt =3D 0; + my $idx =3D 0; + my $part =3D 0; + my $next =3D 0; + my %result; + + $next =3D $imm; + # only one lui can not hold + while ((($next >> 12) !=3D sextract(($next >> 12) & 0xfffff, 20)) || + (($next & 0xfff) !=3D 0)) { + # at the first time, just eat the least 12 bits + if ($idx =3D=3D 0) { + $part =3D sextract($imm & 0xfff, 12); + $result{"first"} =3D $part; + } else { + $imm =3D $imm - $part; # clear the part before it + $cnt =3D ctz($imm); # add a shift + $imm >>=3D $cnt; + $part =3D sextract($imm & 0xfff, 12); + $result{"mid"}{$idx}{"part"} =3D $part; + $result{"mid"}{$idx}{"cnt"} =3D $cnt; + $next =3D $imm - $part; + } + $idx++; + } + # output a lui + $result{"lui"} =3D sextract(($next >> 12) & 0xfffff, 20); + return %result; +} + +# li is implements as Myraid sequences, just the common way here +sub write_mov_ri($$) +{ + my ($rd, $imm) =3D @_; + + # sequence of li rd, 0x1234567887654321 + # + # 0: 002471b7 lui rd,0x247 + # 4: 8ad1819b addiw rd,rd,-1875 + # 8: 00c19193 slli rd,rd,0xc + # c: f1118193 addi rd,rd,-239 # 0x246f11 + # 10: 00d19193 slli rd,rd,0xd + # 14: d9518193 addi rd,rd,-619 + # 18: 00e19193 slli rd,rd,0xe + # 1c: 32118193 addi rd,rd,801 + my %result =3D decode_li($imm); + + my $len =3D keys %{$result{"mid"}}; + my $i =3D 0; + + # output the last lui + insn32(0x00000037 | $rd << 7 | $result{"lui"} << 12); + # output the sequence of slli and addi + foreach my $key (reverse sort keys %{$result{"mid"}}) { + $i++; + if ($i =3D=3D 1) { + # output the last addiw + insn32(0x0000001b | $rd << 7 | $rd << 15 | + $result{"mid"}{$key}{"part"} << 20); + # slli rd, rd, $result{"mid"}{$key}{"part"} + insn32(0x00001013 | $rd << 7 | $rd << 15 | + $result{"mid"}{$key}{"cnt"} << 20); + } else { + insn32(0x00000013 | $rd << 7 | $rd << 15 | + ($result{"mid"}{$key}{"part"} & 0xfff) << 20); + # slli rd, rd, $result{"mid"}{$key}{"part"} + insn32(0x00001013 | $rd << 7 | $rd << 15 | + $result{"mid"}{$key}{"cnt"} << 20); + } + } + # addi rd, rd, $result{"first"} + insn32(0x00000013 | $rd << 7 | $rd << 15 | ($imm & 0xfff) << 20); +} + +sub write_mov_rr($$) +{ + my ($rd, $rs1) =3D @_; + + # addi $rd, $rs1, 0 + insn32(0x00000013 | $rd << 7 | $rs1 << 15); +} + +sub write_sub_rrr($$$) +{ + my ($rd, $rs1, $rs2) =3D @_; + + # sub $rd, $rs1, $rs2 + insn32(0x40000033 |$rd << 7 | $rs1 << 15 | $rs2 << 20); +} + +my $OP_COMPARE =3D 0; # compare registers +my $OP_TESTEND =3D 1; # end of test, stop +my $OP_SETMEMBLOCK =3D 2; # r0 is address of memory block (8192 bytes) +my $OP_GETMEMBLOCK =3D 3; # add the address of memory block to r0 +my $OP_COMPAREMEM =3D 4; # compare memory block + +# write random fp value of passed precision (1=3Dsingle, 2=3Ddouble) +sub write_random_fpreg_var($) +{ + my ($precision) =3D @_; + my $randomize_low =3D 0; + + if ($precision !=3D 1 && $precision !=3D 2) { + die "write_random_fpreg: invalid precision.\n"; + } + + my ($low, $high); + my $r =3D rand(100); + if ($r < 5) { + # +-0 (5%) + $low =3D $high =3D 0; + $high |=3D 0x80000000 if (rand() < 0.5); + } elsif ($r < 10) { + # NaN (5%) + # (plus a tiny chance of generating +-Inf) + $randomize_low =3D 1; + $high =3D rand(0xffffffff) | 0x7ff00000; + } elsif ($r < 15) { + # Infinity (5%) + $low =3D 0; + $high =3D 0x7ff00000; + $high |=3D 0x80000000 if (rand() < 0.5); + } elsif ($r < 30) { + # Denormalized number (15%) + # (plus tiny chance of +-0) + $randomize_low =3D 1; + $high =3D rand(0xffffffff) & ~0x7ff00000; + } else { + # Normalized number (70%) + # (plus a small chance of the other cases) + $randomize_low =3D 1; + $high =3D rand(0xffffffff); + } + + for (my $i =3D 1; $i < $precision; $i++) { + if ($randomize_low) { + $low =3D rand(0xffffffff); + } + insn32($low); + } + insn32($high); +} + +sub write_random_riscv64_fpdata() +{ + # load floating point registers + my $align =3D 16; + my $datalen =3D 32 * 8 + $align; + write_pc_adr(10, (4 * 4) + ($align - 1)); # insn 1 + write_align_reg(10, $align); # insn 2 + write_jump_fwd($datalen + 4); # insn 3 + + # align safety + for (my $i =3D 0; $i < ($align / 4); $i++) { + insn32(rand(0xffffffff)); + } + + # Todo: As the x10 aligned, it won't be the base address of + # the interesting numbers. + for (my $rt =3D 0; $rt <=3D 31; $rt++) { + write_random_fpreg_var(2); # double + } + + for (my ($rt, $imm) =3D (0, 0); $rt < 32; $rt++) { + # fld rt, x10, imm + insn32(0x00003007 | ($imm << 20) | (10 << 15) | ($rt << 7)); + $imm +=3D 8; + } +} + +sub write_random_register_data($) +{ + my ($fp_enabled) =3D @_; + + if ($fp_enabled) { + # load floating point + write_random_riscv64_fpdata(); + } + + # general purpose registers + for (my $i =3D 1; $i < 32; $i++) { + if ($i !=3D 2 && $i !=3D 3 && $i!=3D 4) { + # TODO full 64 bit pattern instead of 32 + write_mov_ri($i, rand(0xffffffff)); + } + } + write_risuop($OP_COMPARE); +} + +# put PC + offset into a register. +# this must emit an instruction of 8 bytes. +sub write_pc_adr($$) +{ + my ($rd, $imm) =3D @_; + + # auipc rd, 0 + # addi rd, rd, imm + insn32(0x00000017 | $rd << 7); + insn32(0x00000013 | $imm << 20 | $rd << 15 | $rd << 7); +} + +# clear bits in register to satisfy alignment. +# Must use exactly 4 instruction-bytes +sub write_align_reg($$) +{ + my ($rd, $align) =3D @_; + my $imm =3D (-$align) & 0xfff; + die "bad alignment!" if ($align < 2); + + # andi rd, rd, ~(align - 1) + insn32(0x00007013 | $imm << 20 | $rd << 15 | $rd << 7); +} + +# jump ahead of n bytes starting from next instruction +sub write_jump_fwd($) +{ + my ($len) =3D @_; + + # 31 30 21 20 19 12 11 7 6 0 + # imm[20] imm[10:1] imm[11] imm[19:12] rd opcode + # 1 10 1 8 5 7 + # offset[20:1] dest JAL + my ($imm20, $imm1, $imm11, $imm12) =3D (($len & 0x100000) >> 20, ($len= & 0x7fe) >> 1, + ($len & 0x800) >> 11, ($len & 0x= ff000) >> 12); + + # jal x0, len + insn32(0x0000006f | $imm20 << 31 | $imm1 << 21 | $imm11 << 20 | + $imm12 << 12); +} + +sub write_memblock_setup() +{ + # Write code which sets up the memory block for loads and stores. + # We set r0 to point to a block of 16K length + # of random data, aligned to the maximum desired alignment. + + my $align =3D $MAXALIGN; + my $datalen =3D 16384 + $align; + if (($align > 255) || !is_pow_of_2($align) || $align < 4) { + die "bad alignment!"; + } + + # set x10 to (datablock + (align-1)) & ~(align-1) + # datablock is at PC + (4 * 5 instructions) =3D PC + 20 + write_pc_adr(10, (4 * 5) + ($align - 1)); # insn 1 + write_align_reg(10, $align); # insn 2 + write_risuop($OP_SETMEMBLOCK); # insn 3 + write_jump_fwd($datalen + 4); # insn 4 + + for (my $i =3D 0; $i < $datalen / 4; $i++) { + insn32(rand(0xffffffff)); + } + # next: +} + +# Functions used in memory blocks to handle addressing modes. +# These all have the same basic API: they get called with parameters +# corresponding to the interesting fields of the instruction, +# and should generate code to set up the base register to be +# valid. They must return the register number of the base register. +# The last (array) parameter lists the registers which are trashed +# by the instruction (ie which are the targets of the load). +# This is used to avoid problems when the base reg is a load target. + +# Global used to communicate between align(x) and reg() etc. +my $alignment_restriction; + +sub align($) +{ + my ($a) =3D @_; + if (!is_pow_of_2($a) || ($a < 0) || ($a > $MAXALIGN)) { + die "bad align() value $a\n"; + } + $alignment_restriction =3D $a; +} + +sub write_get_offset() +{ + # Emit code to get a random offset within the memory block, of the + # right alignment, into r0 + # We require the offset to not be within 256 bytes of either + # end, to (more than) allow for the worst case data transfer, which is + # 16 * 64 bit regs + my $offset =3D (rand(16384 - 8192) + 4096) & ~($alignment_restriction = - 1); + write_mov_ri(10, $offset); + write_risuop($OP_GETMEMBLOCK); +} + +sub reg($@) +{ + my ($base, @trashed) =3D @_; + write_get_offset(); + # Now x10 is the address we want to do the access to, + # so just move it into the basereg + if ($base !=3D 10) { + write_mov_rr($base, 10); + write_mov_ri(10, 0); + } + if (grep $_ =3D=3D $base, @trashed) { + return -1; + } + return $base; +} + +sub reg_plus_imm($$@) +{ + # Handle reg + immediate addressing mode + my ($base, $imm, @trashed) =3D @_; + if ($imm =3D=3D 0) { + return reg($base, @trashed); + } + + write_get_offset(); + # Now x10 is the address we want to do the access to, + # so set the basereg by doing the inverse of the + # addressing mode calculation, ie base =3D x10 - imm + # We could do this more cleverly with a sub immediate. + if ($base !=3D 10) { + write_mov_ri($base, $imm); + write_sub_rrr($base, 10, $base); + # Clear x10 to avoid register compare mismatches + # when the memory block location differs between machines. + write_mov_ri(10, 0); + } else { + # We borrow x11 as a temporary (not a problem + # as long as we don't leave anything in a register + # which depends on the location of the memory block) + write_mov_ri(11, $imm); + write_sub_rrr($base, 10, 11); + } + if (grep $_ =3D=3D $base, @trashed) { + return -1; + } + return $base; +} + +sub gen_one_insn($) +{ + # Given an instruction-details array, generate an instruction + my $constraintfailures =3D 0; + + INSN: while(1) { + my ($rec) =3D @_; + my $insn =3D int(rand(0xffffffff)); + my $insnname =3D $rec->{name}; + my $insnwidth =3D $rec->{width}; + my $fixedbits =3D $rec->{fixedbits}; + my $fixedbitmask =3D $rec->{fixedbitmask}; + my $constraint =3D $rec->{blocks}{"constraints"}; + my $memblock =3D $rec->{blocks}{"memory"}; + + $insn &=3D ~$fixedbitmask; + $insn |=3D $fixedbits; + + if (defined $constraint) { + # user-specified constraint: evaluate in an environment + # with variables set corresponding to the variable fields. + my $v =3D eval_with_fields($insnname, $insn, $rec, "constraint= s", $constraint); + if (!$v) { + $constraintfailures++; + if ($constraintfailures > 10000) { + print "10000 consecutive constraint failures for $insn= name constraints string:\n$constraint\n"; + exit (1); + } + next INSN; + } + } + + # OK, we got a good one + $constraintfailures =3D 0; + + my $basereg; + + if (defined $memblock) { + # This is a load or store. We simply evaluate the block, + # which is expected to be a call to a function which emits + # the code to set up the base register and returns the + # number of the base register. + # we use 16 for riscv64, although often unnecessary and overki= ll. + align(16); + $basereg =3D eval_with_fields($insnname, $insn, $rec, "memory"= , $memblock); + } + + insn32($insn); + + if (defined $memblock) { + # Clean up following a memory access instruction: + # we need to turn the (possibly written-back) basereg + # into an offset from the base of the memory block, + # to avoid making register values depend on memory layout. + # $basereg -1 means the basereg was a target of a load + # (and so it doesn't contain a memory address after the op) + if ($basereg !=3D -1) { + write_mov_ri($basereg, 0); + } + } + return; + } +} + +sub write_risuop($) +{ + # instr with bits (6:0) =3D=3D 1 1 0 1 0 1 1 are UNALLOCATED + my ($op) =3D @_; + insn32(0x0000006b | $op << 8); +} + +sub write_test_code($) +{ + my ($params) =3D @_; + + my $numinsns =3D $params->{ 'numinsns' }; + my $fp_enabled =3D $params->{ 'fp_enabled' }; + my $outfile =3D $params->{ 'outfile' }; + + my %insn_details =3D %{ $params->{ 'details' } }; + my @keys =3D @{ $params->{ 'keys' } }; + + print "Enter write code", "\n"; + open_bin($outfile); + + # TODO better random number generator? + srand(0); + + print "Generating code using patterns: @keys...\n"; + progress_start(78, $numinsns); + + if (grep { defined($insn_details{$_}->{blocks}->{"memory"}) } @keys) { + write_memblock_setup(); + } + + # memblock setup doesn't clean its registers, so this must come afterw= ards. + write_random_register_data($fp_enabled); + + for my $i (1..$numinsns) { + my $insn_enc =3D $keys[int rand (@keys)]; + #dump_insn_details($insn_enc, $insn_details{$insn_enc}); + gen_one_insn($insn_details{$insn_enc}); + write_risuop($OP_COMPARE); + # Rewrite the registers periodically. This avoids the tendency + # for the VFP registers to decay to NaNs and zeroes. + if ($periodic_reg_random && ($i % 100) =3D=3D 0) { + write_random_register_data($fp_enabled); + } + progress_update($i); + } + write_risuop($OP_TESTEND); + progress_end(); + close_bin(); +} + +1; --=20 2.23.0 From nobody Fri Nov 14 13:38:15 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1588231489; cv=none; d=zohomail.com; s=zohoarc; b=KXXauu+nzL4FY+Ai/8dW2UkWn7IFDj8NG7KJn25ic3GcYbB3jEtuLUcGEo8E1NwLFI22eaPZlrLKF1H5Vk988+sKTDjAbOL0yl5DI0hcFB1OudDMxmJR9nwPwpwrmz78FwHF5MjSkBgpQbSZvZcB+wS5pXOjyYOm0GHfO5LZlrg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588231489; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3mmgWog63/yKJ22ZBYOtvWMJXhBOGfLKBvQ414OeVhE=; b=FLQ/sf48uJnnk/ef103zneHiCQSQLcy7BQbFJxXqoXYntAAAVOunCuVP5juorRquwvCJ9f7XD4bURf4jqXIcJpgkNEZGsNxn8ZClE3PISoMm8jq64UlP6Hu5xb8LX/F3m3rNJvSEa5F+VCqR9PLr94mmB3VlbCrj/giovt8RMtE= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1588231489155131.21686000272678; Thu, 30 Apr 2020 00:24:49 -0700 (PDT) Received: from localhost ([::1]:52242 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU3Yt-0006WI-IP for importer@patchew.org; Thu, 30 Apr 2020 03:24:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34256) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU3XW-0004Zm-Os for qemu-devel@nongnu.org; Thu, 30 Apr 2020 03:23:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.90_1) (envelope-from ) id 1jU3W7-0006Y2-8i for qemu-devel@nongnu.org; Thu, 30 Apr 2020 03:23:22 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:53190) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jU3W6-0006Wn-Kj; Thu, 30 Apr 2020 03:21:54 -0400 Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.HQfovas_1588231302) by smtp.aliyun-inc.com(10.147.40.7); Thu, 30 Apr 2020 15:21:44 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.1414109|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0183836-0.00115908-0.980457; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03300; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.HQfovas_1588231302; From: LIU Zhiwei To: peter.maydell@linaro.org Subject: [RFC PATCH 3/8] riscv: Define riscv struct reginfo Date: Thu, 30 Apr 2020 15:21:34 +0800 Message-Id: <20200430072139.4602-4-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200430072139.4602-1-zhiwei_liu@c-sky.com> References: <20200430072139.4602-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/30 03:21:44 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Received-From: 121.197.200.217 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com, wenmeng_zhang@c-sky.com, palmer@dabbelt.com, alistair23@gmail.com, alex.bennee@linaro.org, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei --- risu_reginfo_riscv64.h | 29 +++++++++++++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 risu_reginfo_riscv64.h diff --git a/risu_reginfo_riscv64.h b/risu_reginfo_riscv64.h new file mode 100644 index 0000000..7d365a8 --- /dev/null +++ b/risu_reginfo_riscv64.h @@ -0,0 +1,29 @@ +/*************************************************************************= ***** + * Copyright (c) 2020 PingTouGe Semiconductor + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * which accompanies this distribution, and is available at + * http://www.eclipse.org/legal/epl-v10.html + * + * Contributors: + * LIU Zhiwei(PingTouGe) - initial implementation + * based on Peter Maydell's risu_arm.c + *************************************************************************= ****/ + +#ifndef RISU_REGINFO_RISCV64_H +#define RISU_REGINFO_RISCV64_H + +struct reginfo { + uint64_t fault_address; + uint64_t regs[32]; + uint64_t fregs[32]; + uint64_t sp; + uint64_t pc; + uint32_t flags; + uint32_t faulting_insn; + + /* FP */ + uint32_t fcsr; +}; + +#endif /* RISU_REGINFO_RISCV64_H */ --=20 2.23.0 From nobody Fri Nov 14 13:38:15 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Thu, 30 Apr 2020 00:26:45 -0700 (PDT) Received: from localhost ([::1]:33288 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU3am-0001tE-7A for importer@patchew.org; Thu, 30 Apr 2020 03:26:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34278) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU3XZ-0004ct-QN for qemu-devel@nongnu.org; Thu, 30 Apr 2020 03:23:49 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.90_1) (envelope-from ) id 1jU3W7-0006Yg-T2 for qemu-devel@nongnu.org; Thu, 30 Apr 2020 03:23:25 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:42105) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jU3W6-0006WV-Tx; Thu, 30 Apr 2020 03:21:55 -0400 Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.HQfovas_1588231302) by smtp.aliyun-inc.com(10.147.40.7); Thu, 30 Apr 2020 15:21:45 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436398|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.0951211-0.00075412-0.904125; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03295; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.HQfovas_1588231302; From: LIU Zhiwei To: peter.maydell@linaro.org Subject: [RFC PATCH 4/8] riscv: Implement payload load interfaces Date: Thu, 30 Apr 2020 15:21:35 +0800 Message-Id: <20200430072139.4602-5-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200430072139.4602-1-zhiwei_liu@c-sky.com> References: <20200430072139.4602-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/30 03:21:44 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Received-From: 121.197.200.217 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com, wenmeng_zhang@c-sky.com, palmer@dabbelt.com, alistair23@gmail.com, alex.bennee@linaro.org, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei --- risu_reginfo_riscv64.c | 134 +++++++++++++++++++++++++++++++++++++++++ risu_riscv64.c | 47 +++++++++++++++ 2 files changed, 181 insertions(+) create mode 100644 risu_reginfo_riscv64.c create mode 100644 risu_riscv64.c diff --git a/risu_reginfo_riscv64.c b/risu_reginfo_riscv64.c new file mode 100644 index 0000000..cfa9889 --- /dev/null +++ b/risu_reginfo_riscv64.c @@ -0,0 +1,134 @@ +/*************************************************************************= ***** + * Copyright (c) 2020 PingTouGe Semiconductor + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * which accompanies this distribution, and is available at + * http://www.eclipse.org/legal/epl-v10.html + * + * Contributors: + * LIU Zhiwei (PingTouGe) - initial implementation + * based on Peter Maydell's risu_arm.c + *************************************************************************= ****/ + +#include +#include +#include +#include /* for FPSIMD_MAGIC */ +#include +#include +#include +#include +#include +#include + +#include "risu.h" +#include "risu_reginfo_riscv64.h" + +const struct option * const arch_long_opts; +const char * const arch_extra_help; + +void process_arch_opt(int opt, const char *arg) +{ + abort(); +} + +const int reginfo_size(void) +{ + return sizeof(struct reginfo); +} + +/* reginfo_init: initialize with a ucontext */ +void reginfo_init(struct reginfo *ri, ucontext_t *uc) +{ + int i; + union __riscv_mc_fp_state *fp; + /* necessary to be able to compare with memcmp later */ + memset(ri, 0, sizeof(*ri)); + + for (i =3D 0; i < 32; i++) { + ri->regs[i] =3D uc->uc_mcontext.__gregs[i]; + } + + ri->sp =3D 0xdeadbeefdeadbeef; + ri->regs[2] =3D 0xdeadbeefdeadbeef; + ri->regs[3] =3D 0xdeadbeefdeadbeef; + ri->regs[4] =3D 0xdeadbeefdeadbeef; + ri->pc =3D uc->uc_mcontext.__gregs[0] - image_start_address; + ri->faulting_insn =3D *((uint32_t *) uc->uc_mcontext.__gregs[0]); + fp =3D &uc->uc_mcontext.__fpregs; + ri->fcsr =3D fp->__d.__fcsr; + + for (i =3D 0; i < 32; i++) { + ri->fregs[i] =3D fp->__d.__f[i]; + } +} + +/* reginfo_is_eq: compare the reginfo structs, returns nonzero if equal */ +int reginfo_is_eq(struct reginfo *r1, struct reginfo *r2) +{ + return memcmp(r1, r2, reginfo_size()) =3D=3D 0; +} + +/* reginfo_dump: print state to a stream, returns nonzero on success */ +int reginfo_dump(struct reginfo *ri, FILE * f) +{ + int i; + fprintf(f, " faulting insn %08x\n", ri->faulting_insn); + + for (i =3D 1; i < 32; i++) { + fprintf(f, " X%-2d : %016" PRIx64 "\n", i, ri->regs[i]); + } + + fprintf(f, " sp : %016" PRIx64 "\n", ri->sp); + fprintf(f, " pc : %016" PRIx64 "\n", ri->pc); + fprintf(f, " fcsr : %08x\n", ri->fcsr); + + for (i =3D 0; i < 32; i++) { + fprintf(f, " F%-2d : %016" PRIx64 "\n", i, ri->fregs[i]); + } + + return !ferror(f); +} + +/* reginfo_dump_mismatch: print mismatch details to a stream, ret nonzero= =3Dok */ +int reginfo_dump_mismatch(struct reginfo *m, struct reginfo *a, FILE * f) +{ + int i; + fprintf(f, "mismatch detail (master : apprentice):\n"); + if (m->faulting_insn !=3D a->faulting_insn) { + fprintf(f, " faulting insn mismatch %08x vs %08x\n", + m->faulting_insn, a->faulting_insn); + } + for (i =3D 1; i < 32; i++) { + if (m->regs[i] !=3D a->regs[i]) { + fprintf(f, " X%-2d : %016" PRIx64 " vs %016" PRIx64 "\n", + i, m->regs[i], a->regs[i]); + } + } + + if (m->sp !=3D a->sp) { + fprintf(f, " sp : %016" PRIx64 " vs %016" PRIx64 "\n", + m->sp, a->sp); + } + + if (m->pc !=3D a->pc) { + fprintf(f, " pc : %016" PRIx64 " vs %016" PRIx64 "\n", + m->pc, a->pc); + } + + if (m->fcsr !=3D a->fcsr) { + fprintf(f, " fcsr : %08x vs %08x\n", m->fcsr, a->fcsr); + } + + for (i =3D 0; i < 32; i++) { + if (m->fregs[i] !=3D a->fregs[i]) { + fprintf(f, " F%-2d : " + "%016" PRIx64 " vs " + "%016" PRIx64 "\n", i, + (uint64_t) m->fregs[i], + (uint64_t) a->fregs[i]); + } + } + + return !ferror(f); +} diff --git a/risu_riscv64.c b/risu_riscv64.c new file mode 100644 index 0000000..f742a40 --- /dev/null +++ b/risu_riscv64.c @@ -0,0 +1,47 @@ +/*************************************************************************= ***** + * Copyright (c) 2020 PingTouGe Semiconductor + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * which accompanies this distribution, and is available at + * http://www.eclipse.org/legal/epl-v10.html + * + * Contributors: + * LIU Zhiwei(Linaro) - initial implementation + * based on Peter Maydell's risu_arm.c + *************************************************************************= ****/ + +#include "risu.h" + +void advance_pc(void *vuc) +{ + ucontext_t *uc =3D vuc; + uc->uc_mcontext.__gregs[0] +=3D 4; +} + +void set_ucontext_paramreg(void *vuc, uint64_t value) +{ + ucontext_t *uc =3D vuc; + uc->uc_mcontext.__gregs[10] =3D value; +} + +uint64_t get_reginfo_paramreg(struct reginfo *ri) +{ + return ri->regs[10]; +} + +int get_risuop(struct reginfo *ri) +{ + /* Return the risuop we have been asked to do + * (or -1 if this was a SIGILL for a non-risuop insn) + */ + uint32_t insn =3D ri->faulting_insn; + uint32_t op =3D (insn & 0xf00) >> 8; + uint32_t key =3D insn & ~0xf00; + uint32_t risukey =3D 0x0000006b; + return (key !=3D risukey) ? -1 : op; +} + +uintptr_t get_pc(struct reginfo *ri) +{ + return ri->pc; +} --=20 2.23.0 From nobody Fri Nov 14 13:38:15 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1588231486; cv=none; d=zohomail.com; s=zohoarc; b=SLaD5gGLOBjrJrhshyprNALdskW8jAYMNR9Kb9aX/zlO3PRIL8m25DXmIbGRugz0ZjM4kyEI7SuS7KVT03gQ0PUq0WrwF0UTI+s+xCusQVT+2UNcduK1O21n/DmY6y37r89TmN0g43hPYMFhehJxgfwdI4XvadVm0e0EfVSYD1g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588231486; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=aPvoo3wssN6qUEU5tSPBciuv5HXzmmaaaq6gHBJcrNk=; b=NE30uOMDebFIuf3BDiQGYM5Ai/wpjEAHx81fQmHSXDp51cUKo8SErY3duI4rmE57IVK3yePwdsnatAXK+u/bS1mntQO+ZMZ0hbz1RHnkuL03N5TcTMUAQcKhpYavDwiaexMoQG8dXPrAdTFdj5EDozH077B7+Y7SfZuJ+3oC6mo= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1588231486452170.533775436243; Thu, 30 Apr 2020 00:24:46 -0700 (PDT) Received: from localhost ([::1]:52002 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU3Yq-0006QX-FH for importer@patchew.org; Thu, 30 Apr 2020 03:24:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34248) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jU3XW-0004Y0-1L for qemu-devel@nongnu.org; Thu, 30 Apr 2020 03:23:39 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.90_1) (envelope-from ) id 1jU3W6-0006Xr-SS for qemu-devel@nongnu.org; Thu, 30 Apr 2020 03:23:21 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:42976) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jU3W6-0006Wj-6F; Thu, 30 Apr 2020 03:21:54 -0400 Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.HQfovas_1588231302) by smtp.aliyun-inc.com(10.147.40.7); Thu, 30 Apr 2020 15:21:45 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07436369|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_regular_dialog|0.17134-0.00013087-0.828529; FP=0|0|0|0|0|-1|-1|-1; HT=e01a16378; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.HQfovas_1588231302; From: LIU Zhiwei To: peter.maydell@linaro.org Subject: [RFC PATCH 5/8] riscv: Add standard test case Date: Thu, 30 Apr 2020 15:21:36 +0800 Message-Id: <20200430072139.4602-6-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200430072139.4602-1-zhiwei_liu@c-sky.com> References: <20200430072139.4602-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/30 03:21:44 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Received-From: 121.197.200.217 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com, wenmeng_zhang@c-sky.com, palmer@dabbelt.com, alistair23@gmail.com, alex.bennee@linaro.org, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- test_riscv64.s | 85 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 85 insertions(+) create mode 100644 test_riscv64.s diff --git a/test_riscv64.s b/test_riscv64.s new file mode 100644 index 0000000..5a8279f --- /dev/null +++ b/test_riscv64.s @@ -0,0 +1,85 @@ +/*************************************************************************= **** + * Copyright (c) 2020 PingTouGe Semiconductor + * All rights reserved. This program and the accompanying materials + * are made available under the terms of the Eclipse Public License v1.0 + * which accompanies this distribution, and is available at + * http://www.eclipse.org/legal/epl-v10.html + * + * Contributors: + * LIU Zhiwei (PingTouGe) - initial implementation + * based on test_arm.s by Peter Maydell + *************************************************************************= ****/ + +/* Initialise the gp regs */ +li x1, 1 +#li x2, 2 # stack pointer +#li x3, 3 # global pointer +#li x4, 4 # thread pointer +li x5, 5 +li x6, 6 +li x7, 7 +li x8, 8 +li x9, 9 +li x10, 10 +li x11, 11 +li x12, 12 +li x13, 13 +li x14, 14 +li x15, 15 +li x16, 16 +li x17, 17 +li x18, 18 +li x19, 19 +li x20, 20 +li x21, 21 +li x22, 22 +li x23, 23 +li x24, 24 +li x25, 25 +li x26, 26 +li x27, 27 +li x28, 28 +li x29, 29 +li x30, 30 +li x31, 30 + +/* Initialise the fp regs */ +fcvt.d.lu f0, x0 +fcvt.d.lu f1, x1 +#fcvt.d.lu f2, x2 +fcvt.d.lu f3, x3 +fcvt.d.lu f4, x4 +fcvt.d.lu f5, x5 +fcvt.d.lu f6, x6 +fcvt.d.lu f7, x7 +fcvt.d.lu f8, x8 +fcvt.d.lu f9, x9 +fcvt.d.lu f10, x10 +fcvt.d.lu f11, x11 +fcvt.d.lu f12, x12 +fcvt.d.lu f13, x13 +fcvt.d.lu f14, x14 +fcvt.d.lu f15, x15 +fcvt.d.lu f16, x16 +fcvt.d.lu f17, x17 +fcvt.d.lu f18, x18 +fcvt.d.lu f19, x19 +fcvt.d.lu f20, x20 +fcvt.d.lu f21, x21 +fcvt.d.lu f22, x22 +fcvt.d.lu f23, x23 +fcvt.d.lu f24, x24 +fcvt.d.lu f25, x25 +fcvt.d.lu f26, x26 +fcvt.d.lu f27, x27 +fcvt.d.lu f28, x28 +fcvt.d.lu f29, x29 +fcvt.d.lu f30, x30 +fcvt.d.lu f31, x31 + +/* do compare. + * The manual says instr with bits (6:0) =3D=3D 1 1 0 1 0 1 1 are UNALLOCA= TED + */ +.int 0x0000006b +/* exit test */ +.int 0x0000016b --=20 2.23.0 From nobody Fri Nov 14 13:38:15 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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BC=0.1275953|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_alarm|0.0499706-0.00109699-0.948932; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03299; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.HQfovas_1588231302; From: LIU Zhiwei To: peter.maydell@linaro.org Subject: [RFC PATCH 6/8] riscv: Add configure script Date: Thu, 30 Apr 2020 15:21:37 +0800 Message-Id: <20200430072139.4602-7-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200430072139.4602-1-zhiwei_liu@c-sky.com> References: <20200430072139.4602-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/30 03:21:44 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Received-From: 121.197.200.217 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com, wenmeng_zhang@c-sky.com, palmer@dabbelt.com, alistair23@gmail.com, alex.bennee@linaro.org, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" For RV64 risu, make CFLAGS=3D"-march=3Drv64g" Signed-off-by: LIU Zhiwei --- configure | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/configure b/configure index ca2d7db..5c9e967 100755 --- a/configure +++ b/configure @@ -58,6 +58,8 @@ guess_arch() { ARCH=3D"m68k" elif check_define __powerpc64__ ; then ARCH=3D"ppc64" + elif check_define __riscv ; then + ARCH=3D"riscv64" else echo "This cpu is not supported by risu. Try -h. " >&2 exit 1 @@ -139,7 +141,7 @@ Some influential environment variables: prefixed with the given string. =20 ARCH force target architecture instead of trying to detect it. - Valid values=3D[arm|aarch64|ppc64|ppc64le|m68k] + Valid values=3D[arm|aarch64|ppc64|ppc64le|m68k|riscv64] =20 CC C compiler command CFLAGS C compiler flags --=20 2.23.0 From nobody Fri Nov 14 13:38:15 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1588231496; cv=none; d=zohomail.com; s=zohoarc; b=Jvnx+Vb0s8dF998y/tk2L9VqbO1yrohAneZEo8P3QATmFoKUTxfbXwGsy4fbaOao4Oq66JL6GECIkSBU181jJCEY+bCeZW/vx49csDJ8rWpYEfqWYYskMR4FI5NM9Z9aenCVnqEMW4jL2yhMRCRIHyhxXtfSN/MUv8QSu08d6Ow= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1588231496; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Thu, 30 Apr 2020 03:23:24 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:41364) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jU3W7-0006Wy-2I; Thu, 30 Apr 2020 03:21:55 -0400 Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.HQfovas_1588231302) by smtp.aliyun-inc.com(10.147.40.7); Thu, 30 Apr 2020 15:21:46 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07439117|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.371727-0.00209313-0.62618; FP=0|0|0|0|0|-1|-1|-1; HT=e01l07381; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.HQfovas_1588231302; From: LIU Zhiwei To: peter.maydell@linaro.org Subject: [RFC PATCH 7/8] riscv: Add RV64M instructions description Date: Thu, 30 Apr 2020 15:21:38 +0800 Message-Id: <20200430072139.4602-8-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200430072139.4602-1-zhiwei_liu@c-sky.com> References: <20200430072139.4602-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/30 03:21:44 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Received-From: 121.197.200.217 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com, wenmeng_zhang@c-sky.com, palmer@dabbelt.com, alistair23@gmail.com, alex.bennee@linaro.org, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei Reviewed-by: Richard Henderson --- riscv64.risu | 43 +++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/riscv64.risu b/riscv64.risu index 98141ab..f006dc8 100644 --- a/riscv64.risu +++ b/riscv64.risu @@ -139,3 +139,46 @@ SRLW RISCV 0000000 rs2:5 rs1:5 101 rd:5 0011011 \ =20 SRAW RISCV 0100000 rs2:5 rs1:5 101 rd:5 0011011 \ !constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 } + +@RV64M + +MUL RISCV 0000001 rs2:5 rs1:5 000 rd:5 0110011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 && $r= s2 !=3D 2 } + +MULH RISCV 0000001 rs2:5 rs1:5 001 rd:5 0110011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 && $r= s2 !=3D 2 } + +MULHSU RISCV 0000001 rs2:5 rs1:5 010 rd:5 0110011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 && $r= s2 !=3D 2 } + +MULHU RISCV 0000001 rs2:5 rs1:5 011 rd:5 0110011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 && $r= s2 !=3D 2 } + +DIV RISCV 0000001 rs2:5 rs1:5 100 rd:5 0110011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 && $r= s2 !=3D 2 } + +DIVU RISCV 0000001 rs2:5 rs1:5 101 rd:5 0110011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 && $r= s2 !=3D 2 } + +REM RISCV 0000001 rs2:5 rs1:5 110 rd:5 0110011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 && $r= s2 !=3D 2 } + +REMU RISCV 0000001 rs2:5 rs1:5 111 rd:5 0110011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 && $r= s2 !=3D 2 } + +MULW RISCV 0000001 rs2:5 rs1:5 000 rd:5 0111011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 && $r= s2 !=3D 2 } + +DIVW RISCV 0000001 rs2:5 rs1:5 100 rd:5 0111011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 && $r= s2 !=3D 2 } + +DIVUW RISCV 0000001 rs2:5 rs1:5 101 rd:5 0111011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 && $r= s2 !=3D 2 } + +REMW RISCV 0000001 rs2:5 rs1:5 110 rd:5 0111011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 && $r= s2 !=3D 2 } + +REMUW RISCV 0000001 rs2:5 rs1:5 111 rd:5 0111011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 && $r= s2 !=3D 2 } + + --=20 2.23.0 From nobody Fri Nov 14 13:38:15 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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BC=0.07436297|-1; CH=green; DM=|CONTINUE|false|; DS=CONTINUE|ham_system_inform|0.00411137-0.00097916-0.994909; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03308; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=10; RT=10; SR=0; TI=SMTPD_---.HQfovas_1588231302; From: LIU Zhiwei To: peter.maydell@linaro.org Subject: [RFC PATCH 8/8] riscv: Add RV64F instructions description Date: Thu, 30 Apr 2020 15:21:39 +0800 Message-Id: <20200430072139.4602-9-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200430072139.4602-1-zhiwei_liu@c-sky.com> References: <20200430072139.4602-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=121.197.200.217; envelope-from=zhiwei_liu@c-sky.com; helo=smtp2200-217.mail.aliyun.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/30 03:21:44 X-ACL-Warn: Detected OS = Linux 3.x [generic] [fuzzy] X-Received-From: 121.197.200.217 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, richard.henderson@linaro.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com, wenmeng_zhang@c-sky.com, palmer@dabbelt.com, alistair23@gmail.com, alex.bennee@linaro.org, LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Signed-off-by: LIU Zhiwei --- riscv64.risu | 78 ++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 78 insertions(+) diff --git a/riscv64.risu b/riscv64.risu index f006dc8..0b81dfb 100644 --- a/riscv64.risu +++ b/riscv64.risu @@ -181,4 +181,82 @@ REMW RISCV 0000001 rs2:5 rs1:5 110 rd:5 0111011 \ REMUW RISCV 0000001 rs2:5 rs1:5 111 rd:5 0111011 \ !constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rs1 !=3D 2 && $r= s2 !=3D 2 } =20 +@RV64F =20 +FLW RISCV imm:12 rs1:5 010 rd:5 0000111 \ +!constraints { $rs1 !=3D 0 && $rs1 !=3D 2 && $rs1 !=3D3 && $rs1 !=3D 4 } \ +!memory { align(4); reg_plus_imm($rs1, sextract($imm, 12)); } + +FSW RISCV imm5:7 rs2:5 rs1:5 010 imm:5 0000111 \ +!constraints { $rs1 !=3D 0 && $rs1 !=3D 2 && $rs1 !=3D3 && $rs1 !=3D 4 && = $rs2 !=3D 2} \ +!memory { align(4); reg_plus_imm($rs1, sextract($imm5 << 5 | $imm, 12)); } + +FMADD_S RISCV rs3:5 00 rs2:5 rs1:5 rm:3 rd:5 1000011 + +FMSUB_S RISCV rs3:5 00 rs2:5 rs1:5 rm:3 rd:5 1000111 + +FNMSUB_S RISCV rs3:5 00 rs2:5 rs1:5 rm:3 rd:5 1001011 + +FNMADD_S RISCV rs3:5 00 rs2:5 rs1:5 rm:3 rd:5 1001111 + +FADD_S RISCV 0000000 rs2:5 rs1:5 rm:3 rd:5 1010011 + +FSUB_S RISCV 0000100 rs2:5 rs1:5 rm:3 rd:5 1010011 + +FMUL_S RISCV 0001000 rs2:5 rs1:5 rm:3 rd:5 1010011 + +FDIV_S RISCV 0001100 rs2:5 rs1:5 rm:3 rd:5 1010011 + +FSQRT_S RISCV 0101100 00000 rs1:5 rm:3 rd:5 1010011 + +FSGNJ_S RISCV 0010000 rs2:5 rs1:5 000 rd:5 1010011 + +FSGNJN_S RISCV 0010000 rs2:5 rs1:5 001 rd:5 1010011 + +FSGNJX_S RISCV 0010000 rs2:5 rs1:5 010 rd:5 1010011 + +FMIN_S RISCV 0010100 rs2:5 rs1:5 000 rd:5 1010011 + +FMAX_S RISCV 0010100 rs2:5 rs1:5 001 rd:5 1010011 + +FCVT_W_S RISCV 1100000 00000 rs1:5 rm:3 rd:5 1010011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 } + +FCVT_WU_S RISCV 1100000 00001 rs1:5 rm:3 rd:5 1010011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 } + +FMV_X_W RISCV 1110000 00000 rs1:5 rm:3 rd:5 1010011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 } + +FEQ_S RISCV 1010000 rs2:5 rs1:5 010 rd:5 1010011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 } + +FLT_S RISCV 1010000 rs2:5 rs1:5 001 rd:5 1010011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 } + +FLE_S RISCV 1010000 rs2:5 rs1:5 000 rd:5 1010011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 } + +FCLASS_S RISCV 1110000 00000 rs1:5 001 rd:5 1010011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 } + +FCVT_S_W RISCV 1101000 00000 rs1:5 rm:3 rd:5 1010011 \ +!constraints { $rs1 !=3D 2 } + +FCVT_S_WU RISCV 1101000 00001 rs1:5 rm:3 rd:5 1010011 \ +!constraints { $rs1 !=3D 2 } + +FMV_W_X RISCV 1111000 00000 rs1:5 000 rd:5 1010011 \ +!constraints { $rs1 !=3D 2 } + +FCVT_L_S RISCV 1100000 00010 rs1:5 rm:3 rd:5 1010011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rm !=3D 6 && $rm= !=3D 5 } + +FCVT_LU_S RISCV 1100000 00011 rs1:5 rm:3 rd:5 1010011 \ +!constraints { $rd !=3D 2 && $rd !=3D 3 && $rd !=3D 4 && $rm !=3D 6 && $rm= !=3D 5 } + +FCVT_S_L RISCV 1101000 00010 rs1:5 rm:3 rd:5 1010011 \ +!constraints { $rs1 !=3D 2 && $rm !=3D 6 && $rm !=3D 5 } + +FCVT_S_LU RISCV 1101000 00011 rs1:5 rm:3 rd:5 1010011 \ +!constraints { $rs1 !=3D 2 && $rm !=3D 6 && $rm !=3D 5 } --=20 2.23.0