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IronPort-SDR: sn1OlBLTXEzHxB5o+lRfZjlw9sqOCi632DUimphyfWuZX6+2Ez7oYO5qW5yk6FvP5/HtmtHhwk 7tZiFjyoQXs9QyuV0yQT5v+wzkjII1wGhp0KI7d8ZVNsMs2DH/epmCB6YFyGuoOclop3Hf7+s+ YSwuFFpz0NbDvulZO1hL9PAoaJwcRN6SKGfx2AmOlnCKm2s3MI8QIuwNsH5y9r7Rh0ZwQj0C7q iPCVkvoRyJvI0g3CxnmdqAkl/Bj91a7MBZ7VX/XX/QPqNjsxO7dYgLwTLd24b7vDxo1p+3JDrj AuE= X-IronPort-AV: E=Sophos;i="5.73,333,1583164800"; d="scan'208";a="136507033" IronPort-SDR: toGsanGXqjnwkB5s/kFbSnJuLDjV+ETwDSsycaPkfKQO+dHx/AVfBeWMkMa/sTUkuIZU/UKHZi GP9LQt7k5Lhao1ypr45q7kNjxL3EErpWY= IronPort-SDR: p+xBYG0V2x0r7UL7YqejYEwL0XAu726qpR8mw5NITv8vpGPKdV4plyk33ALfgsFtlqbiaV8XR7 QBLBvSrCccbg== WDCIronportException: Internal From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL v2 03/14] riscv/sifive_u: Add a serial property to the sifive_u machine Date: Wed, 29 Apr 2020 13:19:55 -0700 Message-Id: <20200429202006.775322-4-alistair.francis@wdc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200429202006.775322-1-alistair.francis@wdc.com> References: <20200429202006.775322-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=381fbd49e=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/29 16:28:37 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Received-From: 216.71.154.42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , palmerdabbelt@google.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Bin Meng At present the board serial number is hard-coded to 1, and passed to OTP model during initialization. Firmware (FSBL, U-Boot) uses the serial number to generate a unique MAC address for the on-chip ethernet controller. When multiple QEMU 'sifive_u' instances are created and connected to the same subnet, they all have the same MAC address hence it creates a unusable network. A new "serial" property is introduced to specify the board serial number. When not given, the default serial number 1 is used. Signed-off-by: Bin Meng Reviewed-by: Palmer Dabbelt Reviewed-by: Alistair Francis Message-Id: <1573916930-19068-1-git-send-email-bmeng.cn@gmail.com> [ Changed by AF: - Use the SoC's serial property to pass the info to the SoC - Fixup commit title - Rebase on file restructuring ] Signed-off-by: Alistair Francis --- hw/riscv/sifive_u.c | 20 ++++++++++++++++++++ include/hw/riscv/sifive_u.h | 1 + 2 files changed, 21 insertions(+) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 6e659e986f..8d0ee8b9c4 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -34,6 +34,7 @@ #include "qemu/log.h" #include "qemu/error-report.h" #include "qapi/error.h" +#include "qapi/visitor.h" #include "hw/boards.h" #include "hw/loader.h" #include "hw/sysbus.h" @@ -326,6 +327,8 @@ static void sifive_u_machine_init(MachineState *machine) object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), TYPE_RISCV_U_SOC, &error_abort, NULL); + object_property_set_uint(OBJECT(&s->soc), s->serial, "serial", + &error_abort); object_property_set_bool(OBJECT(&s->soc), true, "realized", &error_abort); =20 @@ -417,6 +420,18 @@ static void sifive_u_machine_set_start_in_flash(Object= *obj, bool value, Error * s->start_in_flash =3D value; } =20 +static void sifive_u_machine_get_serial(Object *obj, Visitor *v, const cha= r *name, + void *opaque, Error **errp) +{ + visit_type_uint32(v, name, (uint32_t *)opaque, errp); +} + +static void sifive_u_machine_set_serial(Object *obj, Visitor *v, const cha= r *name, + void *opaque, Error **errp) +{ + visit_type_uint32(v, name, (uint32_t *)opaque, errp); +} + static void sifive_u_machine_instance_init(Object *obj) { SiFiveUState *s =3D RISCV_U_MACHINE(obj); @@ -428,6 +443,11 @@ static void sifive_u_machine_instance_init(Object *obj) "Set on to tell QEMU's ROM to jump to " "flash. Otherwise QEMU will jump to DR= AM", NULL); + + s->serial =3D OTP_SERIAL; + object_property_add(obj, "serial", "uint32", sifive_u_machine_get_seri= al, + sifive_u_machine_set_serial, NULL, &s->serial, NUL= L); + object_property_set_description(obj, "serial", "Board serial number", = NULL); } =20 static void sifive_u_machine_class_init(ObjectClass *oc, void *data) diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index a2baa1de5f..16c297ec5f 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -61,6 +61,7 @@ typedef struct SiFiveUState { int fdt_size; =20 bool start_in_flash; + uint32_t serial; } SiFiveUState; =20 enum { --=20 2.26.2