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IronPort-SDR: kJV+q8TQPi/zRrBvEkHQrmpDMaTHczUxh2b1CGAiwaJ7adw1O1vmEM3DXCKTdG5k02NxQrMsF0 xjoqGSSSUUPq7+lpst0jLkbYlOU1p4RKLAsAO6G0nZ1mLM/qDlVFVaoZ8yvCEGakLM3SvCS57J yTZ1fgLVeYNy64/qWE8gZO8quO2pNF+uacOOo6DRXxU57Gnb1XzGeHGpJN7hh4CuvuVK9KtyNf LSc/qEmg/5DWhIGz4GXWLgGOnb2+MO+bhuQmM9KQp8SGSTetW1XY96PhMkiIj+lHG9gci2fS/f dFE= X-IronPort-AV: E=Sophos;i="5.73,333,1583164800"; d="scan'208";a="136507032" IronPort-SDR: fg8UYdKrF/sFsO573rKXxJ6u6BGgZQuHzP8E/gx2EJOINz0dThKqGQopGCGx8dXbL0kjsTQzN0 jx7nfnl/ib1jGlFUZC1H4qPvpNbucCX88= IronPort-SDR: P44cC5bmEGK/xynHV2iLMGKZqKgzb/xNkOme/Pi7e83PKgjnoRDDutvlQb572cJuXVbmNVBue8 EiXqHHuyU/1w== WDCIronportException: Internal From: Alistair Francis To: peter.maydell@linaro.org Subject: [PULL v2 02/14] riscv/sifive_u: Add a serial property to the sifive_u SoC Date: Wed, 29 Apr 2020 13:19:54 -0700 Message-Id: <20200429202006.775322-3-alistair.francis@wdc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200429202006.775322-1-alistair.francis@wdc.com> References: <20200429202006.775322-1-alistair.francis@wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.42; envelope-from=prvs=381fbd49e=alistair.francis@wdc.com; helo=esa4.hgst.iphmx.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/29 16:28:37 X-ACL-Warn: Detected OS = FreeBSD 9.x or newer [fuzzy] X-Received-From: 216.71.154.42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , palmerdabbelt@google.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Bin Meng Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" At present the board serial number is hard-coded to 1, and passed to OTP model during initialization. Firmware (FSBL, U-Boot) uses the serial number to generate a unique MAC address for the on-chip ethernet controller. When multiple QEMU 'sifive_u' instances are created and connected to the same subnet, they all have the same MAC address hence it creates a unusable network. A new "serial" property is introduced to the sifive_u SoC to specify the board serial number. When not given, the default serial number 1 is used. Suggested-by: Bin Meng Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Tested-by: Bin Meng --- hw/riscv/sifive_u.c | 8 +++++++- include/hw/riscv/sifive_u.h | 2 ++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 7f6a3c6c15..6e659e986f 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -491,7 +491,6 @@ static void riscv_sifive_u_soc_init(Object *obj) TYPE_SIFIVE_U_PRCI); sysbus_init_child_obj(obj, "otp", &s->otp, sizeof(s->otp), TYPE_SIFIVE_U_OTP); - qdev_prop_set_uint32(DEVICE(&s->otp), "serial", OTP_SERIAL); sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem), TYPE_CADENCE_GEM); } @@ -584,6 +583,7 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev= , Error **errp) object_property_set_bool(OBJECT(&s->prci), true, "realized", &err); sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].bas= e); =20 + qdev_prop_set_uint32(DEVICE(&s->otp), "serial", s->serial); object_property_set_bool(OBJECT(&s->otp), true, "realized", &err); sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base); =20 @@ -610,10 +610,16 @@ static void riscv_sifive_u_soc_realize(DeviceState *d= ev, Error **errp) memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size); } =20 +static Property riscv_sifive_u_soc_props[] =3D { + DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL), + DEFINE_PROP_END_OF_LIST() +}; + static void riscv_sifive_u_soc_class_init(ObjectClass *oc, void *data) { DeviceClass *dc =3D DEVICE_CLASS(oc); =20 + device_class_set_props(dc, riscv_sifive_u_soc_props); dc->realize =3D riscv_sifive_u_soc_realize; /* Reason: Uses serial_hds in realize function, thus can't be used twi= ce */ dc->user_creatable =3D false; diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index 82667b5746..a2baa1de5f 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -42,6 +42,8 @@ typedef struct SiFiveUSoCState { SiFiveUPRCIState prci; SiFiveUOTPState otp; CadenceGEMState gem; + + uint32_t serial; } SiFiveUSoCState; =20 #define TYPE_RISCV_U_MACHINE MACHINE_TYPE_NAME("sifive_u") --=20 2.26.2