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Iglesias" To: qemu-devel@nongnu.org Subject: [PATCH v1 1/1] target/arm: Drop access_el3_aa32ns() Date: Tue, 28 Apr 2020 18:03:50 +0200 Message-Id: <20200428160350.10030-2-edgar.iglesias@gmail.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200428160350.10030-1-edgar.iglesias@gmail.com> References: <20200428160350.10030-1-edgar.iglesias@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::144; envelope-from=edgar.iglesias@gmail.com; helo=mail-lf1-x144.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::144 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: laurent.desnogues@gmail.com, peter.maydell@linaro.org, qemu-arm@nongnu.org, richard.henderson@linaro.org, edgar.iglesias@xilinx.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Calling access_el3_aa32ns() works for AArch32 only cores but it does not handle 32-bit EL2 on top of 64-bit EL3 for mixed 32/64-bit cores. Fold access_el3_aa32ns() into access_el3_aa32ns_aa64any() and replace all direct uses of the aa32 only version with access_el3_aa32ns_aa64any(). Fixes: 68e9c2fe65 ("target-arm: Add VTCR_EL2") Reported-by: Laurent Desnogues Signed-off-by: Edgar E. Iglesias --- target/arm/helper.c | 34 ++++++++++------------------------ 1 file changed, 10 insertions(+), 24 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7e9ea5d20f..888f5f2314 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -504,29 +504,15 @@ void init_cpreg_list(ARMCPU *cpu) /* * Some registers are not accessible if EL3.NS=3D0 and EL3 is using AArch3= 2 but * they are accessible when EL3 is using AArch64 regardless of EL3.NS. - * - * access_el3_aa32ns: Used to check AArch32 register views. - * access_el3_aa32ns_aa64any: Used to check both AArch32/64 register views. */ -static CPAccessResult access_el3_aa32ns(CPUARMState *env, - const ARMCPRegInfo *ri, - bool isread) -{ - bool secure =3D arm_is_secure_below_el3(env); - - assert(!arm_el_is_aa64(env, 3)); - if (secure) { - return CP_ACCESS_TRAP_UNCATEGORIZED; - } - return CP_ACCESS_OK; -} - static CPAccessResult access_el3_aa32ns_aa64any(CPUARMState *env, const ARMCPRegInfo *ri, bool isread) { - if (!arm_el_is_aa64(env, 3)) { - return access_el3_aa32ns(env, ri, isread); + bool secure =3D arm_is_secure_below_el3(env); + + if (!arm_el_is_aa64(env, 3) && secure) { + return CP_ACCESS_TRAP_UNCATEGORIZED; } return CP_ACCESS_OK; } @@ -5223,7 +5209,7 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] =3D= { .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "VTTBR", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 6, .crm =3D 2, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, + .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns_aa64any, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetvalue =3D 0 }, { .name =3D "VTTBR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 0, @@ -5556,7 +5542,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { { .name =3D "VTCR", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, .type =3D ARM_CP_ALIAS, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, + .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns_aa64any, .fieldoffset =3D offsetof(CPUARMState, cp15.vtcr_el2) }, { .name =3D "VTCR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, @@ -5568,7 +5554,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { { .name =3D "VTTBR", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 6, .crm =3D 2, .type =3D ARM_CP_64BIT | ARM_CP_ALIAS, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, + .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns_aa64any, .fieldoffset =3D offsetof(CPUARMState, cp15.vttbr_el2), .writefn =3D vttbr_write }, { .name =3D "VTTBR_EL2", .state =3D ARM_CP_STATE_AA64, @@ -5708,7 +5694,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.mdcr_el2), }, { .name =3D "HPFAR", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 4, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, + .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns_aa64any, .fieldoffset =3D offsetof(CPUARMState, cp15.hpfar_el2) }, { .name =3D "HPFAR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 4, @@ -7565,7 +7551,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) ARMCPRegInfo vpidr_regs[] =3D { { .name =3D "VPIDR", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, + .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns_aa64any, .resetvalue =3D cpu->midr, .type =3D ARM_CP_ALIAS, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.vpidr_el2) = }, { .name =3D "VPIDR_EL2", .state =3D ARM_CP_STATE_AA64, @@ -7574,7 +7560,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .fieldoffset =3D offsetof(CPUARMState, cp15.vpidr_el2) }, { .name =3D "VMPIDR", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D 5, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, + .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns_aa64any, .resetvalue =3D vmpidr_def, .type =3D ARM_CP_ALIAS, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.vmpidr_el2)= }, { .name =3D "VMPIDR_EL2", .state =3D ARM_CP_STATE_AA64, --=20 2.20.1