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[88.21.205.137]) by smtp.gmail.com with ESMTPSA id t8sm25983160wrq.88.2020.04.28.08.50.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 28 Apr 2020 08:50:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=sf14oS2GltqACboZYW3TtfGDUWMhQH2NEauPtmLwgGs=; b=h3mLT85+GgkHeVuaeMyDP4n/XAZpk5EE6+Be0FyldMekdacH6/eE2Av9Z+U8UbyY9K A+Qd+Zi+Q83+AR6HROs0bgdtwjFFKybzak4Q/BYWSfoN95GgfvI1R87x7IWi0wqygVr6 JwoprFL0u1WEWh4QWmfMiHtmXSXl97q+PKyfJbMBbTCmFmd9C2qUsWhwwqaRrLZua+Kp sYQtJ1JkI7AIsqt8KRSoglvVMLdOF2q6k1HGibRCq+B0e8vU33WZuEM1uz2t6fdHrYRf 8kJtQDZGtc3v+MD520JZAN0N1nY6Ap9Tyboo9aunKUUypIXzd85viLhh9YvB3smnahf4 PfPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :mime-version:content-transfer-encoding; bh=sf14oS2GltqACboZYW3TtfGDUWMhQH2NEauPtmLwgGs=; b=AMFZGDUVmm/Yv59W0kCl9KDLE4fb6A9awWZH/RVetw4cFUiSJsJ9PSiA4yULv12eLr G0M54dVkAbxFGJ70NwCpMzaN7ixwNcK3Wje8c+J5xdq4dx6kfE4SajK1DB4POMwSH3wS C0Tp1aZoS/22+/x8kcahfePKQsJREqzaLN9iErPp1AlVTcGFRoQ/HaXZVBp3yCgo9/06 QYvFguDP7i73m376J7SJSWhOZkkKrLb0DZB/IwxHaHJKLJxW+lVv9t+pzkryGoq2XCsk 526hqYZX6Fbtnb7W38sktf/YrHk2g4RxRIaPhBei7NSbJrttRnNuOKr5BXKqavbG6Ze3 EpRw== X-Gm-Message-State: AGi0PuZHCv+VOVXBk3NeUjr9srXFHIO54Xm0I2+kAuldSEW+NiAXx9qW 6NEbYy0TkbMcSPXhD49rovTJNpYXlFk= X-Google-Smtp-Source: APiQypIhPK+mLhTzhYDqmusZbnyzer1aZHJCzZP1wyFp2X8g+W1pp/4fB8TUwAPaWmjDRgD6fExLag== X-Received: by 2002:adf:ee05:: with SMTP id y5mr32597974wrn.176.1588089007248; Tue, 28 Apr 2020 08:50:07 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v2] target/arm: Use correct variable for setting 'max' cpu's MIDR_EL1 Date: Tue, 28 Apr 2020 17:50:05 +0200 Message-Id: <20200428155005.25537-1-f4bug@amsat.org> X-Mailer: git-send-email 2.21.1 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::444; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-x444.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Desnogues , Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) MIDR_EL1 a 64-bit system register with the top 32-bit being RES0. This fixes when compiling with -Werror=3Dconversion: target/arm/cpu64.c: In function =E2=80=98aarch64_max_initfn=E2=80=99: target/arm/cpu64.c:628:21: error: conversion from =E2=80=98uint64_t=E2=80= =99 {aka =E2=80=98long unsigned int=E2=80=99} to =E2=80=98uint32_t=E2=80=99= {aka =E2=80=98unsigned int=E2=80=99} may change value [-Werror=3Dconversio= n] 628 | cpu->midr =3D t; | ^ Suggested-by: Laurent Desnogues Suggested-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- I suppose cp15.c0_cpuid register in target/arm/cpu.h as uint32_t is OK. Since v1: Follow Laurent and Peter suggestion. --- target/arm/cpu.h | 3 ++- target/arm/cpu.c | 4 +++- 2 files changed, 5 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8b9f2961ba..4d1be56df9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -894,7 +894,7 @@ struct ARMCPU { uint64_t id_aa64dfr0; uint64_t id_aa64dfr1; } isar; - uint32_t midr; + uint64_t midr; uint32_t revidr; uint32_t reset_fpsid; uint32_t ctr; @@ -1685,6 +1685,7 @@ FIELD(MIDR_EL1, PARTNUM, 4, 12) FIELD(MIDR_EL1, ARCHITECTURE, 16, 4) FIELD(MIDR_EL1, VARIANT, 20, 4) FIELD(MIDR_EL1, IMPLEMENTER, 24, 8) +FIELD(MIDR_EL1, RESERVED, 32, 32) =20 FIELD(ID_ISAR0, SWAP, 0, 4) FIELD(ID_ISAR0, BITCOUNT, 4, 4) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a79f233b17..aaa48e06ac 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1182,6 +1182,8 @@ void arm_cpu_post_init(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); =20 + assert(FIELD_EX64(cpu->midr, MIDR_EL1, RESERVED) =3D=3D 0); + /* M profile implies PMSA. We have to do this here rather than * in realize with the other feature-implication checks because * we look at the PMSA bit to see if we should add some properties. @@ -2757,7 +2759,7 @@ static const ARMCPUInfo arm_cpus[] =3D { static Property arm_cpu_properties[] =3D { DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false= ), DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0), - DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0), + DEFINE_PROP_UINT64("midr", ARMCPU, midr, 0), DEFINE_PROP_UINT64("mp-affinity", ARMCPU, mp_affinity, ARM64_AFFINITY_INVALID), DEFINE_PROP_INT32("node-id", ARMCPU, node_id, CPU_UNSET_NUMA_NODE_ID), --=20 2.21.1