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[81.2.115.148]) by smtp.gmail.com with ESMTPSA id l5sm3222495wrm.66.2020.04.23.04.09.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 23 Apr 2020 04:09:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=VlGWIXhjhVMOKcrHBCT24bZUCyJntPMX9y4VK0odchk=; b=Eum+PiPOayqHCiEa/E6PHYxAv7LxkfmO5dNWLfbFQs1Iv7vhwkMWHEZDSL/OhVG6+6 hKnN/msgEjrRzV15B5RqlSeOxY35THIC+Qhrrisa+SmeyXcKbfwykFN6f3vUoHdo6ZzP Cp+KZ0AREbCg/CyMLvZEoQXmrhiMVGMSSiZB1jq0WJUYAVJRy2WgmrTm3ZYWmZIwvdLL EYRSGDEv6fCYX5upHAT7z2v0a3fxLsoGf2IyQ5t3VlDciwa+5usMM5UJXCINvtsZtSy5 JHdJo07u4scwPA1Ol2EblcK1DHlojgK0JS1PT5NLYNxgq4987Niw2I3qgN5HG8b5jkHJ SbyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=VlGWIXhjhVMOKcrHBCT24bZUCyJntPMX9y4VK0odchk=; b=rgL4OdctBahTvcEfUB2h8fXKWnZEgzJpl8jKuwzSRL+aPV2lu6KIkw6+rttCmNNm4k +dZFVv28zzH/cBO2NrXOz9mMxWckY8du3wjWtnlPJ0K4KP4+GvVGubyq+TxZUQpV30a1 WqzPp5imZUiLBOsUj8zh17bhGTJjM3Ozq8AN4r2grwBETtD0+8AbGONqnBLmpIBolSJd llDHt4RGM4H9UsKT25ixHSnydenILAGVv+ScQqsKR1AWuZpuvNoe68c3DsStScGZBnc4 qOSPb4sVyMBRIQCMkW6RSVegw0TJHyUEnf5llleAxl9nD1/5HgCfgYNYwumtNFHHJA6R xTjg== X-Gm-Message-State: AGi0PuYoSrohUHjPJlw9m718rEWv9RXsnKw+jBf1jhZgflZFBmrRufo4 /MSbEJMxnPGARSQK1oh4yya4og== X-Google-Smtp-Source: APiQypLrY2akUba3hEKAHoZM0FA33vCDrAdaKDOOJB/zGMVacJpyrEBTsHxQxjTuh5aALDz+ZaexQw== X-Received: by 2002:adf:e8c4:: with SMTP id k4mr4198349wrn.209.1587640157758; Thu, 23 Apr 2020 04:09:17 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH] target/arm: Use correct variable for setting 'max' cpu's ID_AA64DFR0 Date: Thu, 23 Apr 2020 12:09:15 +0100 Message-Id: <20200423110915.10527-1-peter.maydell@linaro.org> X-Mailer: git-send-email 2.20.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::442; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x442.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::442 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" In aarch64_max_initfn() we update both 32-bit and 64-bit ID registers. The intended pattern is that for 64-bit ID registers we use FIELD_DP64 and the uint64_t 't' register, while 32-bit ID registers use FIELD_DP32 and the uint32_t 'u' register. For ID_AA64DFR0 we accidentally used 'u', meaning that the top 32 bits of this 64-bit ID register would end up always zero. Luckily at the moment that's what they should be anyway, so this bug has no visible effects. Use the right-sized variable. Fixes: 3bec78447a958d481991 Signed-off-by: Peter Maydell Reviewed-by: Laurent Desnogues Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu64.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 95d0c8c101a..4c7105ea1a1 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -708,9 +708,9 @@ static void aarch64_max_initfn(Object *obj) u =3D FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */ cpu->isar.id_mmfr4 =3D u; =20 - u =3D cpu->isar.id_aa64dfr0; - u =3D FIELD_DP64(u, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ - cpu->isar.id_aa64dfr0 =3D u; + t =3D cpu->isar.id_aa64dfr0; + t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ + cpu->isar.id_aa64dfr0 =3D t; =20 u =3D cpu->isar.id_dfr0; u =3D FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ --=20 2.20.1