From nobody Tue Feb 10 00:23:22 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1587539479; cv=none; d=zohomail.com; s=zohoarc; b=RHzWGjmzr0UrxitCSiubVZvDDWeTDx8vfVjwMtbptux5jxh5oGA50xh84Khe2JUlLsLWGM1Lmp82c3EQoaw36M/CxEZIhbCeoa1i8UuBcHqhLRJDSWeGBjp1fiWsBl19laYX4RIisFAYH5I7BC1G4B30u//qTq1xyqRv8e3+NYc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1587539479; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=RIjoRN+5U7EuDJCyfLXdLjDrmJTTG25ZNVdw7cr1A/w=; b=Gz/7nKXprm6jqIItxfBRbQzUfNTqYV5la1nt7CsC71Gz6+4YGW+pfJOLMJVfnylARCD1IrB8k44hrXBnnza3F+3T+gKUrgV3kEpbOBxNLvSbWcavbqva7irx6h8f8h3zbOipBy17td+XYXEvkW4cLRzBmIOapwhsjfdSU87BvxY= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 158753947928476.49869213461636; Wed, 22 Apr 2020 00:11:19 -0700 (PDT) Received: from localhost ([::1]:45248 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jR9XR-0003B4-Rr for importer@patchew.org; Wed, 22 Apr 2020 03:11:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39552) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jR9Vv-0000fD-My for qemu-devel@nongnu.org; Wed, 22 Apr 2020 03:09:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.90_1) (envelope-from ) id 1jR9Vu-0007Kc-PL for qemu-devel@nongnu.org; Wed, 22 Apr 2020 03:09:43 -0400 Received: from charlie.dont.surf ([128.199.63.193]:60218) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1jR9Vp-0007Bf-As; Wed, 22 Apr 2020 03:09:37 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id E7BAEBFD25; Wed, 22 Apr 2020 07:09:34 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v3 04/16] nvme: move device parameters to separate struct Date: Wed, 22 Apr 2020 09:09:15 +0200 Message-Id: <20200422070927.373048-5-its@irrelevant.dk> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20200422070927.373048-1-its@irrelevant.dk> References: <20200422070927.373048-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=128.199.63.193; envelope-from=its@irrelevant.dk; helo=charlie.dont.surf X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/22 02:19:11 X-ACL-Warn: Detected OS = Linux 3.11 and newer [fuzzy] X-Received-From: 128.199.63.193 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen Move device configuration parameters to separate struct to make it explicit what is configurable and what is set internally. Signed-off-by: Klaus Jensen Signed-off-by: Klaus Jensen Reviewed-by: Maxim Levitsky Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/block/nvme.c | 49 ++++++++++++++++++++++++------------------------- hw/block/nvme.h | 18 +++++++++++++++--- 2 files changed, 39 insertions(+), 28 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index f67499d85f3a..382275e466fe 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -78,12 +78,12 @@ static void nvme_addr_read(NvmeCtrl *n, hwaddr addr, vo= id *buf, int size) =20 static int nvme_check_sqid(NvmeCtrl *n, uint16_t sqid) { - return sqid < n->num_queues && n->sq[sqid] !=3D NULL ? 0 : -1; + return sqid < n->params.num_queues && n->sq[sqid] !=3D NULL ? 0 : -1; } =20 static int nvme_check_cqid(NvmeCtrl *n, uint16_t cqid) { - return cqid < n->num_queues && n->cq[cqid] !=3D NULL ? 0 : -1; + return cqid < n->params.num_queues && n->cq[cqid] !=3D NULL ? 0 : -1; } =20 static void nvme_inc_cq_tail(NvmeCQueue *cq) @@ -645,7 +645,7 @@ static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeCmd *cm= d) trace_pci_nvme_err_invalid_create_cq_addr(prp1); return NVME_INVALID_FIELD | NVME_DNR; } - if (unlikely(vector > n->num_queues)) { + if (unlikely(vector > n->params.num_queues)) { trace_pci_nvme_err_invalid_create_cq_vector(vector); return NVME_INVALID_IRQ_VECTOR | NVME_DNR; } @@ -797,7 +797,8 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeCmd *= cmd, NvmeRequest *req) trace_pci_nvme_getfeat_vwcache(result ? "enabled" : "disabled"); break; case NVME_NUMBER_OF_QUEUES: - result =3D cpu_to_le32((n->num_queues - 2) | ((n->num_queues - 2) = << 16)); + result =3D cpu_to_le32((n->params.num_queues - 2) | + ((n->params.num_queues - 2) << 16)); trace_pci_nvme_getfeat_numq(result); break; case NVME_TIMESTAMP: @@ -841,9 +842,10 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeCmd = *cmd, NvmeRequest *req) case NVME_NUMBER_OF_QUEUES: trace_pci_nvme_setfeat_numq((dw11 & 0xFFFF) + 1, ((dw11 >> 16) & 0xFFFF) + 1, - n->num_queues - 1, n->num_queues - 1); - req->cqe.result =3D - cpu_to_le32((n->num_queues - 2) | ((n->num_queues - 2) << 16)); + n->params.num_queues - 1, + n->params.num_queues - 1); + req->cqe.result =3D cpu_to_le32((n->params.num_queues - 2) | + ((n->params.num_queues - 2) << 16)); break; case NVME_TIMESTAMP: return nvme_set_feature_timestamp(n, cmd); @@ -914,12 +916,12 @@ static void nvme_clear_ctrl(NvmeCtrl *n) =20 blk_drain(n->conf.blk); =20 - for (i =3D 0; i < n->num_queues; i++) { + for (i =3D 0; i < n->params.num_queues; i++) { if (n->sq[i] !=3D NULL) { nvme_free_sq(n->sq[i], n); } } - for (i =3D 0; i < n->num_queues; i++) { + for (i =3D 0; i < n->params.num_queues; i++) { if (n->cq[i] !=3D NULL) { nvme_free_cq(n->cq[i], n); } @@ -1350,7 +1352,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error **= errp) int64_t bs_size; uint8_t *pci_conf; =20 - if (!n->num_queues) { + if (!n->params.num_queues) { error_setg(errp, "num_queues can't be zero"); return; } @@ -1366,12 +1368,12 @@ static void nvme_realize(PCIDevice *pci_dev, Error = **errp) return; } =20 - if (!n->serial) { + if (!n->params.serial) { error_setg(errp, "serial property not set"); return; } =20 - if (!n->cmb_size_mb && n->pmrdev) { + if (!n->params.cmb_size_mb && n->pmrdev) { if (host_memory_backend_is_mapped(n->pmrdev)) { char *path =3D object_get_canonical_path_component(OBJECT(n->p= mrdev)); error_setg(errp, "can't use already busy memdev: %s", path); @@ -1402,25 +1404,26 @@ static void nvme_realize(PCIDevice *pci_dev, Error = **errp) n->num_namespaces =3D 1; =20 /* num_queues is really number of pairs, so each has two doorbells */ - n->reg_size =3D pow2ceil(NVME_REG_SIZE + 2 * n->num_queues * NVME_DB_S= IZE); + n->reg_size =3D pow2ceil(NVME_REG_SIZE + + 2 * n->params.num_queues * NVME_DB_SIZE); n->ns_size =3D bs_size / (uint64_t)n->num_namespaces; =20 n->namespaces =3D g_new0(NvmeNamespace, n->num_namespaces); - n->sq =3D g_new0(NvmeSQueue *, n->num_queues); - n->cq =3D g_new0(NvmeCQueue *, n->num_queues); + n->sq =3D g_new0(NvmeSQueue *, n->params.num_queues); + n->cq =3D g_new0(NvmeCQueue *, n->params.num_queues); =20 memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme", n->reg_size); pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, &n->iomem); - msix_init_exclusive_bar(pci_dev, n->num_queues, 4, NULL); + msix_init_exclusive_bar(pci_dev, n->params.num_queues, 4, NULL); =20 id->vid =3D cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID)); id->ssvid =3D cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR= _ID)); strpadcpy((char *)id->mn, sizeof(id->mn), "QEMU NVMe Ctrl", ' '); strpadcpy((char *)id->fr, sizeof(id->fr), "1.0", ' '); - strpadcpy((char *)id->sn, sizeof(id->sn), n->serial, ' '); + strpadcpy((char *)id->sn, sizeof(id->sn), n->params.serial, ' '); id->rab =3D 6; id->ieee[0] =3D 0x00; id->ieee[1] =3D 0x02; @@ -1449,7 +1452,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error **= errp) n->bar.vs =3D 0x00010200; n->bar.intmc =3D n->bar.intms =3D 0; =20 - if (n->cmb_size_mb) { + if (n->params.cmb_size_mb) { =20 NVME_CMBLOC_SET_BIR(n->bar.cmbloc, 2); NVME_CMBLOC_SET_OFST(n->bar.cmbloc, 0); @@ -1460,7 +1463,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error **= errp) NVME_CMBSZ_SET_RDS(n->bar.cmbsz, 1); NVME_CMBSZ_SET_WDS(n->bar.cmbsz, 1); NVME_CMBSZ_SET_SZU(n->bar.cmbsz, 2); /* MBs */ - NVME_CMBSZ_SET_SZ(n->bar.cmbsz, n->cmb_size_mb); + NVME_CMBSZ_SET_SZ(n->bar.cmbsz, n->params.cmb_size_mb); =20 n->cmbloc =3D n->bar.cmbloc; n->cmbsz =3D n->bar.cmbsz; @@ -1544,7 +1547,7 @@ static void nvme_exit(PCIDevice *pci_dev) g_free(n->cq); g_free(n->sq); =20 - if (n->cmb_size_mb) { + if (n->params.cmb_size_mb) { g_free(n->cmbuf); } =20 @@ -1556,11 +1559,7 @@ static void nvme_exit(PCIDevice *pci_dev) =20 static Property nvme_props[] =3D { DEFINE_BLOCK_PROPERTIES(NvmeCtrl, conf), - DEFINE_PROP_LINK("pmrdev", NvmeCtrl, pmrdev, TYPE_MEMORY_BACKEND, - HostMemoryBackend *), - DEFINE_PROP_STRING("serial", NvmeCtrl, serial), - DEFINE_PROP_UINT32("cmb_size_mb", NvmeCtrl, cmb_size_mb, 0), - DEFINE_PROP_UINT32("num_queues", NvmeCtrl, num_queues, 64), + DEFINE_NVME_PROPERTIES(NvmeCtrl, params), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/hw/block/nvme.h b/hw/block/nvme.h index 6520a9f0bead..7cb1d5e31870 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -1,7 +1,21 @@ #ifndef HW_NVME_H #define HW_NVME_H + #include "block/nvme.h" =20 +#define DEFINE_NVME_PROPERTIES(_state, _props) \ + DEFINE_PROP_STRING("serial", _state, _props.serial), \ + DEFINE_PROP_UINT32("cmb_size_mb", _state, _props.cmb_size_mb, 0), \ + DEFINE_PROP_UINT32("num_queues", _state, _props.num_queues, 64), \ + DEFINE_PROP_LINK("pmrdev", _state, pmrdev, TYPE_MEMORY_BACKEND, \ + HostMemoryBackend *) + +typedef struct NvmeParams { + char *serial; + uint32_t num_queues; + uint32_t cmb_size_mb; +} NvmeParams; + typedef struct NvmeAsyncEvent { QSIMPLEQ_ENTRY(NvmeAsyncEvent) entry; NvmeAerResult result; @@ -63,6 +77,7 @@ typedef struct NvmeCtrl { MemoryRegion ctrl_mem; NvmeBar bar; BlockConf conf; + NvmeParams params; =20 uint32_t page_size; uint16_t page_bits; @@ -71,10 +86,8 @@ typedef struct NvmeCtrl { uint16_t sqe_size; uint32_t reg_size; uint32_t num_namespaces; - uint32_t num_queues; uint32_t max_q_ents; uint64_t ns_size; - uint32_t cmb_size_mb; uint32_t cmbsz; uint32_t cmbloc; uint8_t *cmbuf; @@ -82,7 +95,6 @@ typedef struct NvmeCtrl { uint64_t host_timestamp; /* Timestamp sent by the h= ost */ uint64_t timestamp_set_qemu_clock_ms; /* QEMU clock time */ =20 - char *serial; HostMemoryBackend *pmrdev; =20 NvmeNamespace *namespaces; --=20 2.26.2