From nobody Tue Feb 10 09:58:14 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1587530918; cv=none; d=zohomail.com; s=zohoarc; b=fdKYjfbZc1sDw5dXqNsuvYE52cioje3G843QZZ5qfJx5adfv6biBo+ilUWf1+AAXhQgjEPwpICvb+59Pyk4c4zLHjqMZUqpb70kcvxiZZa61ZUDqZ96I6axbAtN8oxRbQb5dtApaxQZ6KRl4dBvwyJoDXAGkSC8T0aEUPXSUJ4Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1587530918; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kAjJuC8E6QocqpgcZFzGlZ3iBSLxUs4KOHUk+pvyTWc=; b=nZH2UinRvZyX8DGXSKBRllxfA0lOyjh+JBf84sN5Smv6suNGq04YDZCS8nrX/bNIcqW9AyorFZFYAyv+IC8tHhe5rOjQms5r9WpajHNjL3vJqoxIVgBoIHd7bwLKhDn411L7+5a+lbFOLzypJ8FOSwR+6w+nmCee0hhDLV23Msg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1587530918500230.03061981358167; Tue, 21 Apr 2020 21:48:38 -0700 (PDT) Received: from localhost ([::1]:41688 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jR7JN-0006Jl-Bo for importer@patchew.org; Wed, 22 Apr 2020 00:48:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50980) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jR74v-0001CF-GA for qemu-devel@nongnu.org; Wed, 22 Apr 2020 00:33:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.90_1) (envelope-from ) id 1jR74s-0006OG-DS for qemu-devel@nongnu.org; Wed, 22 Apr 2020 00:33:41 -0400 Received: from mail-pl1-x641.google.com ([2607:f8b0:4864:20::641]:46418) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1jR74r-0006JU-Ug for qemu-devel@nongnu.org; Wed, 22 Apr 2020 00:33:38 -0400 Received: by mail-pl1-x641.google.com with SMTP id n24so422250plp.13 for ; Tue, 21 Apr 2020 21:33:37 -0700 (PDT) Received: from localhost.localdomain (174-21-149-226.tukw.qwest.net. [174.21.149.226]) by smtp.gmail.com with ESMTPSA id l137sm4129613pfd.107.2020.04.21.21.33.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Apr 2020 21:33:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kAjJuC8E6QocqpgcZFzGlZ3iBSLxUs4KOHUk+pvyTWc=; b=mPea3epQd8fn6acRviE37rsYywYW8IdPLb5a2WnFJSrPd/POhHRq3OnVP4kFXelPdq kIhpiuAbJXRUAo00TPNNQVnBQDKvB+fFMcF3FpvW5rpE5orWST6aPx8APTmANdrrRAxo 6BQPUjJa+mHrN87y4ShMQGq4mCOu4kJ7iQLqyOFGOgvqSJxGDrPXkJBsRpKIiQ8xZi/i 8rrpUEDClG9VNZc5spxmH7/4YgauFGur5ndvanGvszDNp+NiiQMT76Rr3bNOyCQ0lDJ5 nwStRZChUjUzrYC0gS3zLwI7uhdN3WeYnSNAQ9mfu9wf3xLeOaMCMSn6spiakzvSCWJw Sepw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kAjJuC8E6QocqpgcZFzGlZ3iBSLxUs4KOHUk+pvyTWc=; b=cYFf9lIEba/Tv95pCP+68rAMMq2KzUuXvX/aQy99lyrWh51RcQiQlHkWwfX/9rfEtf 0VYZeDwbDC8CxCzmIXsRacCx2SjgpqXyGsWLwm4L34SyldcFIlR6HkJkAffIcIAM3hwI LDmTixg2dLejk4HlwU4J8P69sMFokrFG/ctH8zYjWzmVGZZDsr/EVMS7Lk/285GWc69j ygWEGvrWeP32S2ZAuprjmcAMIp3np2p+EMx8Zlz7YKTOSbSC50qUfCELpgJFXVjGfDOQ h3ZNzC7UdjgI2H5sRv/cjQVZI5Ec6Pc4OwlhuYg3Q04qfWyk8ypVVbcoBZeXWmJhgGOU 3+BA== X-Gm-Message-State: AGi0PuYrouWl5aSrVMs2HaLRjorqCg8CqFcPVu6sWeO8618VkyP1dAth BqCaNZiU//L1r7ciOyJ6MGAzBhLju28= X-Google-Smtp-Source: APiQypK8MR/Hq9hCc/bbwwiJPAdotgSA9b9iquvVNF1cGddYz+60rmFDDVvAGNExqkBTPnI1A6jMZg== X-Received: by 2002:a17:90b:3110:: with SMTP id gc16mr9347810pjb.155.1587530015239; Tue, 21 Apr 2020 21:33:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 18/18] target/arm: Remove sve_memopidx Date: Tue, 21 Apr 2020 21:33:09 -0700 Message-Id: <20200422043309.18430-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200422043309.18430-1-richard.henderson@linaro.org> References: <20200422043309.18430-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::641; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x641.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2607:f8b0:4864:20::641 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" None of the sve helpers use TCGMemOpIdx any longer, so we can stop passing it. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 5 ----- target/arm/sve_helper.c | 14 +++++++------- target/arm/translate-sve.c | 17 +++-------------- 3 files changed, 10 insertions(+), 26 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index e633aff36e..a833e3941d 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -979,11 +979,6 @@ static inline int arm_num_ctx_cmps(ARMCPU *cpu) } } =20 -/* Note make_memop_idx reserves 4 bits for mmu_idx, and MO_BSWAP is bit 3. - * Thus a TCGMemOpIdx, without any MO_ALIGN bits, fits in 8 bits. - */ -#define MEMOPIDX_SHIFT 8 - /** * v7m_using_psp: Return true if using process stack pointer * Return true if the CPU is currently using the process stack diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index fffde4b6ec..f482fdd285 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -4440,7 +4440,7 @@ void sve_ldN_r(CPUARMState *env, uint64_t *vg, const = target_ulong addr, sve_ldst1_host_fn *host_fn, sve_ldst1_tlb_fn *tlb_fn) { - const unsigned rd =3D extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT= , 5); + const unsigned rd =3D simd_data(desc); const intptr_t reg_max =3D simd_oprsz(desc); intptr_t reg_off, reg_last, mem_off; SVEContLdSt info; @@ -4696,7 +4696,7 @@ void sve_ldnfff1_r(CPUARMState *env, void *vg, const = target_ulong addr, sve_ldst1_host_fn *host_fn, sve_ldst1_tlb_fn *tlb_fn) { - const unsigned rd =3D extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT= , 5); + const unsigned rd =3D simd_data(desc); void *vd =3D &env->vfp.zregs[rd]; const intptr_t reg_max =3D simd_oprsz(desc); intptr_t reg_off, mem_off, reg_last; @@ -4921,7 +4921,7 @@ void sve_stN_r(CPUARMState *env, uint64_t *vg, target= _ulong addr, uint32_t desc, sve_ldst1_host_fn *host_fn, sve_ldst1_tlb_fn *tlb_fn) { - const unsigned rd =3D extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT= , 5); + const unsigned rd =3D simd_data(desc); const intptr_t reg_max =3D simd_oprsz(desc); intptr_t reg_off, reg_last, mem_off; SVEContLdSt info; @@ -5127,9 +5127,9 @@ void sve_ld1_z(CPUARMState *env, void *vd, uint64_t *= vg, void *vm, sve_ldst1_host_fn *host_fn, sve_ldst1_tlb_fn *tlb_fn) { - const int scale =3D extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, = 2); const int mmu_idx =3D cpu_mmu_index(env, false); const intptr_t reg_max =3D simd_oprsz(desc); + const int scale =3D simd_data(desc); ARMVectorReg scratch; intptr_t reg_off; SVEHostPage info, info2; @@ -5272,10 +5272,10 @@ void sve_ldff1_z(CPUARMState *env, void *vd, uint64= _t *vg, void *vm, sve_ldst1_tlb_fn *tlb_fn) { const int mmu_idx =3D cpu_mmu_index(env, false); - const int scale =3D extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, = 2); + const intptr_t reg_max =3D simd_oprsz(desc); + const int scale =3D simd_data(desc); const int esize =3D 1 << esz; const int msize =3D 1 << msz; - const intptr_t reg_max =3D simd_oprsz(desc); intptr_t reg_off; SVEHostPage info; target_ulong addr, in_page; @@ -5426,9 +5426,9 @@ void sve_st1_z(CPUARMState *env, void *vd, uint64_t *= vg, void *vm, sve_ldst1_host_fn *host_fn, sve_ldst1_tlb_fn *tlb_fn) { - const int scale =3D extract32(desc, SIMD_DATA_SHIFT + MEMOPIDX_SHIFT, = 2); const int mmu_idx =3D cpu_mmu_index(env, false); const intptr_t reg_max =3D simd_oprsz(desc); + const int scale =3D simd_data(desc); void *host[ARM_MAX_VQ * 4]; intptr_t reg_off, i; SVEHostPage info, info2; diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index b35bad245e..7bd7de80e6 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4584,11 +4584,6 @@ static const uint8_t dtype_esz[16] =3D { 3, 2, 1, 3 }; =20 -static TCGMemOpIdx sve_memopidx(DisasContext *s, int dtype) -{ - return make_memop_idx(s->be_data | dtype_mop[dtype], get_mem_index(s)); -} - static void do_mem_zpa(DisasContext *s, int zt, int pg, TCGv_i64 addr, int dtype, gen_helper_gvec_mem *fn) { @@ -4601,9 +4596,7 @@ static void do_mem_zpa(DisasContext *s, int zt, int p= g, TCGv_i64 addr, * registers as pointers, so encode the regno into the data field. * For consistency, do this even for LD1. */ - desc =3D sve_memopidx(s, dtype); - desc |=3D zt << MEMOPIDX_SHIFT; - desc =3D simd_desc(vsz, vsz, desc); + desc =3D simd_desc(vsz, vsz, zt); t_desc =3D tcg_const_i32(desc); t_pg =3D tcg_temp_new_ptr(); =20 @@ -4835,9 +4828,7 @@ static void do_ldrq(DisasContext *s, int zt, int pg, = TCGv_i64 addr, int msz) int desc, poff; =20 /* Load the first quadword using the normal predicated load helpers. = */ - desc =3D sve_memopidx(s, msz_dtype(s, msz)); - desc |=3D zt << MEMOPIDX_SHIFT; - desc =3D simd_desc(16, 16, desc); + desc =3D simd_desc(16, 16, zt); t_desc =3D tcg_const_i32(desc); =20 poff =3D pred_full_reg_offset(s, pg); @@ -5066,9 +5057,7 @@ static void do_mem_zpz(DisasContext *s, int zt, int p= g, int zm, TCGv_i32 t_desc; int desc; =20 - desc =3D sve_memopidx(s, msz_dtype(s, msz)); - desc |=3D scale << MEMOPIDX_SHIFT; - desc =3D simd_desc(vsz, vsz, desc); + desc =3D simd_desc(vsz, vsz, scale); t_desc =3D tcg_const_i32(desc); =20 tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); --=20 2.20.1