From nobody Sat May 18 13:16:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1587475372; cv=none; d=zohomail.com; s=zohoarc; b=X69WFHvZP0Nxgopi2zIiCILgpyk1b3jYY6ZnjpXMKG8Ft0wb/6A+3RBRHWAJG0ME8/LUlPq6wEyrg0zzTYrlGYgMffG4e0UGQQpCDMD7dvDIWawiKqImuCzN5SA4YvzafXsSZmNmams7xqc7z+H91mkbMAzL3WnxwnkOX0eCtas= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1587475372; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=uMFN46GGJRGQBe/rYYHHm3lwuDss4tLS+w7l4aZddpQ=; b=laDGXErkPij3H5EEOwTvqeXiagTjwPOpcT1L1QZZ/CgOmgFEDE17q1MgFF5ZQ5oL+cpuhVF1iAr9HXHM0CrJ3UcLo5gYNRcx6Qzwf2TwIdogFFdTI/n4B11uqgfEBHv2kpi1JTq8/FjFdvabPHBWY/DVL2AzlM5/2HWRXo6DZzk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1587475372173386.3360668062254; Tue, 21 Apr 2020 06:22:52 -0700 (PDT) Received: from localhost ([::1]:58316 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jQsrS-0005ND-RH for importer@patchew.org; Tue, 21 Apr 2020 09:22:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48378) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jQsoO-0000wD-3T for qemu-devel@nongnu.org; Tue, 21 Apr 2020 09:19:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.90_1) (envelope-from ) id 1jQsoN-0007NK-GP for qemu-devel@nongnu.org; Tue, 21 Apr 2020 09:19:39 -0400 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:58837 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1jQsoN-0007LR-3X for qemu-devel@nongnu.org; Tue, 21 Apr 2020 09:19:39 -0400 Received: from mail-wr1-f71.google.com (mail-wr1-f71.google.com [209.85.221.71]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-466-QbP3bM4lOXm6WTdX5T33ow-1; Tue, 21 Apr 2020 09:19:35 -0400 Received: by mail-wr1-f71.google.com with SMTP id p16so7470949wro.16 for ; Tue, 21 Apr 2020 06:19:35 -0700 (PDT) Received: from x1w.redhat.com (116.red-83-42-57.dynamicip.rima-tde.net. [83.42.57.116]) by smtp.gmail.com with ESMTPSA id t16sm4307074wrb.8.2020.04.21.06.19.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Apr 2020 06:19:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1587475178; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=uMFN46GGJRGQBe/rYYHHm3lwuDss4tLS+w7l4aZddpQ=; b=Ob69b3JNJIcAnudEgSWXy2wp9EPlceo+q9763wIYBcks0f9Q/EMhXTzGomztgVbS+DynLv T+ADxmsEf9v/EVP6/Z264aCEqQA6R2Q6H1EIGmbnJBJje5iYYX2wP1fKsntmx0qinaUPBf Opl0dAqCd3QjFPKJDYU3rhzdCvRaUnk= X-MC-Unique: QbP3bM4lOXm6WTdX5T33ow-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ae/4+1sN6db4JUzTalWSGb//t3m1oKTsE7xQyTnypSQ=; b=MzEIGQbfxbT2SfQ22eMLX+F92EsUmStTfq42Icx4kRg6TDSHrPRsL4tBWQWCnhz9aF UYCDy6hGtv0KG2EyNaD4S7T4HpvrWIJEXOoOsiEhF+yKVmovZUXZom4vZX5MW1Tq5+BG nzmgwDaeoAgYxxcIPLbRakg4VNSevch/1/KXwWlux7oKj/G1k61Awlz1561r8RVwesa0 ZKAsjWkxq4IfDp9rTUgwzMQalVo5CvFK+pYeSGBGlPEkh2kOkC6v/u41rOiKeYZdAgiz U61saXgz9GVyvdVaJqCuWDookqoZWmhPkydGWylfSpx5Sy4zoPoJEH2GGtlt7lnHUKEs HBLw== X-Gm-Message-State: AGi0PubiSyG9wq22C/pDQRBYXW8pbHFiqxq+Zh8oRoBFH/MRkyvTmuvx F/CF93sqzu/pI4RTgcMckCjvvkM0JA6uFJWqweqisrnguStB8ePAQaGm6lKDHetGSP1HbRiYkS5 pcVBOZgOvv8sYroI= X-Received: by 2002:a1c:154:: with SMTP id 81mr4819469wmb.48.1587475173853; Tue, 21 Apr 2020 06:19:33 -0700 (PDT) X-Google-Smtp-Source: APiQypLHPuElbADy4mspBGKtfKCwZM91kYTJTe3uodBw9u/qXg53Z5lnxWy+W/ZDj504BwBLoLYMkQ== X-Received: by 2002:a1c:154:: with SMTP id 81mr4819454wmb.48.1587475173622; Tue, 21 Apr 2020 06:19:33 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 1/6] target/arm: Restric the Address Translate write operation to TCG accel Date: Tue, 21 Apr 2020 15:19:21 +0200 Message-Id: <20200421131926.12116-2-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200421131926.12116-1-philmd@redhat.com> References: <20200421131926.12116-1-philmd@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.139.110.120; envelope-from=philmd@redhat.com; helo=us-smtp-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/21 03:31:23 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8"; text/plain; charset="utf-8" Under KVM these registers are written by the hardware. Restrict the writefn handlers to TCG to avoid when building without TCG: LINK aarch64-softmmu/qemu-system-aarch64 target/arm/helper.o: In function `do_ats_write': target/arm/helper.c:3524: undefined reference to `raise_exception' Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- Better explanation: https://www.mail-archive.com/qemu-devel@nongnu.org/msg689388.html --- target/arm/helper.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7e9ea5d20f..dfefb9b3d9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3442,6 +3442,7 @@ static CPAccessResult ats_access(CPUARMState *env, co= nst ARMCPRegInfo *ri, return CP_ACCESS_OK; } =20 +#ifdef CONFIG_TCG static uint64_t do_ats_write(CPUARMState *env, uint64_t value, MMUAccessType access_type, ARMMMUIdx mmu_idx) { @@ -3602,9 +3603,11 @@ static uint64_t do_ats_write(CPUARMState *env, uint6= 4_t value, } return par64; } +#endif /* CONFIG_TCG */ =20 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) { +#ifdef CONFIG_TCG MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA= _LOAD; uint64_t par64; ARMMMUIdx mmu_idx; @@ -3664,17 +3667,26 @@ static void ats_write(CPUARMState *env, const ARMCP= RegInfo *ri, uint64_t value) par64 =3D do_ats_write(env, value, access_type, mmu_idx); =20 A32_BANKED_CURRENT_REG_SET(env, par, par64); +#else + /* Handled by hardware accelerator. */ + g_assert_not_reached(); +#endif /* CONFIG_TCG */ } =20 static void ats1h_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { +#ifdef CONFIG_TCG MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA= _LOAD; uint64_t par64; =20 par64 =3D do_ats_write(env, value, access_type, ARMMMUIdx_E2); =20 A32_BANKED_CURRENT_REG_SET(env, par, par64); +#else + /* Handled by hardware accelerator. */ + g_assert_not_reached(); +#endif /* CONFIG_TCG */ } =20 static CPAccessResult at_s1e2_access(CPUARMState *env, const ARMCPRegInfo = *ri, @@ -3689,6 +3701,7 @@ static CPAccessResult at_s1e2_access(CPUARMState *env= , const ARMCPRegInfo *ri, static void ats_write64(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { +#ifdef CONFIG_TCG MMUAccessType access_type =3D ri->opc2 & 1 ? MMU_DATA_STORE : MMU_DATA= _LOAD; ARMMMUIdx mmu_idx; int secure =3D arm_is_secure_below_el3(env); @@ -3728,6 +3741,10 @@ static void ats_write64(CPUARMState *env, const ARMC= PRegInfo *ri, } =20 env->cp15.par_el[1] =3D do_ats_write(env, value, access_type, mmu_idx); +#else + /* Handled by hardware accelerator. */ + g_assert_not_reached(); +#endif /* CONFIG_TCG */ } #endif =20 --=20 2.21.1 From nobody Sat May 18 13:16:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1587475270; cv=none; d=zohomail.com; s=zohoarc; b=H2/ZeICqD2sXA3BBzDD1IAUZNk5Eiw3QWx5l+YaNydijBFZ1SvS7LoKqkLBf/yWlcX47JTYus37h0ifmJiJKNmtlp6KFpOVNsxN6/J7NJsGJlS6XKy31GhNiIxCO500IIQeNLR3fXn7dZWop+KxptULcfdFQlb62/Kk8+zyEXgQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1587475270; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=MB+KcpzEineBQraMabNomRZxm0WGxSq/4mX06L66IW8=; b=m7nGHq5EhjLMZq7CtYHI/WBi9WrTvOsCkELputvQEqFRaRmUsQzwlSo6BEA5SO42Rw78VPgtHSTjJCGHciLVtnRe+bxOOH70mBxch+kKXo0RKHLAZ/387/U6X1+p2bTZ9Ui8BV2W43UCh7vDrIybp0WCXck1mxjh/7F82EbluK4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1587475270225816.5019300389152; Tue, 21 Apr 2020 06:21:10 -0700 (PDT) Received: from localhost ([::1]:58286 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jQspo-0002nf-I0 for importer@patchew.org; Tue, 21 Apr 2020 09:21:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48402) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jQsoS-00011t-LA for qemu-devel@nongnu.org; Tue, 21 Apr 2020 09:19:45 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.90_1) (envelope-from ) id 1jQsoR-0007Ta-Pu for qemu-devel@nongnu.org; Tue, 21 Apr 2020 09:19:44 -0400 Received: from us-smtp-delivery-1.mimecast.com ([205.139.110.120]:59601 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1jQsoR-0007Sp-DK for qemu-devel@nongnu.org; Tue, 21 Apr 2020 09:19:43 -0400 Received: from mail-wr1-f70.google.com (mail-wr1-f70.google.com [209.85.221.70]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-6-QI4TxWVBMnW-TFqYY5s2uw-1; Tue, 21 Apr 2020 09:19:41 -0400 Received: by mail-wr1-f70.google.com with SMTP id d17so7446150wrr.17 for ; Tue, 21 Apr 2020 06:19:40 -0700 (PDT) Received: from x1w.redhat.com (116.red-83-42-57.dynamicip.rima-tde.net. [83.42.57.116]) by smtp.gmail.com with ESMTPSA id j11sm3780321wrr.62.2020.04.21.06.19.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Apr 2020 06:19:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1587475182; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=MB+KcpzEineBQraMabNomRZxm0WGxSq/4mX06L66IW8=; b=KTA9XP+D9PZNyYAktUskcO13qQ0PrbRkZ9L+V6Y8YDF/LktIpzgRgrvx4oesWTjBonT5m7 rfLRk1jkRvzLQ8R0UskEyDDXcqdHH6VBO+1qyu3YHVI4sdz1j0eE6Vd5KlJ4Yspb2Aw/xu J3EbHNZXMLfH6cYuVIMfJqR4KqzHBVs= X-MC-Unique: QI4TxWVBMnW-TFqYY5s2uw-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tByUF6YONCD4gqGP4f3pAvFwLd8JVDzJFormU5gNpuE=; b=syP+VgqVmm+fKTtiYDii7RzM7CXuyV9lwwZ5Ma0VGPVGCJliGf1K1u9cA+7GTuRTAF mWAmacKx+FwBz31BPFu8w8gDPwFNbPW/GekX2CBuy+jJbrXECPk/S7ZiCP5OfUeY0Fky aUSZ489q9zUiQKI28563zF5sY/VY+OX3pCpjuFq6Ytir9xmHoJcVhqqCW7u0k+kv+Ni6 fbuhNonFcIGXOrUKBIsrBaI98x1daKcrAdqTiCqOPxyIlpXu7gC4Hjb9tDxhfvvkmgBJ NborhYRTwUJy6suKwEo4NBDk3fyZp41ndJc4xBX0wAu2Q5jq48g9y4oC+S/OFtOlxfXo 4YOQ== X-Gm-Message-State: AGi0PubwFmB/TFCdXSSxpbmvW7CQU1NXOLWHdiyQaUPG/sN88WqufQxp +/Z5cdkt1raEV90yw4yZZ+1dRS3r7W85dF/YAmy/hdtWYWEunvUDKhMsg3OJeVtyrJWnk3+B14O PnZ0JOHmua+91DuE= X-Received: by 2002:adf:ee0c:: with SMTP id y12mr26222156wrn.0.1587475178633; Tue, 21 Apr 2020 06:19:38 -0700 (PDT) X-Google-Smtp-Source: APiQypLY7VVo0T+M1kriR9MW4uQc9UFP0hXNVeOtx8QeDV8L28NN3tVov1QD9OsVJBj0qmn/46cgPQ== X-Received: by 2002:adf:ee0c:: with SMTP id y12mr26222141wrn.0.1587475178468; Tue, 21 Apr 2020 06:19:38 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 2/6] target/arm: Make set_feature() available for other files Date: Tue, 21 Apr 2020 15:19:22 +0200 Message-Id: <20200421131926.12116-3-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200421131926.12116-1-philmd@redhat.com> References: <20200421131926.12116-1-philmd@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=205.139.110.120; envelope-from=philmd@redhat.com; helo=us-smtp-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/21 03:31:23 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , Richard Henderson , Eric Auger , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8"; text/plain; charset="utf-8" From: Thomas Huth Move the common set_feature() and unset_feature() functions from cpu.c and cpu64.c to cpu.h. Suggested-by: Peter Maydell Signed-off-by: Thomas Huth Reviewed-by: Richard Henderson Reviewed-by: Eric Auger Message-ID: <20190921150420.30743-2-thuth@redhat.com> [PMD: Split Thomas's patch in two: set_feature, cpu_register (later)] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu.h | 10 ++++++++++ target/arm/cpu.c | 10 ---------- target/arm/cpu64.c | 11 +---------- 3 files changed, 11 insertions(+), 20 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 8b9f2961ba..5e32fe7518 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -696,6 +696,16 @@ typedef struct CPUARMState { void *gicv3state; } CPUARMState; =20 +static inline void set_feature(CPUARMState *env, int feature) +{ + env->features |=3D 1ULL << feature; +} + +static inline void unset_feature(CPUARMState *env, int feature) +{ + env->features &=3D ~(1ULL << feature); +} + /** * ARMELChangeHookFn: * type of a function which can be registered via arm_register_el_change_h= ook() diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a79f233b17..37f18d1648 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -724,16 +724,6 @@ static bool arm_cpu_virtio_is_big_endian(CPUState *cs) =20 #endif =20 -static inline void set_feature(CPUARMState *env, int feature) -{ - env->features |=3D 1ULL << feature; -} - -static inline void unset_feature(CPUARMState *env, int feature) -{ - env->features &=3D ~(1ULL << feature); -} - static int print_insn_thumb1(bfd_vma pc, disassemble_info *info) { diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 62d36f9e8d..622082eae2 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "cpu.h" +#include "internals.h" #include "qemu/module.h" #if !defined(CONFIG_USER_ONLY) #include "hw/loader.h" @@ -29,16 +30,6 @@ #include "kvm_arm.h" #include "qapi/visitor.h" =20 -static inline void set_feature(CPUARMState *env, int feature) -{ - env->features |=3D 1ULL << feature; -} - -static inline void unset_feature(CPUARMState *env, int feature) -{ - env->features &=3D ~(1ULL << feature); -} - #ifndef CONFIG_USER_ONLY static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *= ri) { --=20 2.21.1 From nobody Sat May 18 13:16:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1587475284; cv=none; d=zohomail.com; s=zohoarc; b=oDS34JjHLXDtUwOU8dJTZntB48czcKXYTd/PoRUjnO3RZdLks6IQORkzHOxAneFJ83zjBFFUQ3FAfmJQM9Z0b5byB29oYWl/VlBHpTO8S6xkmWdEnnUPQRcDpvTpgzgEAeCex4QOAEnslq7xadrd6oBEo0m1ceXtu15w4GweESc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1587475284; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=F6lGB+gV2hrPr/0M/fUQbumiT1BIsGf5idBsThrgFcY=; b=SeGZadYSY2mDTij8gZXMhADBFWN9Cv4B24rwoLdzqbDP2elvi5eg8+vrCI51KBPpCNruKIDcFhtDdUX24ZniHTWIgY3DnDfPqJQk3UHpMc7Y+jp9tarXWXJrfegZuskCxpCjRDjk+w1IrL85TCE2qn+S0q/9P+F67DmExmdaU+Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1587475284785619.5680276561483; Tue, 21 Apr 2020 06:21:24 -0700 (PDT) Received: from localhost ([::1]:58294 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jQsq3-0003Gx-HF for importer@patchew.org; Tue, 21 Apr 2020 09:21:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48436) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jQsoY-0001A7-6p for qemu-devel@nongnu.org; Tue, 21 Apr 2020 09:19:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.90_1) (envelope-from ) id 1jQsoW-0007bx-E3 for qemu-devel@nongnu.org; Tue, 21 Apr 2020 09:19:48 -0400 Received: from us-smtp-delivery-1.mimecast.com ([207.211.31.120]:34076 helo=us-smtp-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1jQsoW-0007aO-09 for qemu-devel@nongnu.org; Tue, 21 Apr 2020 09:19:48 -0400 Received: from mail-wm1-f69.google.com (mail-wm1-f69.google.com [209.85.128.69]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-191-SuwlQToxPCKUfQPuVICSlw-1; Tue, 21 Apr 2020 09:19:45 -0400 Received: by mail-wm1-f69.google.com with SMTP id b203so1353483wmd.6 for ; Tue, 21 Apr 2020 06:19:45 -0700 (PDT) Received: from x1w.redhat.com (116.red-83-42-57.dynamicip.rima-tde.net. [83.42.57.116]) by smtp.gmail.com with ESMTPSA id m1sm3689226wro.64.2020.04.21.06.19.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Apr 2020 06:19:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1587475187; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=F6lGB+gV2hrPr/0M/fUQbumiT1BIsGf5idBsThrgFcY=; b=F795fu0mDuImZx9/Utrf13J3gJjUgdNxAyMvtMZ1Gux2j9RMzzl9TyTQl5z7Sxrh9yTKw3 7Hq262qjPtAmwQrEAa1Yh1gGHBuzpZbb0fW98aIdJsPxB5aSohlsfUl+3iPzM5tJopezF0 KbIUoOrPDObPsH/tRAVh3+Qzun3OZ88= X-MC-Unique: SuwlQToxPCKUfQPuVICSlw-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dS/vtbkAfNhRHkFDGLX+PdB0iniDOVA5vUlcTpqcra4=; b=daEyOaz9qakjmUgxRlJ/d0DP5o2SK77iwwIwfmiNhD74RYGczL9efNe4qmfbCz9MOg NUaMDsPtZMTrW0NJUSa43xktlyj16ioR+btiZC4RYvLyTGq7Y2JqDKU+Dy4ZrmTQZ7/e PxbJ3nPa5vjW4Xjv69kPPzbfriVfh7YKSvvcZ2HrfgOrmdS1/2AxLXe5TTsnY6BjpNOb 2DlY0yxBZTauMvjXnG5sfEUWQw4T5h+A6jVFTwm4lJnE2/NcX/BLKaEqH2/+A0npwXNy Gv5lXlYgWfnhI8M5vEeqo7ZRQEa/GVUOeVRnrlUp//EgPo8EB1h41P4oxQ0Gq6BGZuRO P1uQ== X-Gm-Message-State: AGi0Puanfygpv+qLqAl4usNo8Qc62+o/KR5fZtolUeBfGMyAgt/RFf7v blcuDpUEsWZ33ckLKYfSCIR6WoU0BtLJJpuQu8IzFmWe7i5+kRjXgzs5XGQxFclVhcGezTtx49u dqE2ZZpW/LFcZj7w= X-Received: by 2002:a5d:640a:: with SMTP id z10mr18445528wru.280.1587475183474; Tue, 21 Apr 2020 06:19:43 -0700 (PDT) X-Google-Smtp-Source: APiQypK4guldDk+QQqsJDxrv++UW6HSamXV9/89Lude0W71xIS6NLVELt9/oOzIjYYyfZYhVfagNog== X-Received: by 2002:a5d:640a:: with SMTP id z10mr18445510wru.280.1587475183303; Tue, 21 Apr 2020 06:19:43 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 3/6] target/arm: Make cpu_register() available for other files Date: Tue, 21 Apr 2020 15:19:23 +0200 Message-Id: <20200421131926.12116-4-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200421131926.12116-1-philmd@redhat.com> References: <20200421131926.12116-1-philmd@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=207.211.31.120; envelope-from=philmd@redhat.com; helo=us-smtp-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/21 04:54:00 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , Thomas Huth , Richard Henderson , Eric Auger , qemu-arm@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8"; text/plain; charset="utf-8" From: Thomas Huth Make cpu_register() (renamed to arm_cpu_register()) available from internals.h so we can register CPUs also from other files in the future. Signed-off-by: Thomas Huth Reviewed-by: Richard Henderson Reviewed-by: Eric Auger Message-ID: <20190921150420.30743-2-thuth@redhat.com> [PMD: Split Thomas's patch in two: set_feature (earlier), cpu_register] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu-qom.h | 9 ++++++++- target/arm/cpu.c | 10 ++-------- target/arm/cpu64.c | 8 +------- 3 files changed, 11 insertions(+), 16 deletions(-) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index d95568bf05..56395b87f6 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -35,7 +35,14 @@ struct arm_boot_info; =20 #define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU =20 -typedef struct ARMCPUInfo ARMCPUInfo; +typedef struct ARMCPUInfo { + const char *name; + void (*initfn)(Object *obj); + void (*class_init)(ObjectClass *oc, void *data); +} ARMCPUInfo; + +void arm_cpu_register(const ARMCPUInfo *info); +void aarch64_cpu_register(const ARMCPUInfo *info); =20 /** * ARMCPUClass: diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 37f18d1648..6c84e99a38 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2683,12 +2683,6 @@ static void arm_max_initfn(Object *obj) =20 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ =20 -struct ARMCPUInfo { - const char *name; - void (*initfn)(Object *obj); - void (*class_init)(ObjectClass *oc, void *data); -}; - static const ARMCPUInfo arm_cpus[] =3D { #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) { .name =3D "arm926", .initfn =3D arm926_initfn }, @@ -2854,7 +2848,7 @@ static void cpu_register_class_init(ObjectClass *oc, = void *data) acc->info =3D data; } =20 -static void cpu_register(const ARMCPUInfo *info) +void arm_cpu_register(const ARMCPUInfo *info) { TypeInfo type_info =3D { .parent =3D TYPE_ARM_CPU, @@ -2895,7 +2889,7 @@ static void arm_cpu_register_types(void) type_register_static(&idau_interface_type_info); =20 while (info->name) { - cpu_register(info); + arm_cpu_register(info); info++; } =20 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 622082eae2..e89388378b 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -728,12 +728,6 @@ static void aarch64_max_initfn(Object *obj) cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal); } =20 -struct ARMCPUInfo { - const char *name; - void (*initfn)(Object *obj); - void (*class_init)(ObjectClass *oc, void *data); -}; - static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a57", .initfn =3D aarch64_a57_initfn }, { .name =3D "cortex-a53", .initfn =3D aarch64_a53_initfn }, @@ -816,7 +810,7 @@ static void cpu_register_class_init(ObjectClass *oc, vo= id *data) acc->info =3D data; } =20 -static void aarch64_cpu_register(const ARMCPUInfo *info) +void aarch64_cpu_register(const ARMCPUInfo *info) { TypeInfo type_info =3D { .parent =3D TYPE_AARCH64_CPU, --=20 2.21.1 From nobody Sat May 18 13:16:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1587475390; cv=none; d=zohomail.com; s=zohoarc; b=EAT3kNhlO2oAm+fkaEcnzgRPaiyWAz38ZPGeNBt/K3X+z777uH0fTYD6ivGQYODB/zS7ERTUbWAQp/+recp3XtL/011LY9S8huSSYpqLaxjuJ1em3bJjdRLZOlombKX1bZsXlajPcoQl9wZySUfgpHzVe4ZsfM/Ui6DmA0+wq+g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1587475390; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qfG1iMoMuVJK3ytJuPp4jkcsIuLSkap1NwXNvJU0GUg=; b=I6Jn0l+c9nUJMktNtbFp0hwIrk6s6UBkGMTpuWwuBydNBSGNzqEhWfCNq/jw0/BotvHdvRyVabs+zIeQeuNQ0yXelOPRXCvfWxZeoKIb4K4sgfmrAh6yOq6AFZW9Xk2oEsuFTahm1AqJ1EpQKvWaH7U4gvhU7pVwYv1aF3p18P8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1587475390165363.83377704413635; Tue, 21 Apr 2020 06:23:10 -0700 (PDT) Received: from localhost ([::1]:58322 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jQsrk-0005tj-UZ for importer@patchew.org; Tue, 21 Apr 2020 09:23:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48484) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jQsob-0001Gt-Mx for qemu-devel@nongnu.org; Tue, 21 Apr 2020 09:19:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.90_1) (envelope-from ) id 1jQsob-0007k3-2G for qemu-devel@nongnu.org; Tue, 21 Apr 2020 09:19:53 -0400 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:43705 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1jQsoa-0007ei-LJ for qemu-devel@nongnu.org; Tue, 21 Apr 2020 09:19:52 -0400 Received: from mail-wr1-f70.google.com (mail-wr1-f70.google.com [209.85.221.70]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-145-W7h8QfvDPuSKiMbXVDAFFQ-1; Tue, 21 Apr 2020 09:19:49 -0400 Received: by mail-wr1-f70.google.com with SMTP id m5so7459070wru.15 for ; Tue, 21 Apr 2020 06:19:49 -0700 (PDT) Received: from x1w.redhat.com (116.red-83-42-57.dynamicip.rima-tde.net. [83.42.57.116]) by smtp.gmail.com with ESMTPSA id q184sm3549887wma.25.2020.04.21.06.19.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Apr 2020 06:19:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1587475191; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qfG1iMoMuVJK3ytJuPp4jkcsIuLSkap1NwXNvJU0GUg=; b=I828JxlhqWpiHP91/W7hiQrC6LAMtFc3NtNsNPvP35vH4iaD4u3AvfbjOwbknzOz985Qgc nhCcNblcZXup2Xr51VM0Dt9lzvY1C3MDzpQWHBN06+e8NSnYCKek1cvgblauU5tpV+YcxP Q9+Rt3ghqh57DiQBBOfMOc0cZHw8f9I= X-MC-Unique: W7h8QfvDPuSKiMbXVDAFFQ-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=A6xQD+3rOPF5ujK6YzLWEuyxUGl4uZx+Lu/2zv1O3wM=; b=kkJ1WflIoATLcfFHKzcPih8jQpk3HgVwsvKYJkiO3adOYC96oRhsQCXR37qen8qDJZ OGsjI9gNVm7ywGc1B/nUu8evBxLnPHJVXtn/qKs2tJ7XZZNcqMp7xgqSw4NumpMf67Pc Nr/NBG5DRNc77S7USORx6jSMIP2TeCBrtmL4alTIx+LAAR90pK4YNKj0NuLKIlpCjezC d0yRKHWgKeJYzcoEKBf3efVaCTKrymAQCa+U76FC64y5tVh7Xs8pd/7wZjsjNGyBQwO5 9y7zhCZaoiaKiPV6alxkzPpwyvVMKkQDb451PnIsFw8/zhV99g+WXgsRcV3hzdvdIbWs JGrA== X-Gm-Message-State: AGi0PuaOfjsj8UAuNBdLyQ+En/LHJp6kOJfyEJvCGrrRfKSfxyaDmFHA H9At4EAFA4CnKLbaAckvxIKktiu2YR0T6hf3w9kTHBE8FyUTc0roBaKIf11TNSj3wMGJU21qP8g 9ts5W0lpq8m+EN74= X-Received: by 2002:adf:aad4:: with SMTP id i20mr20368771wrc.47.1587475188189; Tue, 21 Apr 2020 06:19:48 -0700 (PDT) X-Google-Smtp-Source: APiQypKQ45wjdIi2JB7mTGs5QgEoycKoGnml4/LCG6bAVS7Yhekx7ffdfLPkoBCKsiqu3f0PLxQrAQ== X-Received: by 2002:adf:aad4:: with SMTP id i20mr20368754wrc.47.1587475187984; Tue, 21 Apr 2020 06:19:47 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 4/6] target/arm/cpu: Use ARRAY_SIZE() to iterate over ARMCPUInfo[] Date: Tue, 21 Apr 2020 15:19:24 +0200 Message-Id: <20200421131926.12116-5-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200421131926.12116-1-philmd@redhat.com> References: <20200421131926.12116-1-philmd@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=207.211.31.81; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/21 01:28:51 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8"; text/plain; charset="utf-8" Suggested-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/cpu.c | 8 +++----- target/arm/cpu64.c | 8 +++----- 2 files changed, 6 insertions(+), 10 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6c84e99a38..9023d9e2cf 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2735,7 +2735,6 @@ static const ARMCPUInfo arm_cpus[] =3D { { .name =3D "any", .initfn =3D arm_max_initfn }, #endif #endif - { .name =3D NULL } }; =20 static Property arm_cpu_properties[] =3D { @@ -2883,14 +2882,13 @@ static const TypeInfo idau_interface_type_info =3D { =20 static void arm_cpu_register_types(void) { - const ARMCPUInfo *info =3D arm_cpus; + size_t i; =20 type_register_static(&arm_cpu_type_info); type_register_static(&idau_interface_type_info); =20 - while (info->name) { - arm_cpu_register(info); - info++; + for (i =3D 0; i < ARRAY_SIZE(arm_cpus); ++i) { + arm_cpu_register(&arm_cpus[i]); } =20 #ifdef CONFIG_KVM diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index e89388378b..5daafba937 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -733,7 +733,6 @@ static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a53", .initfn =3D aarch64_a53_initfn }, { .name =3D "cortex-a72", .initfn =3D aarch64_a72_initfn }, { .name =3D "max", .initfn =3D aarch64_max_initfn }, - { .name =3D NULL } }; =20 static bool aarch64_cpu_get_aarch64(Object *obj, Error **errp) @@ -839,13 +838,12 @@ static const TypeInfo aarch64_cpu_type_info =3D { =20 static void aarch64_cpu_register_types(void) { - const ARMCPUInfo *info =3D aarch64_cpus; + size_t i; =20 type_register_static(&aarch64_cpu_type_info); =20 - while (info->name) { - aarch64_cpu_register(info); - info++; + for (i =3D 0; i < ARRAY_SIZE(aarch64_cpus); ++i) { + aarch64_cpu_register(&aarch64_cpus[i]); } } =20 --=20 2.21.1 From nobody Sat May 18 13:16:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1587475463; cv=none; d=zohomail.com; s=zohoarc; b=NtNegugKgoRNsyTDRMlC2upVl1Ix+cDDlYPZA6xnoowdO3ntxhjXc+5tYzwPN6Wnq5vJ1eesvdN1sKneoTo+kq9qIaJ66M6Ac0EEsRqqrG6uXCZshKPpdVU1bfKbV7prG2R6GE+GDD1+FaA0iKWhKZeeZbo87jL/rI0WeNJBHkY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1587475463; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pU9wiDrqb1FbUODn1z0R5OZvX82oaKZlJ+qXZZecY0U=; b=cb5F7iunIMGL6WqGSJP007fW7moIgCVEaPiJOyzCOssxolhboDqDEmod3fcBxPn5F8fkPLTy8h0/v32Ix+3KTFio4H9L6BXsV6j0oXiIFrg6OXQEPaqxKTspQ4ZZ6UlJ/N83eMjhec3qb45rZKOlCDn7o6YgrKnTp2QXiPAFfQk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1587475463797330.61474563690865; Tue, 21 Apr 2020 06:24:23 -0700 (PDT) Received: from localhost ([::1]:58356 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jQssw-0007bE-L9 for importer@patchew.org; Tue, 21 Apr 2020 09:24:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48532) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jQsoh-0001Qk-6k for qemu-devel@nongnu.org; Tue, 21 Apr 2020 09:20:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.90_1) (envelope-from ) id 1jQsog-0007sB-5I for qemu-devel@nongnu.org; Tue, 21 Apr 2020 09:19:58 -0400 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:42063 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1jQsoe-0007px-NV for qemu-devel@nongnu.org; Tue, 21 Apr 2020 09:19:57 -0400 Received: from mail-wm1-f71.google.com (mail-wm1-f71.google.com [209.85.128.71]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-341-cv26NbiHMpWrg9RP8jQbmg-1; Tue, 21 Apr 2020 09:19:54 -0400 Received: by mail-wm1-f71.google.com with SMTP id l21so1443584wmh.2 for ; Tue, 21 Apr 2020 06:19:54 -0700 (PDT) Received: from x1w.redhat.com (116.red-83-42-57.dynamicip.rima-tde.net. [83.42.57.116]) by smtp.gmail.com with ESMTPSA id y10sm3395269wma.5.2020.04.21.06.19.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Apr 2020 06:19:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1587475196; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=pU9wiDrqb1FbUODn1z0R5OZvX82oaKZlJ+qXZZecY0U=; b=UjttNA5JE4WsRwj3ywUDZc2Pz+325cotcMVNFGmrIcTRLL/buJh8OETAPiNMMeXl7PP+Ce 86uysHToH+nBiZ1cz8PHSg5sRp5O6U+2BBBvqTlcavDKonyyn7yUYi2kWmJ17ZpDbrjb5V EviFvPkqa26/70Xo+IRHJDvgBrotEeg= X-MC-Unique: cv26NbiHMpWrg9RP8jQbmg-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Zqzb/pshEzW1fPo5MmdJgyS/wpMg+nvvsoa+3p+thQ0=; b=ekjQ3M7iKWg4bLD1vzkq6VzqVtWHWqbqBFdA4wZz3391Hg69eG6m8gtbJuFfuVUdbP zJpWw6duQY92jLoU5V9ocuQvyQ8woyIAFUzadI2kVQ0Db39HFIc50x67U9us/BQ/gCyX CxTQAhhCFAexlTDoi85yCObJHJh/gUYNGOBessePaC6DkGk8roZzDmJblHORP1OzrPhB 1W48mc4YJbk14gUfRpTYMlmZ6WRhKypw+pQhrT/GEF8zVL6fAw1sFOp6vhSNk+bbSjwJ ElhWrdmVc/hguek6I4IDZ35qvIZkP3JWXD3GJ703688JVd7I7hDxwXQX4nnvhouTreMA xgJg== X-Gm-Message-State: AGi0PubipywO28iiZiEORgKXgKlUWhdvcHs7XGFjo1WUBzSCJe6og5mo Lcldilcyq8VwM7i+p1qYHDUykz+q7TWl6WTCPfLQvDpDSNDr0fMKjEyilWkHZYetexTdlKYRMV5 Qkcbqkv9ocDpqSB0= X-Received: by 2002:adf:e282:: with SMTP id v2mr24137576wri.329.1587475193001; Tue, 21 Apr 2020 06:19:53 -0700 (PDT) X-Google-Smtp-Source: APiQypJi8RM6ZFcZImP1v+szj5GX0ylJ5Ta9bTGS/vimyu/dAjz0CEoRCbjwXiMnWKdnATOybQwPIQ== X-Received: by 2002:adf:e282:: with SMTP id v2mr24137559wri.329.1587475192830; Tue, 21 Apr 2020 06:19:52 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 5/6] target/arm/cpu: Update coding style to make checkpatch.pl happy Date: Tue, 21 Apr 2020 15:19:25 +0200 Message-Id: <20200421131926.12116-6-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200421131926.12116-1-philmd@redhat.com> References: <20200421131926.12116-1-philmd@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=207.211.31.81; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/21 01:28:51 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8"; text/plain; charset="utf-8" We will move this code in the next commit. Clean it up first to avoid checkpatch.pl errors. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- target/arm/cpu.c | 9 ++++++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 9023d9e2cf..1ddf850f00 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -582,7 +582,8 @@ static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, in= t interrupt_request) CPUARMState *env =3D &cpu->env; bool ret =3D false; =20 - /* ARMv7-M interrupt masking works differently than -A or -R. + /* + * ARMv7-M interrupt masking works differently than -A or -R. * There is no FIQ/IRQ distinction. Instead of I and F bits * masking FIQ and IRQ interrupts, an exception is taken only * if it is higher priority than the current execution priority @@ -1902,7 +1903,8 @@ static void arm1026_initfn(Object *obj) static void arm1136_r2_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); - /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an + /* + * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an * older core than plain "arm1136". In particular this does not * have the v6K features. * These ID register values are correct for 1136 but may be wrong @@ -2688,7 +2690,8 @@ static const ARMCPUInfo arm_cpus[] =3D { { .name =3D "arm926", .initfn =3D arm926_initfn }, { .name =3D "arm946", .initfn =3D arm946_initfn }, { .name =3D "arm1026", .initfn =3D arm1026_initfn }, - /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an + /* + * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an * older core than plain "arm1136". In particular this does not * have the v6K features. */ --=20 2.21.1 From nobody Sat May 18 13:16:33 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1587475384; cv=none; d=zohomail.com; s=zohoarc; b=XsoQkpuOh2K1PhFF6kkeNeU+0s8ZUKjUTJgybCC9/dKvW1KIHy9oqC8QsILIHX2RMScCnlWPTD6HZHIke1G7CLS9ZVIpPX+UobhUHG5mFGP9uk/MUeHarw+fLKDxjL0PL1qofKSR9suoc0GFrpS5O003xdOst1ZYcynUzm6/Fmw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1587475384; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=FzwPOMqdtZSYdT32firlVy7PjpXciFCNA9agXuINWnc=; b=kEKpRs2pR7i4DjyHQ7r6pz27U5T5TNOpbRRs/0XfA+bkRV/1X7viTQHmHKzKhVhUQhvApPxGbeGLfqzA91XfXV/jHB4SVMfVLAqYskpbfoDFtfBXeJ0l1gpCU8e/zezQYTSF4JfwTuM0YfRGcAUvCTdltlXmoArFvPfowBRpTtw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 158747538412157.786084776902385; Tue, 21 Apr 2020 06:23:04 -0700 (PDT) Received: from localhost ([::1]:58318 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jQsre-0005eZ-Q0 for importer@patchew.org; Tue, 21 Apr 2020 09:23:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48568) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jQsop-0001h1-62 for qemu-devel@nongnu.org; Tue, 21 Apr 2020 09:20:10 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.90_1) (envelope-from ) id 1jQsom-00085W-Jq for qemu-devel@nongnu.org; Tue, 21 Apr 2020 09:20:06 -0400 Received: from us-smtp-1.mimecast.com ([207.211.31.81]:56724 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1jQsom-00083s-2c for qemu-devel@nongnu.org; Tue, 21 Apr 2020 09:20:04 -0400 Received: from mail-wm1-f70.google.com (mail-wm1-f70.google.com [209.85.128.70]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-399-D6vGFOAoM3WBH7E0zOTkRw-1; Tue, 21 Apr 2020 09:20:01 -0400 Received: by mail-wm1-f70.google.com with SMTP id o26so1369065wmh.1 for ; Tue, 21 Apr 2020 06:20:01 -0700 (PDT) Received: from x1w.redhat.com (116.red-83-42-57.dynamicip.rima-tde.net. [83.42.57.116]) by smtp.gmail.com with ESMTPSA id z10sm3851877wrg.69.2020.04.21.06.19.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Apr 2020 06:19:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1587475203; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=FzwPOMqdtZSYdT32firlVy7PjpXciFCNA9agXuINWnc=; b=CS/mhPhJarpB6vRkSsLuzL5qlosKXN08NqrXqa3ePIG+jVaot2WRl/N+VJ4sH7OSTmow7Y Psuae9f8LGmBxB1iKuKLb5WaIiKiYoamIhIrib/bRHCwVXNX7dIoAkLFIk/prW2s5gDH47 kedSuJ1xcyk+LItTjhBvPSAlGdqyF/c= X-MC-Unique: D6vGFOAoM3WBH7E0zOTkRw-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oU7W4nI0AW+Rq2I20Q1jXQJWNo5D7Q0B6oX5KyGq0vY=; b=WgmDnEHTEVr5WDYb4kJv6U7B9U+O0PSPL8u3bdCXC3NPeqCBdSBzAf6e01EV8NIAeU pMO0eRPfvso4GIOvDmFhbtoeLFOAazXLxtRbrymkFHVrN5WCznUakrw2lzhcjUCRSJtd GVHLXlMoSZySvHkf17FGEy4d/NLE/G3QMOU0SPay+mtCKMuCu0WFzLQHJkB3+eRpa/PL L4MSTqHKAKdmaL0eFSStasylmRYBqRP7FSkV2lnShPpqLDBzWXne7uUEtCAF4Xu9cJ4r mswuIEt3oOlIuVpIeSohUF51PRcypKX0+5V962p23fficu549c0+tkAYUTqIUNXbq72w lz4Q== X-Gm-Message-State: AGi0PuYUjesLgPa/uEVabB4huF1i9Zi1uvaQKy82gnJB5LBf9l7ud3ri rKIf0XXt+5ktoRWPlgvEgXb2JfV1lxiaV+8xMspdnwZBneRtqQ3VhhyMOhRzgon0AoSBDYL5J/O 73WuZqUl6PZT7Itw= X-Received: by 2002:adf:decb:: with SMTP id i11mr23147908wrn.140.1587475199042; Tue, 21 Apr 2020 06:19:59 -0700 (PDT) X-Google-Smtp-Source: APiQypJ+TgoEiT99/aGLwwWjEMcDPH7HmE4Xm6BGQxAVoTreIQHN/swEbzsB0uB1uJZDkiY8sR4a2g== X-Received: by 2002:adf:decb:: with SMTP id i11mr23147849wrn.140.1587475198069; Tue, 21 Apr 2020 06:19:58 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH 6/6] target/arm: Restrict TCG cpus to TCG accel Date: Tue, 21 Apr 2020 15:19:26 +0200 Message-Id: <20200421131926.12116-7-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200421131926.12116-1-philmd@redhat.com> References: <20200421131926.12116-1-philmd@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=207.211.31.81; envelope-from=philmd@redhat.com; helo=us-smtp-delivery-1.mimecast.com X-detected-operating-system: by eggs.gnu.org: First seen = 2020/04/21 01:28:51 X-ACL-Warn: Detected OS = Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8"; text/plain; charset="utf-8" A KVM-only build won't be able to run TCG cpus. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- This patch review is funnier using: 'git-diff --color-moved=3Ddimmed-zebra' --- target/arm/cpu.c | 634 ------------------------------------- target/arm/cpu_tcg.c | 663 +++++++++++++++++++++++++++++++++++++++ target/arm/Makefile.objs | 1 + 3 files changed, 664 insertions(+), 634 deletions(-) create mode 100644 target/arm/cpu_tcg.c diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1ddf850f00..92d90f0925 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -574,32 +574,6 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) return true; } =20 -#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) -static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) -{ - CPUClass *cc =3D CPU_GET_CLASS(cs); - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - bool ret =3D false; - - /* - * ARMv7-M interrupt masking works differently than -A or -R. - * There is no FIQ/IRQ distinction. Instead of I and F bits - * masking FIQ and IRQ interrupts, an exception is taken only - * if it is higher priority than the current execution priority - * (which depends on state like BASEPRI, FAULTMASK and the - * currently active exception). - */ - if (interrupt_request & CPU_INTERRUPT_HARD - && (armv7m_nvic_can_take_pending_exception(env->nvic))) { - cs->exception_index =3D EXCP_IRQ; - cc->do_interrupt(cs); - ret =3D true; - } - return ret; -} -#endif - void arm_cpu_update_virq(ARMCPU *cpu) { /* @@ -1820,406 +1794,6 @@ static ObjectClass *arm_cpu_class_by_name(const cha= r *cpu_model) /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) =20 -static void arm926_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,arm926"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); - cpu->midr =3D 0x41069265; - cpu->reset_fpsid =3D 0x41011090; - cpu->ctr =3D 0x1dd20d2; - cpu->reset_sctlr =3D 0x00090078; - - /* - * ARMv5 does not have the ID_ISAR registers, but we can still - * set the field to indicate Jazelle support within QEMU. - */ - cpu->isar.id_isar1 =3D FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELL= E, 1); - /* - * Similarly, we need to set MVFR0 fields to enable vfp and short vect= or - * support even though ARMv5 doesn't have this register. - */ - cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); - cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); - cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); -} - -static void arm946_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,arm946"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_PMSA); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - cpu->midr =3D 0x41059461; - cpu->ctr =3D 0x0f004006; - cpu->reset_sctlr =3D 0x00000078; -} - -static void arm1026_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,arm1026"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_AUXCR); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); - cpu->midr =3D 0x4106a262; - cpu->reset_fpsid =3D 0x410110a0; - cpu->ctr =3D 0x1dd20d2; - cpu->reset_sctlr =3D 0x00090078; - cpu->reset_auxcr =3D 1; - - /* - * ARMv5 does not have the ID_ISAR registers, but we can still - * set the field to indicate Jazelle support within QEMU. - */ - cpu->isar.id_isar1 =3D FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELL= E, 1); - /* - * Similarly, we need to set MVFR0 fields to enable vfp and short vect= or - * support even though ARMv5 doesn't have this register. - */ - cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); - cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); - cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); - - { - /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0= ,2 */ - ARMCPRegInfo ifar =3D { - .name =3D "IFAR", .cp =3D 15, .crn =3D 6, .crm =3D 0, .opc1 = =3D 0, .opc2 =3D 1, - .access =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.ifar_ns), - .resetvalue =3D 0 - }; - define_one_arm_cp_reg(cpu, &ifar); - } -} - -static void arm1136_r2_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - /* - * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an - * older core than plain "arm1136". In particular this does not - * have the v6K features. - * These ID register values are correct for 1136 but may be wrong - * for 1136_r2 (in particular r0p2 does not actually implement most - * of the ID registers). - */ - - cpu->dtb_compatible =3D "arm,arm1136"; - set_feature(&cpu->env, ARM_FEATURE_V6); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); - set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); - cpu->midr =3D 0x4107b362; - cpu->reset_fpsid =3D 0x410120b4; - cpu->isar.mvfr0 =3D 0x11111111; - cpu->isar.mvfr1 =3D 0x00000000; - cpu->ctr =3D 0x1dd20d2; - cpu->reset_sctlr =3D 0x00050078; - cpu->id_pfr0 =3D 0x111; - cpu->id_pfr1 =3D 0x1; - cpu->isar.id_dfr0 =3D 0x2; - cpu->id_afr0 =3D 0x3; - cpu->isar.id_mmfr0 =3D 0x01130003; - cpu->isar.id_mmfr1 =3D 0x10030302; - cpu->isar.id_mmfr2 =3D 0x01222110; - cpu->isar.id_isar0 =3D 0x00140011; - cpu->isar.id_isar1 =3D 0x12002111; - cpu->isar.id_isar2 =3D 0x11231111; - cpu->isar.id_isar3 =3D 0x01102131; - cpu->isar.id_isar4 =3D 0x141; - cpu->reset_auxcr =3D 7; -} - -static void arm1136_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,arm1136"; - set_feature(&cpu->env, ARM_FEATURE_V6K); - set_feature(&cpu->env, ARM_FEATURE_V6); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); - set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); - cpu->midr =3D 0x4117b363; - cpu->reset_fpsid =3D 0x410120b4; - cpu->isar.mvfr0 =3D 0x11111111; - cpu->isar.mvfr1 =3D 0x00000000; - cpu->ctr =3D 0x1dd20d2; - cpu->reset_sctlr =3D 0x00050078; - cpu->id_pfr0 =3D 0x111; - cpu->id_pfr1 =3D 0x1; - cpu->isar.id_dfr0 =3D 0x2; - cpu->id_afr0 =3D 0x3; - cpu->isar.id_mmfr0 =3D 0x01130003; - cpu->isar.id_mmfr1 =3D 0x10030302; - cpu->isar.id_mmfr2 =3D 0x01222110; - cpu->isar.id_isar0 =3D 0x00140011; - cpu->isar.id_isar1 =3D 0x12002111; - cpu->isar.id_isar2 =3D 0x11231111; - cpu->isar.id_isar3 =3D 0x01102131; - cpu->isar.id_isar4 =3D 0x141; - cpu->reset_auxcr =3D 7; -} - -static void arm1176_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,arm1176"; - set_feature(&cpu->env, ARM_FEATURE_V6K); - set_feature(&cpu->env, ARM_FEATURE_VAPA); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); - set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); - set_feature(&cpu->env, ARM_FEATURE_EL3); - cpu->midr =3D 0x410fb767; - cpu->reset_fpsid =3D 0x410120b5; - cpu->isar.mvfr0 =3D 0x11111111; - cpu->isar.mvfr1 =3D 0x00000000; - cpu->ctr =3D 0x1dd20d2; - cpu->reset_sctlr =3D 0x00050078; - cpu->id_pfr0 =3D 0x111; - cpu->id_pfr1 =3D 0x11; - cpu->isar.id_dfr0 =3D 0x33; - cpu->id_afr0 =3D 0; - cpu->isar.id_mmfr0 =3D 0x01130003; - cpu->isar.id_mmfr1 =3D 0x10030302; - cpu->isar.id_mmfr2 =3D 0x01222100; - cpu->isar.id_isar0 =3D 0x0140011; - cpu->isar.id_isar1 =3D 0x12002111; - cpu->isar.id_isar2 =3D 0x11231121; - cpu->isar.id_isar3 =3D 0x01102131; - cpu->isar.id_isar4 =3D 0x01141; - cpu->reset_auxcr =3D 7; -} - -static void arm11mpcore_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,arm11mpcore"; - set_feature(&cpu->env, ARM_FEATURE_V6K); - set_feature(&cpu->env, ARM_FEATURE_VAPA); - set_feature(&cpu->env, ARM_FEATURE_MPIDR); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - cpu->midr =3D 0x410fb022; - cpu->reset_fpsid =3D 0x410120b4; - cpu->isar.mvfr0 =3D 0x11111111; - cpu->isar.mvfr1 =3D 0x00000000; - cpu->ctr =3D 0x1d192992; /* 32K icache 32K dcache */ - cpu->id_pfr0 =3D 0x111; - cpu->id_pfr1 =3D 0x1; - cpu->isar.id_dfr0 =3D 0; - cpu->id_afr0 =3D 0x2; - cpu->isar.id_mmfr0 =3D 0x01100103; - cpu->isar.id_mmfr1 =3D 0x10020302; - cpu->isar.id_mmfr2 =3D 0x01222000; - cpu->isar.id_isar0 =3D 0x00100011; - cpu->isar.id_isar1 =3D 0x12002111; - cpu->isar.id_isar2 =3D 0x11221011; - cpu->isar.id_isar3 =3D 0x01102131; - cpu->isar.id_isar4 =3D 0x141; - cpu->reset_auxcr =3D 1; -} - -static void cortex_m0_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - set_feature(&cpu->env, ARM_FEATURE_V6); - set_feature(&cpu->env, ARM_FEATURE_M); - - cpu->midr =3D 0x410cc200; -} - -static void cortex_m3_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_M); - set_feature(&cpu->env, ARM_FEATURE_M_MAIN); - cpu->midr =3D 0x410fc231; - cpu->pmsav7_dregion =3D 8; - cpu->id_pfr0 =3D 0x00000030; - cpu->id_pfr1 =3D 0x00000200; - cpu->isar.id_dfr0 =3D 0x00100000; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x00000030; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x00000000; - cpu->isar.id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01141110; - cpu->isar.id_isar1 =3D 0x02111000; - cpu->isar.id_isar2 =3D 0x21112231; - cpu->isar.id_isar3 =3D 0x01111110; - cpu->isar.id_isar4 =3D 0x01310102; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; -} - -static void cortex_m4_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_M); - set_feature(&cpu->env, ARM_FEATURE_M_MAIN); - set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); - cpu->midr =3D 0x410fc240; /* r0p0 */ - cpu->pmsav7_dregion =3D 8; - cpu->isar.mvfr0 =3D 0x10110021; - cpu->isar.mvfr1 =3D 0x11000011; - cpu->isar.mvfr2 =3D 0x00000000; - cpu->id_pfr0 =3D 0x00000030; - cpu->id_pfr1 =3D 0x00000200; - cpu->isar.id_dfr0 =3D 0x00100000; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x00000030; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x00000000; - cpu->isar.id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01141110; - cpu->isar.id_isar1 =3D 0x02111000; - cpu->isar.id_isar2 =3D 0x21112231; - cpu->isar.id_isar3 =3D 0x01111110; - cpu->isar.id_isar4 =3D 0x01310102; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; -} - -static void cortex_m7_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_M); - set_feature(&cpu->env, ARM_FEATURE_M_MAIN); - set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); - cpu->midr =3D 0x411fc272; /* r1p2 */ - cpu->pmsav7_dregion =3D 8; - cpu->isar.mvfr0 =3D 0x10110221; - cpu->isar.mvfr1 =3D 0x12000011; - cpu->isar.mvfr2 =3D 0x00000040; - cpu->id_pfr0 =3D 0x00000030; - cpu->id_pfr1 =3D 0x00000200; - cpu->isar.id_dfr0 =3D 0x00100000; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x00100030; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x01000000; - cpu->isar.id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01101110; - cpu->isar.id_isar1 =3D 0x02112000; - cpu->isar.id_isar2 =3D 0x20232231; - cpu->isar.id_isar3 =3D 0x01111131; - cpu->isar.id_isar4 =3D 0x01310132; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; -} - -static void cortex_m33_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_M); - set_feature(&cpu->env, ARM_FEATURE_M_MAIN); - set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); - set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); - cpu->midr =3D 0x410fd213; /* r0p3 */ - cpu->pmsav7_dregion =3D 16; - cpu->sau_sregion =3D 8; - cpu->isar.mvfr0 =3D 0x10110021; - cpu->isar.mvfr1 =3D 0x11000011; - cpu->isar.mvfr2 =3D 0x00000040; - cpu->id_pfr0 =3D 0x00000030; - cpu->id_pfr1 =3D 0x00000210; - cpu->isar.id_dfr0 =3D 0x00200000; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x00101F40; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x01000000; - cpu->isar.id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01101110; - cpu->isar.id_isar1 =3D 0x02212000; - cpu->isar.id_isar2 =3D 0x20232232; - cpu->isar.id_isar3 =3D 0x01111131; - cpu->isar.id_isar4 =3D 0x01310132; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; - cpu->clidr =3D 0x00000000; - cpu->ctr =3D 0x8000c000; -} - -static void arm_v7m_class_init(ObjectClass *oc, void *data) -{ - ARMCPUClass *acc =3D ARM_CPU_CLASS(oc); - CPUClass *cc =3D CPU_CLASS(oc); - - acc->info =3D data; -#ifndef CONFIG_USER_ONLY - cc->do_interrupt =3D arm_v7m_cpu_do_interrupt; -#endif - - cc->cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt; -} - -static const ARMCPRegInfo cortexr5_cp_reginfo[] =3D { - /* Dummy the TCM region regs for the moment */ - { .name =3D "ATCM", .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 1, .= opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_CONST }, - { .name =3D "BTCM", .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 1, .= opc2 =3D 1, - .access =3D PL1_RW, .type =3D ARM_CP_CONST }, - { .name =3D "DCACHE_INVAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 15, .crm= =3D 5, - .opc2 =3D 0, .access =3D PL1_W, .type =3D ARM_CP_NOP }, - REGINFO_SENTINEL -}; - -static void cortex_r5_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_V7MP); - set_feature(&cpu->env, ARM_FEATURE_PMSA); - set_feature(&cpu->env, ARM_FEATURE_PMU); - cpu->midr =3D 0x411fc153; /* r1p3 */ - cpu->id_pfr0 =3D 0x0131; - cpu->id_pfr1 =3D 0x001; - cpu->isar.id_dfr0 =3D 0x010400; - cpu->id_afr0 =3D 0x0; - cpu->isar.id_mmfr0 =3D 0x0210030; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x01200000; - cpu->isar.id_mmfr3 =3D 0x0211; - cpu->isar.id_isar0 =3D 0x02101111; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232141; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x0010142; - cpu->isar.id_isar5 =3D 0x0; - cpu->isar.id_isar6 =3D 0x0; - cpu->mp_is_up =3D true; - cpu->pmsav7_dregion =3D 16; - define_arm_cp_regs(cpu, cortexr5_cp_reginfo); -} - -static void cortex_r5f_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cortex_r5_initfn(obj); - cpu->isar.mvfr0 =3D 0x10110221; - cpu->isar.mvfr1 =3D 0x00000011; -} - static const ARMCPRegInfo cortexa8_cp_reginfo[] =3D { { .name =3D "L2LOCKDOWN", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 = =3D 1, .opc2 =3D 0, .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, @@ -2446,174 +2020,6 @@ static void cortex_a15_initfn(Object *obj) define_arm_cp_regs(cpu, cortexa15_cp_reginfo); } =20 -static void ti925t_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - set_feature(&cpu->env, ARM_FEATURE_V4T); - set_feature(&cpu->env, ARM_FEATURE_OMAPCP); - cpu->midr =3D ARM_CPUID_TI925T; - cpu->ctr =3D 0x5109149; - cpu->reset_sctlr =3D 0x00000070; -} - -static void sa1100_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "intel,sa1100"; - set_feature(&cpu->env, ARM_FEATURE_STRONGARM); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - cpu->midr =3D 0x4401A11B; - cpu->reset_sctlr =3D 0x00000070; -} - -static void sa1110_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - set_feature(&cpu->env, ARM_FEATURE_STRONGARM); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - cpu->midr =3D 0x6901B119; - cpu->reset_sctlr =3D 0x00000070; -} - -static void pxa250_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - cpu->midr =3D 0x69052100; - cpu->ctr =3D 0xd172172; - cpu->reset_sctlr =3D 0x00000078; -} - -static void pxa255_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - cpu->midr =3D 0x69052d00; - cpu->ctr =3D 0xd172172; - cpu->reset_sctlr =3D 0x00000078; -} - -static void pxa260_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - cpu->midr =3D 0x69052903; - cpu->ctr =3D 0xd172172; - cpu->reset_sctlr =3D 0x00000078; -} - -static void pxa261_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - cpu->midr =3D 0x69052d05; - cpu->ctr =3D 0xd172172; - cpu->reset_sctlr =3D 0x00000078; -} - -static void pxa262_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - cpu->midr =3D 0x69052d06; - cpu->ctr =3D 0xd172172; - cpu->reset_sctlr =3D 0x00000078; -} - -static void pxa270a0_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - set_feature(&cpu->env, ARM_FEATURE_IWMMXT); - cpu->midr =3D 0x69054110; - cpu->ctr =3D 0xd172172; - cpu->reset_sctlr =3D 0x00000078; -} - -static void pxa270a1_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - set_feature(&cpu->env, ARM_FEATURE_IWMMXT); - cpu->midr =3D 0x69054111; - cpu->ctr =3D 0xd172172; - cpu->reset_sctlr =3D 0x00000078; -} - -static void pxa270b0_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - set_feature(&cpu->env, ARM_FEATURE_IWMMXT); - cpu->midr =3D 0x69054112; - cpu->ctr =3D 0xd172172; - cpu->reset_sctlr =3D 0x00000078; -} - -static void pxa270b1_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - set_feature(&cpu->env, ARM_FEATURE_IWMMXT); - cpu->midr =3D 0x69054113; - cpu->ctr =3D 0xd172172; - cpu->reset_sctlr =3D 0x00000078; -} - -static void pxa270c0_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - set_feature(&cpu->env, ARM_FEATURE_IWMMXT); - cpu->midr =3D 0x69054114; - cpu->ctr =3D 0xd172172; - cpu->reset_sctlr =3D 0x00000078; -} - -static void pxa270c5_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - set_feature(&cpu->env, ARM_FEATURE_IWMMXT); - cpu->midr =3D 0x69054117; - cpu->ctr =3D 0xd172172; - cpu->reset_sctlr =3D 0x00000078; -} - #ifndef TARGET_AARCH64 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this ho= st); * otherwise, a CPU with as many features enabled as our emulation support= s. @@ -2687,50 +2093,10 @@ static void arm_max_initfn(Object *obj) =20 static const ARMCPUInfo arm_cpus[] =3D { #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) - { .name =3D "arm926", .initfn =3D arm926_initfn }, - { .name =3D "arm946", .initfn =3D arm946_initfn }, - { .name =3D "arm1026", .initfn =3D arm1026_initfn }, - /* - * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an - * older core than plain "arm1136". In particular this does not - * have the v6K features. - */ - { .name =3D "arm1136-r2", .initfn =3D arm1136_r2_initfn }, - { .name =3D "arm1136", .initfn =3D arm1136_initfn }, - { .name =3D "arm1176", .initfn =3D arm1176_initfn }, - { .name =3D "arm11mpcore", .initfn =3D arm11mpcore_initfn }, - { .name =3D "cortex-m0", .initfn =3D cortex_m0_initfn, - .class_init =3D arm_v7m_class_init }, - { .name =3D "cortex-m3", .initfn =3D cortex_m3_initfn, - .class_init =3D arm_v7m_class_init }, - { .name =3D "cortex-m4", .initfn =3D cortex_m4_initfn, - .class_init =3D arm_v7m_class_init }, - { .name =3D "cortex-m7", .initfn =3D cortex_m7_initfn, - .class_init =3D arm_v7m_class_init }, - { .name =3D "cortex-m33", .initfn =3D cortex_m33_initfn, - .class_init =3D arm_v7m_class_init }, - { .name =3D "cortex-r5", .initfn =3D cortex_r5_initfn }, - { .name =3D "cortex-r5f", .initfn =3D cortex_r5f_initfn }, { .name =3D "cortex-a7", .initfn =3D cortex_a7_initfn }, { .name =3D "cortex-a8", .initfn =3D cortex_a8_initfn }, { .name =3D "cortex-a9", .initfn =3D cortex_a9_initfn }, { .name =3D "cortex-a15", .initfn =3D cortex_a15_initfn }, - { .name =3D "ti925t", .initfn =3D ti925t_initfn }, - { .name =3D "sa1100", .initfn =3D sa1100_initfn }, - { .name =3D "sa1110", .initfn =3D sa1110_initfn }, - { .name =3D "pxa250", .initfn =3D pxa250_initfn }, - { .name =3D "pxa255", .initfn =3D pxa255_initfn }, - { .name =3D "pxa260", .initfn =3D pxa260_initfn }, - { .name =3D "pxa261", .initfn =3D pxa261_initfn }, - { .name =3D "pxa262", .initfn =3D pxa262_initfn }, - /* "pxa270" is an alias for "pxa270-a0" */ - { .name =3D "pxa270", .initfn =3D pxa270a0_initfn }, - { .name =3D "pxa270-a0", .initfn =3D pxa270a0_initfn }, - { .name =3D "pxa270-a1", .initfn =3D pxa270a1_initfn }, - { .name =3D "pxa270-b0", .initfn =3D pxa270b0_initfn }, - { .name =3D "pxa270-b1", .initfn =3D pxa270b1_initfn }, - { .name =3D "pxa270-c0", .initfn =3D pxa270c0_initfn }, - { .name =3D "pxa270-c5", .initfn =3D pxa270c5_initfn }, #ifndef TARGET_AARCH64 { .name =3D "max", .initfn =3D arm_max_initfn }, #endif diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c new file mode 100644 index 0000000000..899d3ac7bc --- /dev/null +++ b/target/arm/cpu_tcg.c @@ -0,0 +1,663 @@ +/* + * ARM generic helpers. + * QEMU ARM CPU + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" + +/* CPU models. These are not needed for the AArch64 linux-user build. */ +#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) + +static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + CPUClass *cc =3D CPU_GET_CLASS(cs); + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + bool ret =3D false; + + /* + * ARMv7-M interrupt masking works differently than -A or -R. + * There is no FIQ/IRQ distinction. Instead of I and F bits + * masking FIQ and IRQ interrupts, an exception is taken only + * if it is higher priority than the current execution priority + * (which depends on state like BASEPRI, FAULTMASK and the + * currently active exception). + */ + if (interrupt_request & CPU_INTERRUPT_HARD + && (armv7m_nvic_can_take_pending_exception(env->nvic))) { + cs->exception_index =3D EXCP_IRQ; + cc->do_interrupt(cs); + ret =3D true; + } + return ret; +} + +static void arm926_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,arm926"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); + cpu->midr =3D 0x41069265; + cpu->reset_fpsid =3D 0x41011090; + cpu->ctr =3D 0x1dd20d2; + cpu->reset_sctlr =3D 0x00090078; + + /* + * ARMv5 does not have the ID_ISAR registers, but we can still + * set the field to indicate Jazelle support within QEMU. + */ + cpu->isar.id_isar1 =3D FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELL= E, 1); + /* + * Similarly, we need to set MVFR0 fields to enable vfp and short vect= or + * support even though ARMv5 doesn't have this register. + */ + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); +} + +static void arm946_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,arm946"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_PMSA); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + cpu->midr =3D 0x41059461; + cpu->ctr =3D 0x0f004006; + cpu->reset_sctlr =3D 0x00000078; +} + +static void arm1026_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,arm1026"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_AUXCR); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); + cpu->midr =3D 0x4106a262; + cpu->reset_fpsid =3D 0x410110a0; + cpu->ctr =3D 0x1dd20d2; + cpu->reset_sctlr =3D 0x00090078; + cpu->reset_auxcr =3D 1; + + /* + * ARMv5 does not have the ID_ISAR registers, but we can still + * set the field to indicate Jazelle support within QEMU. + */ + cpu->isar.id_isar1 =3D FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELL= E, 1); + /* + * Similarly, we need to set MVFR0 fields to enable vfp and short vect= or + * support even though ARMv5 doesn't have this register. + */ + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); + + { + /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0= ,2 */ + ARMCPRegInfo ifar =3D { + .name =3D "IFAR", .cp =3D 15, .crn =3D 6, .crm =3D 0, .opc1 = =3D 0, .opc2 =3D 1, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.ifar_ns), + .resetvalue =3D 0 + }; + define_one_arm_cp_reg(cpu, &ifar); + } +} + +static void arm1136_r2_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + /* + * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an + * older core than plain "arm1136". In particular this does not + * have the v6K features. + * These ID register values are correct for 1136 but may be wrong + * for 1136_r2 (in particular r0p2 does not actually implement most + * of the ID registers). + */ + + cpu->dtb_compatible =3D "arm,arm1136"; + set_feature(&cpu->env, ARM_FEATURE_V6); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); + set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); + cpu->midr =3D 0x4107b362; + cpu->reset_fpsid =3D 0x410120b4; + cpu->isar.mvfr0 =3D 0x11111111; + cpu->isar.mvfr1 =3D 0x00000000; + cpu->ctr =3D 0x1dd20d2; + cpu->reset_sctlr =3D 0x00050078; + cpu->id_pfr0 =3D 0x111; + cpu->id_pfr1 =3D 0x1; + cpu->isar.id_dfr0 =3D 0x2; + cpu->id_afr0 =3D 0x3; + cpu->isar.id_mmfr0 =3D 0x01130003; + cpu->isar.id_mmfr1 =3D 0x10030302; + cpu->isar.id_mmfr2 =3D 0x01222110; + cpu->isar.id_isar0 =3D 0x00140011; + cpu->isar.id_isar1 =3D 0x12002111; + cpu->isar.id_isar2 =3D 0x11231111; + cpu->isar.id_isar3 =3D 0x01102131; + cpu->isar.id_isar4 =3D 0x141; + cpu->reset_auxcr =3D 7; +} + +static void arm1136_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,arm1136"; + set_feature(&cpu->env, ARM_FEATURE_V6K); + set_feature(&cpu->env, ARM_FEATURE_V6); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); + set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); + cpu->midr =3D 0x4117b363; + cpu->reset_fpsid =3D 0x410120b4; + cpu->isar.mvfr0 =3D 0x11111111; + cpu->isar.mvfr1 =3D 0x00000000; + cpu->ctr =3D 0x1dd20d2; + cpu->reset_sctlr =3D 0x00050078; + cpu->id_pfr0 =3D 0x111; + cpu->id_pfr1 =3D 0x1; + cpu->isar.id_dfr0 =3D 0x2; + cpu->id_afr0 =3D 0x3; + cpu->isar.id_mmfr0 =3D 0x01130003; + cpu->isar.id_mmfr1 =3D 0x10030302; + cpu->isar.id_mmfr2 =3D 0x01222110; + cpu->isar.id_isar0 =3D 0x00140011; + cpu->isar.id_isar1 =3D 0x12002111; + cpu->isar.id_isar2 =3D 0x11231111; + cpu->isar.id_isar3 =3D 0x01102131; + cpu->isar.id_isar4 =3D 0x141; + cpu->reset_auxcr =3D 7; +} + +static void arm1176_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,arm1176"; + set_feature(&cpu->env, ARM_FEATURE_V6K); + set_feature(&cpu->env, ARM_FEATURE_VAPA); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); + set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); + set_feature(&cpu->env, ARM_FEATURE_EL3); + cpu->midr =3D 0x410fb767; + cpu->reset_fpsid =3D 0x410120b5; + cpu->isar.mvfr0 =3D 0x11111111; + cpu->isar.mvfr1 =3D 0x00000000; + cpu->ctr =3D 0x1dd20d2; + cpu->reset_sctlr =3D 0x00050078; + cpu->id_pfr0 =3D 0x111; + cpu->id_pfr1 =3D 0x11; + cpu->isar.id_dfr0 =3D 0x33; + cpu->id_afr0 =3D 0; + cpu->isar.id_mmfr0 =3D 0x01130003; + cpu->isar.id_mmfr1 =3D 0x10030302; + cpu->isar.id_mmfr2 =3D 0x01222100; + cpu->isar.id_isar0 =3D 0x0140011; + cpu->isar.id_isar1 =3D 0x12002111; + cpu->isar.id_isar2 =3D 0x11231121; + cpu->isar.id_isar3 =3D 0x01102131; + cpu->isar.id_isar4 =3D 0x01141; + cpu->reset_auxcr =3D 7; +} + +static void arm11mpcore_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,arm11mpcore"; + set_feature(&cpu->env, ARM_FEATURE_V6K); + set_feature(&cpu->env, ARM_FEATURE_VAPA); + set_feature(&cpu->env, ARM_FEATURE_MPIDR); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + cpu->midr =3D 0x410fb022; + cpu->reset_fpsid =3D 0x410120b4; + cpu->isar.mvfr0 =3D 0x11111111; + cpu->isar.mvfr1 =3D 0x00000000; + cpu->ctr =3D 0x1d192992; /* 32K icache 32K dcache */ + cpu->id_pfr0 =3D 0x111; + cpu->id_pfr1 =3D 0x1; + cpu->isar.id_dfr0 =3D 0; + cpu->id_afr0 =3D 0x2; + cpu->isar.id_mmfr0 =3D 0x01100103; + cpu->isar.id_mmfr1 =3D 0x10020302; + cpu->isar.id_mmfr2 =3D 0x01222000; + cpu->isar.id_isar0 =3D 0x00100011; + cpu->isar.id_isar1 =3D 0x12002111; + cpu->isar.id_isar2 =3D 0x11221011; + cpu->isar.id_isar3 =3D 0x01102131; + cpu->isar.id_isar4 =3D 0x141; + cpu->reset_auxcr =3D 1; +} + +static void cortex_m0_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V6); + set_feature(&cpu->env, ARM_FEATURE_M); + + cpu->midr =3D 0x410cc200; +} + +static void cortex_m3_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); + cpu->midr =3D 0x410fc231; + cpu->pmsav7_dregion =3D 8; + cpu->id_pfr0 =3D 0x00000030; + cpu->id_pfr1 =3D 0x00000200; + cpu->isar.id_dfr0 =3D 0x00100000; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x00000030; + cpu->isar.id_mmfr1 =3D 0x00000000; + cpu->isar.id_mmfr2 =3D 0x00000000; + cpu->isar.id_mmfr3 =3D 0x00000000; + cpu->isar.id_isar0 =3D 0x01141110; + cpu->isar.id_isar1 =3D 0x02111000; + cpu->isar.id_isar2 =3D 0x21112231; + cpu->isar.id_isar3 =3D 0x01111110; + cpu->isar.id_isar4 =3D 0x01310102; + cpu->isar.id_isar5 =3D 0x00000000; + cpu->isar.id_isar6 =3D 0x00000000; +} + +static void cortex_m4_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); + cpu->midr =3D 0x410fc240; /* r0p0 */ + cpu->pmsav7_dregion =3D 8; + cpu->isar.mvfr0 =3D 0x10110021; + cpu->isar.mvfr1 =3D 0x11000011; + cpu->isar.mvfr2 =3D 0x00000000; + cpu->id_pfr0 =3D 0x00000030; + cpu->id_pfr1 =3D 0x00000200; + cpu->isar.id_dfr0 =3D 0x00100000; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x00000030; + cpu->isar.id_mmfr1 =3D 0x00000000; + cpu->isar.id_mmfr2 =3D 0x00000000; + cpu->isar.id_mmfr3 =3D 0x00000000; + cpu->isar.id_isar0 =3D 0x01141110; + cpu->isar.id_isar1 =3D 0x02111000; + cpu->isar.id_isar2 =3D 0x21112231; + cpu->isar.id_isar3 =3D 0x01111110; + cpu->isar.id_isar4 =3D 0x01310102; + cpu->isar.id_isar5 =3D 0x00000000; + cpu->isar.id_isar6 =3D 0x00000000; +} + +static void cortex_m7_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); + cpu->midr =3D 0x411fc272; /* r1p2 */ + cpu->pmsav7_dregion =3D 8; + cpu->isar.mvfr0 =3D 0x10110221; + cpu->isar.mvfr1 =3D 0x12000011; + cpu->isar.mvfr2 =3D 0x00000040; + cpu->id_pfr0 =3D 0x00000030; + cpu->id_pfr1 =3D 0x00000200; + cpu->isar.id_dfr0 =3D 0x00100000; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x00100030; + cpu->isar.id_mmfr1 =3D 0x00000000; + cpu->isar.id_mmfr2 =3D 0x01000000; + cpu->isar.id_mmfr3 =3D 0x00000000; + cpu->isar.id_isar0 =3D 0x01101110; + cpu->isar.id_isar1 =3D 0x02112000; + cpu->isar.id_isar2 =3D 0x20232231; + cpu->isar.id_isar3 =3D 0x01111131; + cpu->isar.id_isar4 =3D 0x01310132; + cpu->isar.id_isar5 =3D 0x00000000; + cpu->isar.id_isar6 =3D 0x00000000; +} + +static void cortex_m33_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); + set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); + cpu->midr =3D 0x410fd213; /* r0p3 */ + cpu->pmsav7_dregion =3D 16; + cpu->sau_sregion =3D 8; + cpu->isar.mvfr0 =3D 0x10110021; + cpu->isar.mvfr1 =3D 0x11000011; + cpu->isar.mvfr2 =3D 0x00000040; + cpu->id_pfr0 =3D 0x00000030; + cpu->id_pfr1 =3D 0x00000210; + cpu->isar.id_dfr0 =3D 0x00200000; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x00101F40; + cpu->isar.id_mmfr1 =3D 0x00000000; + cpu->isar.id_mmfr2 =3D 0x01000000; + cpu->isar.id_mmfr3 =3D 0x00000000; + cpu->isar.id_isar0 =3D 0x01101110; + cpu->isar.id_isar1 =3D 0x02212000; + cpu->isar.id_isar2 =3D 0x20232232; + cpu->isar.id_isar3 =3D 0x01111131; + cpu->isar.id_isar4 =3D 0x01310132; + cpu->isar.id_isar5 =3D 0x00000000; + cpu->isar.id_isar6 =3D 0x00000000; + cpu->clidr =3D 0x00000000; + cpu->ctr =3D 0x8000c000; +} + +static const ARMCPRegInfo cortexr5_cp_reginfo[] =3D { + /* Dummy the TCM region regs for the moment */ + { .name =3D "ATCM", .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 1, .= opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST }, + { .name =3D "BTCM", .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 1, .= opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_CONST }, + { .name =3D "DCACHE_INVAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 15, .crm= =3D 5, + .opc2 =3D 0, .access =3D PL1_W, .type =3D ARM_CP_NOP }, + REGINFO_SENTINEL +}; + +static void cortex_r5_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_V7MP); + set_feature(&cpu->env, ARM_FEATURE_PMSA); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->midr =3D 0x411fc153; /* r1p3 */ + cpu->id_pfr0 =3D 0x0131; + cpu->id_pfr1 =3D 0x001; + cpu->isar.id_dfr0 =3D 0x010400; + cpu->id_afr0 =3D 0x0; + cpu->isar.id_mmfr0 =3D 0x0210030; + cpu->isar.id_mmfr1 =3D 0x00000000; + cpu->isar.id_mmfr2 =3D 0x01200000; + cpu->isar.id_mmfr3 =3D 0x0211; + cpu->isar.id_isar0 =3D 0x02101111; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232141; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x0010142; + cpu->isar.id_isar5 =3D 0x0; + cpu->isar.id_isar6 =3D 0x0; + cpu->mp_is_up =3D true; + cpu->pmsav7_dregion =3D 16; + define_arm_cp_regs(cpu, cortexr5_cp_reginfo); +} + +static void cortex_r5f_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cortex_r5_initfn(obj); + cpu->isar.mvfr0 =3D 0x10110221; + cpu->isar.mvfr1 =3D 0x00000011; +} + +static void ti925t_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V4T); + set_feature(&cpu->env, ARM_FEATURE_OMAPCP); + cpu->midr =3D ARM_CPUID_TI925T; + cpu->ctr =3D 0x5109149; + cpu->reset_sctlr =3D 0x00000070; +} + +static void sa1100_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "intel,sa1100"; + set_feature(&cpu->env, ARM_FEATURE_STRONGARM); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + cpu->midr =3D 0x4401A11B; + cpu->reset_sctlr =3D 0x00000070; +} + +static void sa1110_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_STRONGARM); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + cpu->midr =3D 0x6901B119; + cpu->reset_sctlr =3D 0x00000070; +} + +static void pxa250_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "marvell,xscale"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + cpu->midr =3D 0x69052100; + cpu->ctr =3D 0xd172172; + cpu->reset_sctlr =3D 0x00000078; +} + +static void pxa255_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "marvell,xscale"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + cpu->midr =3D 0x69052d00; + cpu->ctr =3D 0xd172172; + cpu->reset_sctlr =3D 0x00000078; +} + +static void pxa260_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "marvell,xscale"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + cpu->midr =3D 0x69052903; + cpu->ctr =3D 0xd172172; + cpu->reset_sctlr =3D 0x00000078; +} + +static void pxa261_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "marvell,xscale"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + cpu->midr =3D 0x69052d05; + cpu->ctr =3D 0xd172172; + cpu->reset_sctlr =3D 0x00000078; +} + +static void pxa262_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "marvell,xscale"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + cpu->midr =3D 0x69052d06; + cpu->ctr =3D 0xd172172; + cpu->reset_sctlr =3D 0x00000078; +} + +static void pxa270a0_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "marvell,xscale"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + set_feature(&cpu->env, ARM_FEATURE_IWMMXT); + cpu->midr =3D 0x69054110; + cpu->ctr =3D 0xd172172; + cpu->reset_sctlr =3D 0x00000078; +} + +static void pxa270a1_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "marvell,xscale"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + set_feature(&cpu->env, ARM_FEATURE_IWMMXT); + cpu->midr =3D 0x69054111; + cpu->ctr =3D 0xd172172; + cpu->reset_sctlr =3D 0x00000078; +} + +static void pxa270b0_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "marvell,xscale"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + set_feature(&cpu->env, ARM_FEATURE_IWMMXT); + cpu->midr =3D 0x69054112; + cpu->ctr =3D 0xd172172; + cpu->reset_sctlr =3D 0x00000078; +} + +static void pxa270b1_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "marvell,xscale"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + set_feature(&cpu->env, ARM_FEATURE_IWMMXT); + cpu->midr =3D 0x69054113; + cpu->ctr =3D 0xd172172; + cpu->reset_sctlr =3D 0x00000078; +} + +static void pxa270c0_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "marvell,xscale"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + set_feature(&cpu->env, ARM_FEATURE_IWMMXT); + cpu->midr =3D 0x69054114; + cpu->ctr =3D 0xd172172; + cpu->reset_sctlr =3D 0x00000078; +} + +static void pxa270c5_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "marvell,xscale"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + set_feature(&cpu->env, ARM_FEATURE_IWMMXT); + cpu->midr =3D 0x69054117; + cpu->ctr =3D 0xd172172; + cpu->reset_sctlr =3D 0x00000078; +} + +static void arm_v7m_class_init(ObjectClass *oc, void *data) +{ + ARMCPUClass *acc =3D ARM_CPU_CLASS(oc); + CPUClass *cc =3D CPU_CLASS(oc); + + acc->info =3D data; +#ifndef CONFIG_USER_ONLY + cc->do_interrupt =3D arm_v7m_cpu_do_interrupt; +#endif + + cc->cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt; +} + +static const ARMCPUInfo arm_tcg_cpus[] =3D { + { .name =3D "arm926", .initfn =3D arm926_initfn }, + { .name =3D "arm946", .initfn =3D arm946_initfn }, + { .name =3D "arm1026", .initfn =3D arm1026_initfn }, + /* + * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an + * older core than plain "arm1136". In particular this does not + * have the v6K features. + */ + { .name =3D "arm1136-r2", .initfn =3D arm1136_r2_initfn }, + { .name =3D "arm1136", .initfn =3D arm1136_initfn }, + { .name =3D "arm1176", .initfn =3D arm1176_initfn }, + { .name =3D "arm11mpcore", .initfn =3D arm11mpcore_initfn }, + { .name =3D "cortex-m0", .initfn =3D cortex_m0_initfn, + .class_init =3D arm_v7m_class_init }, + { .name =3D "cortex-m3", .initfn =3D cortex_m3_initfn, + .class_init =3D arm_v7m_class_init }, + { .name =3D "cortex-m4", .initfn =3D cortex_m4_initfn, + .class_init =3D arm_v7m_class_init }, + { .name =3D "cortex-m7", .initfn =3D cortex_m7_initfn, + .class_init =3D arm_v7m_class_init }, + { .name =3D "cortex-m33", .initfn =3D cortex_m33_initfn, + .class_init =3D arm_v7m_class_init }, + { .name =3D "cortex-r5", .initfn =3D cortex_r5_initfn }, + { .name =3D "cortex-r5f", .initfn =3D cortex_r5f_initfn }, + { .name =3D "ti925t", .initfn =3D ti925t_initfn }, + { .name =3D "sa1100", .initfn =3D sa1100_initfn }, + { .name =3D "sa1110", .initfn =3D sa1110_initfn }, + { .name =3D "pxa250", .initfn =3D pxa250_initfn }, + { .name =3D "pxa255", .initfn =3D pxa255_initfn }, + { .name =3D "pxa260", .initfn =3D pxa260_initfn }, + { .name =3D "pxa261", .initfn =3D pxa261_initfn }, + { .name =3D "pxa262", .initfn =3D pxa262_initfn }, + /* "pxa270" is an alias for "pxa270-a0" */ + { .name =3D "pxa270", .initfn =3D pxa270a0_initfn }, + { .name =3D "pxa270-a0", .initfn =3D pxa270a0_initfn }, + { .name =3D "pxa270-a1", .initfn =3D pxa270a1_initfn }, + { .name =3D "pxa270-b0", .initfn =3D pxa270b0_initfn }, + { .name =3D "pxa270-b1", .initfn =3D pxa270b1_initfn }, + { .name =3D "pxa270-c0", .initfn =3D pxa270c0_initfn }, + { .name =3D "pxa270-c5", .initfn =3D pxa270c5_initfn }, +}; + +static void arm_tcg_cpu_register_types(void) +{ + size_t i; + + for (i =3D 0; i < ARRAY_SIZE(arm_tcg_cpus); ++i) { + arm_cpu_register(&arm_tcg_cpus[i]); + } +} + +type_init(arm_tcg_cpu_register_types) + +#endif /* !CONFIG_USER_ONLY || !TARGET_AARCH64 */ diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index cf26c16f5f..212b588afd 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -61,6 +61,7 @@ obj-y +=3D translate.o op_helper.o obj-y +=3D crypto_helper.o obj-y +=3D iwmmxt_helper.o vec_helper.o neon_helper.o obj-y +=3D m_helper.o +obj-y +=3D cpu_tcg.o =20 obj-$(CONFIG_SOFTMMU) +=3D psci.o =20 --=20 2.21.1