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[83.42.57.116]) by smtp.gmail.com with ESMTPSA id d5sm2481631wrp.44.2020.04.21.00.13.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 21 Apr 2020 00:13:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:mime-version :content-transfer-encoding; bh=nAASM20KlmtmCGTRTSznUWtd6msX/BJofWlyBMvnWBQ=; b=r6cVo6LUzKkVSbL5m35GIhIUGATv96tr7UBvRyCvDFEmfUfcuHPi38G04R8DLId58C igTgEDEnJFXn8XfQ4tEWubvgAkXD95IltuMdZCT+Tt2FB8wjNdqHDcmILybpng2lUMT/ kNLihJX4jDG7DCBjWanswI8qqN3DZTR6kcm/iPbC7Bu+E1RsXSaYmbZEUzurSQ6XE+vp Y9KJ3KysCfQTD02D0p15pXc8cDfbrNhDta52A5C03ekpGYT66pzl296i/nt4bilF3XmJ Uxn85VYPiC+/lLN06PYJB91g266AWwn62B1zk4EJtdgHseq2N9kdZNxmAwMSoIkUxSJZ 0jaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :mime-version:content-transfer-encoding; bh=nAASM20KlmtmCGTRTSznUWtd6msX/BJofWlyBMvnWBQ=; b=OaSl7PeUZzUGquufj6h+gT9SmiWbIl/8o6tdGOrV1dUW/7RpTFNCg83Qi7EBvENTHz XE43zjskS3Wy6ksCMCjtbns6faYK8v9338aig3xwxAE/neWYZmeBkED6uxKCwTjYPhx1 LaJjuobRsCAnGQvDYtz8gF/Km2sxCXWgg8KebMltYr3zU/4ErWn53mTgD3VKB4xbQe67 io0bfHc9BOA1TSjghb3MLWYFluGh9Trc43Msdqe6WolP/FYVQu0Y/EStdIdVRQRZ5KRu 0KtsgO0YabcERVT5VuMO83ZWLmzU6DNjS2sPGTnnZgY3uaiyvay4WVcFiT+A0PXQiQLK /qhw== X-Gm-Message-State: AGi0PuYjrJkyYGGgnQjlsZ5js22y1MM/oOcyKBUd5ETmd7Phe/fC5ey2 Gym5aSIA1CJq8dTsswo69FWllTlOe8E= X-Google-Smtp-Source: APiQypImksgfsR97NoQEWa1HVMIuHhE1/fFSDObUvUxmi80/NrdJyV01ssRCMFJmDSro6u48CeIr0w== X-Received: by 2002:a1c:a58b:: with SMTP id o133mr3289452wme.5.1587453216176; Tue, 21 Apr 2020 00:13:36 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org, Paul Zimmerman Subject: [PATCH] hw/usb/hcd-dwc2: Simplified I/O memory regions Date: Tue, 21 Apr 2020 09:13:33 +0200 Message-Id: <20200421071333.24706-1-f4bug@amsat.org> X-Mailer: git-send-email 2.21.1 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::343; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-x343.google.com X-detected-operating-system: by eggs.gnu.org: Error: [-] PROGRAM ABORT : Malformed IPv6 address (bad octet value). Location : parse_addr6(), p0f-client.c:67 X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Gerd Hoffmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Use 1 container holding 2 regions: - I/O registers - FIFOs Remove all the static base addresses. Name address space. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- Sometime a patch is cleaner/quicker than explanations. Suggestion to be squashed on patch: 'dwc-hsotg (dwc2) USB host controller emulation' Further simplificatio would be to move some exploded read/write functions directly into dwc2_hsotg_read/write. Based-on: <20200421014551.10426-1-pauldzim@gmail.com> --- hw/usb/hcd-dwc2.h | 17 +---- hw/usb/hcd-dwc2.c | 181 ++++++++++++++++++++++------------------------ 2 files changed, 88 insertions(+), 110 deletions(-) diff --git a/hw/usb/hcd-dwc2.h b/hw/usb/hcd-dwc2.h index 403afd1747..7d7ea604a4 100644 --- a/hw/usb/hcd-dwc2.h +++ b/hw/usb/hcd-dwc2.h @@ -61,20 +61,9 @@ struct DWC2State { qemu_irq irq; MemoryRegion *dma_mr; AddressSpace dma_as; - MemoryRegion mem; - MemoryRegion mem_glbreg; - MemoryRegion mem_fszreg; - MemoryRegion mem_hreg0; - MemoryRegion mem_hreg1; - MemoryRegion mem_pcgreg; - MemoryRegion mem_hreg2; - - uint16_t glbregbase; - uint16_t fszregbase; - uint16_t hreg0base; - uint16_t hreg1base; - uint16_t pcgregbase; - uint16_t hfifobase; + MemoryRegion container; + MemoryRegion hsotg; + MemoryRegion fifos; =20 union { #define DWC2_GLBREG_SIZE 0x70 diff --git a/hw/usb/hcd-dwc2.c b/hw/usb/hcd-dwc2.c index 31de82bcd3..5c0e6a66b8 100644 --- a/hw/usb/hcd-dwc2.c +++ b/hw/usb/hcd-dwc2.c @@ -28,6 +28,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/units.h" #include "qapi/error.h" #include "hw/usb/dwc2-regs.h" #include "hw/usb/hcd-dwc2.h" @@ -655,7 +656,7 @@ static const char *glbregnm[] =3D { static uint64_t dwc2_glbreg_read(void *ptr, hwaddr addr, unsigned size) { DWC2State *s =3D ptr; - uint32_t reg =3D s->glbregbase + addr; + uint32_t reg =3D addr; uint32_t val; =20 assert(reg <=3D GINTSTS2); @@ -681,7 +682,7 @@ static void dwc2_glbreg_write(void *ptr, hwaddr addr, u= int64_t val, { DWC2State *s =3D ptr; uint64_t orig =3D val; - uint32_t reg =3D s->glbregbase + addr; + uint32_t reg =3D addr; uint32_t *mmio; uint32_t old; int iflg =3D 0; @@ -762,10 +763,9 @@ static void dwc2_glbreg_write(void *ptr, hwaddr addr, = uint64_t val, static uint64_t dwc2_fszreg_read(void *ptr, hwaddr addr, unsigned size) { DWC2State *s =3D ptr; - uint32_t reg =3D s->fszregbase + addr; uint32_t val; =20 - assert(reg <=3D HPTXFSIZ); + assert(addr <=3D HPTXFSIZ); val =3D s->fszreg[addr >> 2]; =20 trace_usb_dwc2_fszreg_read(addr, val); @@ -777,11 +777,10 @@ static void dwc2_fszreg_write(void *ptr, hwaddr addr,= uint64_t val, { DWC2State *s =3D ptr; uint64_t orig =3D val; - uint32_t reg =3D s->fszregbase + addr; uint32_t *mmio; uint32_t old; =20 - assert(reg <=3D HPTXFSIZ); + assert(addr <=3D HPTXFSIZ); mmio =3D &s->fszreg[addr >> 2]; old =3D *mmio; =20 @@ -800,13 +799,12 @@ static const char *hreg0nm[] =3D { static uint64_t dwc2_hreg0_read(void *ptr, hwaddr addr, unsigned size) { DWC2State *s =3D ptr; - uint32_t reg =3D s->hreg0base + addr; uint32_t val; =20 - assert(reg <=3D HPRT0); + assert(addr <=3D HPRT0); val =3D s->hreg0[addr >> 2]; =20 - switch (reg) { + switch (addr) { case HFNUM: val =3D (dwc2_get_frame_remaining(s) << HFNUM_FRREM_SHIFT) | (s->hfnum << HFNUM_FRNUM_SHIFT); @@ -825,17 +823,16 @@ static void dwc2_hreg0_write(void *ptr, hwaddr addr, = uint64_t val, DWC2State *s =3D ptr; USBDevice *dev =3D s->uport.dev; uint64_t orig =3D val; - uint32_t reg =3D s->hreg0base + addr; uint32_t *mmio; uint32_t tval, told, old; int prst =3D 0; int iflg =3D 0; =20 - assert(reg <=3D HPRT0); + assert(addr <=3D HPRT0); mmio =3D &s->hreg0[addr >> 2]; old =3D *mmio; =20 - switch (reg) { + switch (addr) { case HFIR: break; case HFNUM: @@ -915,14 +912,13 @@ static const char *hreg1nm[] =3D { static uint64_t dwc2_hreg1_read(void *ptr, hwaddr addr, unsigned size) { DWC2State *s =3D ptr; - uint32_t reg =3D s->hreg1base + addr; uint32_t val; =20 - assert(reg <=3D HCDMAB(DWC2_NB_CHAN - 1)); + assert(addr <=3D HCDMAB(DWC2_NB_CHAN - 1)); val =3D s->hreg1[addr >> 2]; =20 trace_usb_dwc2_hreg1_read(addr, hreg1nm[(addr >> 2) & 7], addr >> 5, v= al); - assert(s->hreg1base + (addr & 0x1c) <=3D HCDMAB(DWC2_NB_CHAN)); + assert((addr & 0x1c) <=3D HCDMAB(DWC2_NB_CHAN)); return val; } =20 @@ -931,18 +927,17 @@ static void dwc2_hreg1_write(void *ptr, hwaddr addr, = uint64_t val, { DWC2State *s =3D ptr; uint64_t orig =3D val; - uint32_t reg =3D s->hreg1base + addr; uint32_t *mmio; uint32_t old; int iflg =3D 0; int enflg =3D 0; int disflg =3D 0; =20 - assert(reg <=3D HCDMAB(DWC2_NB_CHAN - 1)); + assert(addr <=3D HCDMAB(DWC2_NB_CHAN - 1)); mmio =3D &s->hreg1[addr >> 2]; old =3D *mmio; =20 - switch (s->hreg1base + (addr & 0x1c)) { + switch (addr & 0x1c) { case HCCHAR(0): if ((val & HCCHAR_CHDIS) && !(old & HCCHAR_CHDIS)) { val &=3D ~(HCCHAR_CHENA | HCCHAR_CHDIS); @@ -1002,10 +997,9 @@ static const char *pcgregnm[] =3D { static uint64_t dwc2_pcgreg_read(void *ptr, hwaddr addr, unsigned size) { DWC2State *s =3D ptr; - uint32_t reg =3D s->pcgregbase + addr; uint32_t val; =20 - assert(reg <=3D PCGCCTL1); + assert(addr <=3D PCGCCTL1); val =3D s->pcgreg[addr >> 2]; =20 trace_usb_dwc2_pcgreg_read(addr, pcgregnm[addr >> 2], val); @@ -1017,11 +1011,10 @@ static void dwc2_pcgreg_write(void *ptr, hwaddr add= r, uint64_t val, { DWC2State *s =3D ptr; uint64_t orig =3D val; - uint32_t reg =3D s->pcgregbase + addr; uint32_t *mmio; uint32_t old; =20 - assert(reg <=3D PCGCCTL1); + assert(addr <=3D PCGCCTL1); mmio =3D &s->pcgreg[addr >> 2]; old =3D *mmio; =20 @@ -1030,6 +1023,65 @@ static void dwc2_pcgreg_write(void *ptr, hwaddr addr= , uint64_t val, *mmio =3D val; } =20 +static uint64_t dwc2_hsotg_read(void *ptr, hwaddr addr, unsigned size) +{ + uint64_t val; + + switch (addr) { + case HSOTG_REG(0x000) ... HSOTG_REG(0x0fc): + val =3D dwc2_glbreg_read(ptr, addr - HSOTG_REG(0x000), size); + break; + case HSOTG_REG(0x100) ... HSOTG_REG(0x3fc): + val =3D dwc2_fszreg_read(ptr, addr - HSOTG_REG(0x100), size); + break; + case HSOTG_REG(0x400) ... HSOTG_REG(0x4fc): + val =3D dwc2_hreg0_read(ptr, addr - HSOTG_REG(0x400), size); + break; + case HSOTG_REG(0x500) ... HSOTG_REG(0xdfc): + val =3D dwc2_hreg1_read(ptr, addr - HSOTG_REG(0x500), size); + break; + case HSOTG_REG(0xe00) ... HSOTG_REG(0xffc): + val =3D dwc2_pcgreg_read(ptr, addr - HSOTG_REG(0xe00), size); + break; + default: + g_assert_not_reached(); + } + + return val; +} + +static void dwc2_hsotg_write(void *ptr, hwaddr addr, uint64_t val, + unsigned size) +{ + switch (addr) { + case HSOTG_REG(0x000) ... HSOTG_REG(0x0fc): + dwc2_glbreg_write(ptr, addr - HSOTG_REG(0x000), val, size); + break; + case HSOTG_REG(0x100) ... HSOTG_REG(0x3fc): + dwc2_fszreg_write(ptr, addr - HSOTG_REG(0x100), val, size); + break; + case HSOTG_REG(0x400) ... HSOTG_REG(0x4fc): + dwc2_hreg0_write(ptr, addr - HSOTG_REG(0x400), val, size); + break; + case HSOTG_REG(0x500) ... HSOTG_REG(0xdfc): + dwc2_hreg1_write(ptr, addr - HSOTG_REG(0x500), val, size); + break; + case HSOTG_REG(0xe00) ... HSOTG_REG(0xffc): + dwc2_pcgreg_write(ptr, addr - HSOTG_REG(0xe00), val, size); + break; + default: + g_assert_not_reached(); + } +} + +static const MemoryRegionOps dwc2_mmio_hsotg_ops =3D { + .read =3D dwc2_hsotg_read, + .write =3D dwc2_hsotg_write, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + static uint64_t dwc2_hreg2_read(void *ptr, hwaddr addr, unsigned size) { /* TODO - implement FIFOs to support slave mode */ @@ -1047,46 +1099,6 @@ static void dwc2_hreg2_write(void *ptr, hwaddr addr,= uint64_t val, trace_usb_dwc2_hreg2_write(addr, addr >> 12, orig, 0, val); } =20 -static const MemoryRegionOps dwc2_mmio_glbreg_ops =3D { - .read =3D dwc2_glbreg_read, - .write =3D dwc2_glbreg_write, - .valid.min_access_size =3D 4, - .valid.max_access_size =3D 4, - .endianness =3D DEVICE_LITTLE_ENDIAN, -}; - -static const MemoryRegionOps dwc2_mmio_fszreg_ops =3D { - .read =3D dwc2_fszreg_read, - .write =3D dwc2_fszreg_write, - .valid.min_access_size =3D 4, - .valid.max_access_size =3D 4, - .endianness =3D DEVICE_LITTLE_ENDIAN, -}; - -static const MemoryRegionOps dwc2_mmio_hreg0_ops =3D { - .read =3D dwc2_hreg0_read, - .write =3D dwc2_hreg0_write, - .valid.min_access_size =3D 4, - .valid.max_access_size =3D 4, - .endianness =3D DEVICE_LITTLE_ENDIAN, -}; - -static const MemoryRegionOps dwc2_mmio_hreg1_ops =3D { - .read =3D dwc2_hreg1_read, - .write =3D dwc2_hreg1_write, - .valid.min_access_size =3D 4, - .valid.max_access_size =3D 4, - .endianness =3D DEVICE_LITTLE_ENDIAN, -}; - -static const MemoryRegionOps dwc2_mmio_pcgreg_ops =3D { - .read =3D dwc2_pcgreg_read, - .write =3D dwc2_pcgreg_write, - .valid.min_access_size =3D 4, - .valid.max_access_size =3D 4, - .endianness =3D DEVICE_LITTLE_ENDIAN, -}; - static const MemoryRegionOps dwc2_mmio_hreg2_ops =3D { .read =3D dwc2_hreg2_read, .write =3D dwc2_hreg2_write, @@ -1219,7 +1231,7 @@ static void dwc2_realize(DeviceState *dev, Error **er= rp) } =20 s->dma_mr =3D MEMORY_REGION(obj); - address_space_init(&s->dma_as, s->dma_mr, NULL); + address_space_init(&s->dma_as, s->dma_mr, "dwc2"); =20 usb_bus_new(&s->bus, sizeof(s->bus), &dwc2_bus_ops, dev); usb_register_port(&s->bus, &s->uport, s, 0, &dwc2_port_ops, @@ -1247,35 +1259,17 @@ static void dwc2_init(Object *obj) SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); DWC2State *s =3D DWC2_USB(obj); =20 - s->glbregbase =3D 0; - s->fszregbase =3D 0x0100; - s->hreg0base =3D 0x0400; - s->hreg1base =3D 0x0500; - s->pcgregbase =3D 0x0e00; - s->hfifobase =3D 0x1000; + memory_region_init(&s->container, obj, "dwc2", DWC2_MMIO_SIZE); + sysbus_init_mmio(sbd, &s->container); =20 - memory_region_init(&s->mem, obj, "dwc2", DWC2_MMIO_SIZE); - memory_region_init_io(&s->mem_glbreg, obj, &dwc2_mmio_glbreg_ops, s, - "global", DWC2_GLBREG_SIZE); - memory_region_init_io(&s->mem_fszreg, obj, &dwc2_mmio_fszreg_ops, s, - "hptxfsiz", DWC2_FSZREG_SIZE); - memory_region_init_io(&s->mem_hreg0, obj, &dwc2_mmio_hreg0_ops, s, - "host", DWC2_HREG0_SIZE); - memory_region_init_io(&s->mem_hreg1, obj, &dwc2_mmio_hreg1_ops, s, - "host channels", DWC2_HREG1_SIZE); - memory_region_init_io(&s->mem_pcgreg, obj, &dwc2_mmio_pcgreg_ops, s, - "power/clock", DWC2_PCGREG_SIZE); - memory_region_init_io(&s->mem_hreg2, obj, &dwc2_mmio_hreg2_ops, s, - "host fifos", DWC2_HFIFO_SIZE); + memory_region_init_io(&s->hsotg, obj, &dwc2_mmio_hsotg_ops, s, + "dwc2-io", 4 * KiB); + memory_region_add_subregion(&s->container, 0x0000, &s->hsotg); =20 - memory_region_add_subregion(&s->mem, s->glbregbase, &s->mem_glbreg); - memory_region_add_subregion(&s->mem, s->fszregbase, &s->mem_fszreg); - memory_region_add_subregion(&s->mem, s->hreg0base, &s->mem_hreg0); - memory_region_add_subregion(&s->mem, s->hreg1base, &s->mem_hreg1); - memory_region_add_subregion(&s->mem, s->pcgregbase, &s->mem_pcgreg); - memory_region_add_subregion(&s->mem, s->hfifobase, &s->mem_hreg2); + memory_region_init_io(&s->fifos, obj, &dwc2_mmio_hreg2_ops, s, + "dwc2-fifo", 64 * KiB); + memory_region_add_subregion(&s->container, 0x1000, &s->fifos); =20 - sysbus_init_mmio(sbd, &s->mem); } =20 static const VMStateDescription vmstate_dwc2_state_packet =3D { @@ -1303,13 +1297,6 @@ const VMStateDescription vmstate_dwc2_state =3D { .version_id =3D 1, .minimum_version_id =3D 1, .fields =3D (VMStateField[]) { - VMSTATE_UINT16(glbregbase, DWC2State), - VMSTATE_UINT16(fszregbase, DWC2State), - VMSTATE_UINT16(hreg0base, DWC2State), - VMSTATE_UINT16(hreg1base, DWC2State), - VMSTATE_UINT16(pcgregbase, DWC2State), - VMSTATE_UINT16(hfifobase, DWC2State), - VMSTATE_UINT32_ARRAY(glbreg, DWC2State, DWC2_GLBREG_SIZE / sizeof(uint32_t)), VMSTATE_UINT32_ARRAY(fszreg, DWC2State, @@ -1343,6 +1330,8 @@ const VMStateDescription vmstate_dwc2_state =3D { =20 static Property dwc2_usb_properties[] =3D { DEFINE_PROP_UINT32("usb_version", DWC2State, usb_version, 2), + /* FIXME isn't 'usb_version=3D2' const? */ + DEFINE_PROP_END_OF_LIST() }; =20 static void dwc2_class_init(ObjectClass *klass, void *data) --=20 2.21.1