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[174.21.149.226]) by smtp.gmail.com with ESMTPSA id m189sm13928532pfm.60.2020.04.18.08.56.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Apr 2020 08:56:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5wIqJJlAXSxMp0Ef0rZrs4CyiYgBlKFC7q0dmEQ2am4=; b=QXLS/Bgmn5Sly7dRplMVrYtHFnTlszesYi/raOKNsl3+LKH7NueONtFOO1nCowo4i8 wMD/oir0F2VxcmdPZMe6XB4mGTKmXVmgQw2TPYVdWFvmqKiMWKlCO3ExDCJWTUBZ3neM h/9CgcKXavaFk80tvky3FI7I/BUgk9BJiXXk0//+chVTvki3kHP+liMTyYNtM5c3dIH8 YuTJAgHrp3DuzIFRuFFH+x+DqRjel1w6M0W0d5t2Gzykiw7eNod34kSLw8qNtMm0ZRce Ge7tO/HJEf2MAvkpt4mi2XL9Gsmjt1WxRqtHe1ZVbUOJ2bdbDdpL/23s1czj0TyRKcsr fH1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5wIqJJlAXSxMp0Ef0rZrs4CyiYgBlKFC7q0dmEQ2am4=; b=sCR6UJNW3qmMCa5Upt8BfjZJWXgGOXqGxXDvPJGDf5s31FSj0AckMquG+7Z0zbsutD oHNz/M86a8AXvwiZawir94YsTlfiV+f4wOGMuQ4fSS1hhE0ctqyxicxILjJjja30FENb B9pD/VT3CLtAKiYMUGdeSGz2bzlEzIZORiYtX5i/Qy4ziWAq9nVsw8RF5xlzyws52dsW y3eajFkujfQlL3ED9QaKokKgheDElY0qzltpkp4Wpur/HbtMLFHq2fAk1UBm27PhJN0u 2HTdwOBsMqbkL7MhcVAzDH2wcbYYA/vzYE7fdWwRne8aWCayWylpbvnAqVpJCgTQWkcu DSuw== X-Gm-Message-State: AGi0PuYY0AiNHlZgBt0Ay5zBNMEDtTK4P6yjGFlupN9/ZvmA6LB5RVx1 rI3d+fRCPKU7514x8WhHAIOIiABW8fM= X-Google-Smtp-Source: APiQypKFj+8RW/B1CfE67L7JkddqVNNSkLQ83S8XRPC3soXdf3k/KKk5wo+il1gd6Tbi4gC+yHe6VQ== X-Received: by 2002:a63:cd08:: with SMTP id i8mr8301816pgg.55.1587225415562; Sat, 18 Apr 2020 08:56:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 1/3] tcg: Improve vector tail clearing Date: Sat, 18 Apr 2020 08:56:49 -0700 Message-Id: <20200418155651.3901-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200418155651.3901-1-richard.henderson@linaro.org> References: <20200418155651.3901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Better handling of non-power-of-2 tails as seen with Arm 8-byte vector operations. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- tcg/tcg-op-gvec.c | 82 ++++++++++++++++++++++++++++++++++++----------- 1 file changed, 63 insertions(+), 19 deletions(-) diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c index 5a6cc19812..43cac1a0bf 100644 --- a/tcg/tcg-op-gvec.c +++ b/tcg/tcg-op-gvec.c @@ -326,11 +326,34 @@ void tcg_gen_gvec_5_ptr(uint32_t dofs, uint32_t aofs,= uint32_t bofs, in units of LNSZ. This limits the expansion of inline code. */ static inline bool check_size_impl(uint32_t oprsz, uint32_t lnsz) { - if (oprsz % lnsz =3D=3D 0) { - uint32_t lnct =3D oprsz / lnsz; - return lnct >=3D 1 && lnct <=3D MAX_UNROLL; + uint32_t q, r; + + if (oprsz < lnsz) { + return false; } - return false; + + q =3D oprsz / lnsz; + r =3D oprsz % lnsz; + tcg_debug_assert((r & 7) =3D=3D 0); + + if (lnsz < 16) { + /* For sizes below 16, accept no remainder. */ + if (r !=3D 0) { + return false; + } + } else { + /* + * Recall that ARM SVE allows vector sizes that are not a + * power of 2, but always a multiple of 16. The intent is + * that e.g. size =3D=3D 80 would be expanded with 2x32 + 1x16. + * In addition, expand_clr needs to handle a multiple of 8. + * Thus we can handle the tail with one more operation per + * diminishing power of 2. + */ + q +=3D ctpop32(r); + } + + return q <=3D MAX_UNROLL; } =20 static void expand_clr(uint32_t dofs, uint32_t maxsz); @@ -402,22 +425,31 @@ static void gen_dup_i64(unsigned vece, TCGv_i64 out, = TCGv_i64 in) static TCGType choose_vector_type(const TCGOpcode *list, unsigned vece, uint32_t size, bool prefer_i64) { - if (TCG_TARGET_HAS_v256 && check_size_impl(size, 32)) { - /* - * Recall that ARM SVE allows vector sizes that are not a - * power of 2, but always a multiple of 16. The intent is - * that e.g. size =3D=3D 80 would be expanded with 2x32 + 1x16. - * It is hard to imagine a case in which v256 is supported - * but v128 is not, but check anyway. - */ - if (tcg_can_emit_vecop_list(list, TCG_TYPE_V256, vece) - && (size % 32 =3D=3D 0 - || tcg_can_emit_vecop_list(list, TCG_TYPE_V128, vece))) { - return TCG_TYPE_V256; - } + /* + * Recall that ARM SVE allows vector sizes that are not a + * power of 2, but always a multiple of 16. The intent is + * that e.g. size =3D=3D 80 would be expanded with 2x32 + 1x16. + * It is hard to imagine a case in which v256 is supported + * but v128 is not, but check anyway. + * In addition, expand_clr needs to handle a multiple of 8. + */ + if (TCG_TARGET_HAS_v256 && + check_size_impl(size, 32) && + tcg_can_emit_vecop_list(list, TCG_TYPE_V256, vece) && + (!(size & 16) || + (TCG_TARGET_HAS_v128 && + tcg_can_emit_vecop_list(list, TCG_TYPE_V128, vece))) && + (!(size & 8) || + (TCG_TARGET_HAS_v64 && + tcg_can_emit_vecop_list(list, TCG_TYPE_V64, vece)))) { + return TCG_TYPE_V256; } - if (TCG_TARGET_HAS_v128 && check_size_impl(size, 16) - && tcg_can_emit_vecop_list(list, TCG_TYPE_V128, vece)) { + if (TCG_TARGET_HAS_v128 && + check_size_impl(size, 16) && + tcg_can_emit_vecop_list(list, TCG_TYPE_V128, vece) && + (!(size & 8) || + (TCG_TARGET_HAS_v64 && + tcg_can_emit_vecop_list(list, TCG_TYPE_V64, vece)))) { return TCG_TYPE_V128; } if (TCG_TARGET_HAS_v64 && !prefer_i64 && check_size_impl(size, 8) @@ -432,6 +464,18 @@ static void do_dup_store(TCGType type, uint32_t dofs, = uint32_t oprsz, { uint32_t i =3D 0; =20 + tcg_debug_assert(oprsz >=3D 8); + + /* + * This may be expand_clr for the tail of an operation, e.g. + * oprsz =3D=3D 8 && maxsz =3D=3D 64. The first 8 bytes of this store + * are misaligned wrt the maximum vector size, so do that first. + */ + if (dofs & 8) { + tcg_gen_stl_vec(t_vec, cpu_env, dofs + i, TCG_TYPE_V64); + i +=3D 8; + } + switch (type) { case TCG_TYPE_V256: /* --=20 2.20.1 From nobody Fri May 17 10:13:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1587225496; cv=none; d=zohomail.com; s=zohoarc; b=bgGdSivwj5hackxuObOG8hTOogLIIT1yRXRsTYPkwH/DK/0Tk5gIc84eFAzaNZaaH1VRk4lHPV+9luLtMAND4gEYN3oD4eqWCvvwHZinRUlcHUl2xlUg8uZCImYxRNxS4nq4zocZiBfN9lYJs2D8S5xsZV2ZqyqcnqBX3nDKURM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1587225496; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=7uX8ThqikoEq018tD9k93q1ZZz6mGC+ypRxdEu5/0Vw=; b=hvBcnsEFtUsuZ4kJu3aEZ4qH67jYc8Qa2/SLXJ+SHUyz3JFMnaCs26qCN8OXQbpf/2JMaEPejvKKVfnMBCrFeC3CadInOxdAH9lSNomD6sGqo/72FnJ1tuhcWoUhjpWqLD3nTKQWw3qnGy5zKe5lbt0+MXkpyNJx1VP2W74RSAQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1587225496556858.6658238290454; Sat, 18 Apr 2020 08:58:16 -0700 (PDT) Received: from localhost ([::1]:59128 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jPprD-0008MX-4w for importer@patchew.org; Sat, 18 Apr 2020 11:58:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44243) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jPppz-0006wk-IZ for qemu-devel@nongnu.org; Sat, 18 Apr 2020 11:57:00 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jPppy-0002kN-AZ for qemu-devel@nongnu.org; Sat, 18 Apr 2020 11:56:59 -0400 Received: from mail-pl1-x642.google.com ([2607:f8b0:4864:20::642]:41575) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1jPppy-0002iy-57 for qemu-devel@nongnu.org; Sat, 18 Apr 2020 11:56:58 -0400 Received: by mail-pl1-x642.google.com with SMTP id d24so2191432pll.8 for ; Sat, 18 Apr 2020 08:56:58 -0700 (PDT) Received: from localhost.localdomain (174-21-149-226.tukw.qwest.net. [174.21.149.226]) by smtp.gmail.com with ESMTPSA id m189sm13928532pfm.60.2020.04.18.08.56.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Apr 2020 08:56:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7uX8ThqikoEq018tD9k93q1ZZz6mGC+ypRxdEu5/0Vw=; b=LHcXxhgYH8NUJ32OqE1+8L5xl0iipBPoiI1xa0YRy0pH1jm6NAkOc7oaVccIVeOy3g T/F7+wIYib6zNYSm5gebCftgMbwR0CO+WqT5y6Ihe94VFe4KW7T2TSxyvvvRpSBMBJvi 1Bi031xX1jFptSs2i/zmLZzqEWe1pftpO1AgrHDdtbIg4A8b2go7f8JA/utmrKFpKOV0 BPSL4kLzLxG2JYuwLxpt5Wdoxa6Fp6/38c898k58rVcE1QOy55+v5l9WFVFUnEm5fuD8 cBfwjdV9xId0Zq2olmCJwVyb/Cq8CcJEiPr9Uecr+3UApJQMR2L0WrWhEIrYs75MdjNH zxsg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7uX8ThqikoEq018tD9k93q1ZZz6mGC+ypRxdEu5/0Vw=; b=qXf92rVBILiMmldNmEy/gzISoFbfXF+5tX32cRjmqqtbndVCubfx5gQrC5s0oPMap3 gqYv1Z4upDLBtV7+6TVj0H9jCKZQ5W+23UkhqWf7ye4LMY7ET9MEvGI3o9IsfZ5ois3p is38ouSA/EKqiuMPNnwcagYczn5yE90o3SHYitllo6osRPUhNsAamqJp5H20cyx1v2gd F//Z9A1YoYtWmpOmquWjFwsO7aIf1PgXunvK8Jks11cvo/LclluKHaf9/MRBPGi+AHLp nU0RLmrJWXKuAIT59bOrV7Fxr0SxqOdX9ecAw0iSaScJ7AfiMpwn0yyEq/f2MpqYCvBG D86g== X-Gm-Message-State: AGi0PuYan1BHP1+AvPupjqVsNk2aCuH69pKPSrsIB65zPklzlUs+9CdN OlYueQu+O0saGC4UOjnBRAIOwsLnmdw= X-Google-Smtp-Source: APiQypInsW1j8bdviOTcpHgkM9TbZW04QcFv9JYn8hnkpQGzfK5Qecb4gC5kqT6eMOzlPVUatZRLpQ== X-Received: by 2002:a17:90a:fb4e:: with SMTP id iq14mr11022943pjb.146.1587225416810; Sat, 18 Apr 2020 08:56:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 2/3] target/arm: Use tcg_gen_gvec_mov for clear_vec_high Date: Sat, 18 Apr 2020 08:56:50 -0700 Message-Id: <20200418155651.3901-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200418155651.3901-1-richard.henderson@linaro.org> References: <20200418155651.3901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" The 8-byte store for the end a !is_q operation can be merged with the other stores. Use a no-op vector move to trigger the expand_clr portion of tcg_gen_gvec_mov. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/translate-a64.c | 10 ++-------- 1 file changed, 2 insertions(+), 8 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 095638e09a..d57aa54d6a 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -513,14 +513,8 @@ static void clear_vec_high(DisasContext *s, bool is_q,= int rd) unsigned ofs =3D fp_reg_offset(s, rd, MO_64); unsigned vsz =3D vec_full_reg_size(s); =20 - if (!is_q) { - TCGv_i64 tcg_zero =3D tcg_const_i64(0); - tcg_gen_st_i64(tcg_zero, cpu_env, ofs + 8); - tcg_temp_free_i64(tcg_zero); - } - if (vsz > 16) { - tcg_gen_gvec_dup_imm(MO_64, ofs + 16, vsz - 16, vsz - 16, 0); - } + /* Nop move, with side effect of clearing the tail. */ + tcg_gen_gvec_mov(MO_64, ofs, ofs, is_q ? 16 : 8, vsz); } =20 void write_fp_dreg(DisasContext *s, int reg, TCGv_i64 v) --=20 2.20.1 From nobody Fri May 17 10:13:27 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1587225576; cv=none; d=zohomail.com; s=zohoarc; b=lPi+7TnWwAjR3JVnV9ODgmN5YBaZlyVSCTU1zVGIYjxI9ckwHdnBI2N8dk27YEkZL08/6yXopKFJx5Dk7ETzmwtvdI6WWSRVZ2XpM/9WAStn0iwzkQ4bruU2dkO0QxRQdgqoaGn3KIOXaU7LzsxV7UNdYfPy2I39wo7mv6YsxLc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1587225576; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yo0JFxbi1JQMS1C5IWuwNJ4cHonOrcnEkwrUJKkp0u0=; b=dQhmlXdHzoo1XhHCw9dhTyX3YpFNjCZPjpY4V03+ajXSoZ+CqdVS3qVDezJoMwEpMa+KQuQL0SMDbAh54jbVCAeE/VHf2UIAGFnYdVlZgfxeRwuyX7yAzcyimux+z4pywDRSDb7uSCk5rv40p6LuXg1WDui5mjJYC5z5AC8L1Ss= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1587225576755852.7276914544451; Sat, 18 Apr 2020 08:59:36 -0700 (PDT) Received: from localhost ([::1]:59154 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jPpsV-00020n-Dt for importer@patchew.org; Sat, 18 Apr 2020 11:59:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44254) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jPpq0-0006yV-RR for qemu-devel@nongnu.org; Sat, 18 Apr 2020 11:57:02 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jPppz-0002mj-Hb for qemu-devel@nongnu.org; Sat, 18 Apr 2020 11:57:00 -0400 Received: from mail-pj1-x1044.google.com ([2607:f8b0:4864:20::1044]:53306) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1jPppz-0002lU-Bh for qemu-devel@nongnu.org; Sat, 18 Apr 2020 11:56:59 -0400 Received: by mail-pj1-x1044.google.com with SMTP id hi11so1829753pjb.3 for ; Sat, 18 Apr 2020 08:56:59 -0700 (PDT) Received: from localhost.localdomain (174-21-149-226.tukw.qwest.net. [174.21.149.226]) by smtp.gmail.com with ESMTPSA id m189sm13928532pfm.60.2020.04.18.08.56.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 18 Apr 2020 08:56:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yo0JFxbi1JQMS1C5IWuwNJ4cHonOrcnEkwrUJKkp0u0=; b=OAOk90dPG7IQflKcg2lah7u11hKgaZp3mdfoPlM9YQlUqvyLaXotiOBmUqHIbxEJXt sS0zX5/eu6F00A4PIHUobNr76qZ+K9mT5FvoCGLqIe9y4D/Ml43uAu9W3vvwobUI7nsW b61GDK6aDiv/6IMTiW1jXigT4Za/s8evxh614FgOiKXa2StY1aeJ5CudLM8I2cNqU7Qk Au8CqPmBarbUnOTaZXovwflbGaN2gxizOMFOWXHBQV5q4WCSGHhtREdQt/xsY2lZEODW E0HOWSEK2m/rtxEEvtTq80cXM+Dl+x+IWiOzadSSyBOumLEFPX3Kb1UgMgMK+3bkeO7h Kgjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yo0JFxbi1JQMS1C5IWuwNJ4cHonOrcnEkwrUJKkp0u0=; b=tNpgeSey7lKdVKrG15m5htDwnahIRBWgv+++7WKfUyM5rfalJTA2ka/6yiJ3/UO5Sc RzzF6EaI8rrk9ug9c/fOma1ZmXe0SvFuac0rd2yMIyAHGUw+mHcNv3fHTONop4d+vtio +4pVGHMloGsNKTbg/0+hBbdj4K4fCXgLAlZGcwU+gM8UulHJy8VCzUAQxSJV6X0EKFk7 U2d6KBeNgkH51VVyxMbivSfz05uOxMp+7fYQjJV3iP3Hc1wgntIoozX1naPfgr7vZrfn mc/RY9kd3xR1Pwqzq6cr0vwo5KoJD6Zu1xuGKNL2HAgiz4sFnmEwuEOOCAtTg4GQ4+3N 7vfA== X-Gm-Message-State: AGi0PuY3JOICg1QOLdM8sWwx275bshkD8iDRuMvLhfFVfOb4q+UwCYIK xYZggm3MqQpHr25M8B+tfK2jD6Tg6Xc= X-Google-Smtp-Source: APiQypJ4MDMhghhhF3T6drb/MXMrCCuCvV121GiBZmNkY+4F2JIvWVXpa1F78+izPB+LxtjWXBdaDQ== X-Received: by 2002:a17:90a:aa84:: with SMTP id l4mr2208196pjq.177.1587225418014; Sat, 18 Apr 2020 08:56:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 3/3] target/arm: Use clear_vec_high more effectively Date: Sat, 18 Apr 2020 08:56:51 -0700 Message-Id: <20200418155651.3901-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200418155651.3901-1-richard.henderson@linaro.org> References: <20200418155651.3901-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1044 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Do not explicitly store zero to the NEON high part when we can pass !is_q to clear_vec_high. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/translate-a64.c | 59 +++++++++++++++++++++++--------------- 1 file changed, 36 insertions(+), 23 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index d57aa54d6a..bf82a2e115 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -948,11 +948,10 @@ static void do_fp_ld(DisasContext *s, int destidx, TC= Gv_i64 tcg_addr, int size) { /* This always zero-extends and writes to a full 128 bit wide vector */ TCGv_i64 tmplo =3D tcg_temp_new_i64(); - TCGv_i64 tmphi; + TCGv_i64 tmphi =3D NULL; =20 if (size < 4) { MemOp memop =3D s->be_data + size; - tmphi =3D tcg_const_i64(0); tcg_gen_qemu_ld_i64(tmplo, tcg_addr, get_mem_index(s), memop); } else { bool be =3D s->be_data =3D=3D MO_BE; @@ -970,12 +969,13 @@ static void do_fp_ld(DisasContext *s, int destidx, TC= Gv_i64 tcg_addr, int size) } =20 tcg_gen_st_i64(tmplo, cpu_env, fp_reg_offset(s, destidx, MO_64)); - tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(s, destidx)); - tcg_temp_free_i64(tmplo); - tcg_temp_free_i64(tmphi); =20 - clear_vec_high(s, true, destidx); + if (tmphi) { + tcg_gen_st_i64(tmphi, cpu_env, fp_reg_hi_offset(s, destidx)); + tcg_temp_free_i64(tmphi); + } + clear_vec_high(s, tmphi !=3D NULL, destidx); } =20 /* @@ -6969,8 +6969,8 @@ static void disas_simd_ext(DisasContext *s, uint32_t = insn) return; } =20 - tcg_resh =3D tcg_temp_new_i64(); tcg_resl =3D tcg_temp_new_i64(); + tcg_resh =3D NULL; =20 /* Vd gets bits starting at pos bits into Vm:Vn. This is * either extracting 128 bits from a 128:128 concatenation, or @@ -6982,7 +6982,6 @@ static void disas_simd_ext(DisasContext *s, uint32_t = insn) read_vec_element(s, tcg_resh, rm, 0, MO_64); do_ext64(s, tcg_resh, tcg_resl, pos); } - tcg_gen_movi_i64(tcg_resh, 0); } else { TCGv_i64 tcg_hh; typedef struct { @@ -6997,6 +6996,7 @@ static void disas_simd_ext(DisasContext *s, uint32_t = insn) pos -=3D 64; } =20 + tcg_resh =3D tcg_temp_new_i64(); read_vec_element(s, tcg_resl, elt->reg, elt->elt, MO_64); elt++; read_vec_element(s, tcg_resh, elt->reg, elt->elt, MO_64); @@ -7012,9 +7012,12 @@ static void disas_simd_ext(DisasContext *s, uint32_t= insn) =20 write_vec_element(s, tcg_resl, rd, 0, MO_64); tcg_temp_free_i64(tcg_resl); - write_vec_element(s, tcg_resh, rd, 1, MO_64); - tcg_temp_free_i64(tcg_resh); - clear_vec_high(s, true, rd); + + if (is_q) { + write_vec_element(s, tcg_resh, rd, 1, MO_64); + tcg_temp_free_i64(tcg_resh); + } + clear_vec_high(s, is_q, rd); } =20 /* TBL/TBX @@ -7051,17 +7054,21 @@ static void disas_simd_tb(DisasContext *s, uint32_t= insn) * the input. */ tcg_resl =3D tcg_temp_new_i64(); - tcg_resh =3D tcg_temp_new_i64(); + tcg_resh =3D NULL; =20 if (is_tblx) { read_vec_element(s, tcg_resl, rd, 0, MO_64); } else { tcg_gen_movi_i64(tcg_resl, 0); } - if (is_tblx && is_q) { - read_vec_element(s, tcg_resh, rd, 1, MO_64); - } else { - tcg_gen_movi_i64(tcg_resh, 0); + + if (is_q) { + tcg_resh =3D tcg_temp_new_i64(); + if (is_tblx) { + read_vec_element(s, tcg_resh, rd, 1, MO_64); + } else { + tcg_gen_movi_i64(tcg_resh, 0); + } } =20 tcg_idx =3D tcg_temp_new_i64(); @@ -7081,9 +7088,12 @@ static void disas_simd_tb(DisasContext *s, uint32_t = insn) =20 write_vec_element(s, tcg_resl, rd, 0, MO_64); tcg_temp_free_i64(tcg_resl); - write_vec_element(s, tcg_resh, rd, 1, MO_64); - tcg_temp_free_i64(tcg_resh); - clear_vec_high(s, true, rd); + + if (is_q) { + write_vec_element(s, tcg_resh, rd, 1, MO_64); + tcg_temp_free_i64(tcg_resh); + } + clear_vec_high(s, is_q, rd); } =20 /* ZIP/UZP/TRN @@ -7120,7 +7130,7 @@ static void disas_simd_zip_trn(DisasContext *s, uint3= 2_t insn) } =20 tcg_resl =3D tcg_const_i64(0); - tcg_resh =3D tcg_const_i64(0); + tcg_resh =3D is_q ? tcg_const_i64(0) : NULL; tcg_res =3D tcg_temp_new_i64(); =20 for (i =3D 0; i < elements; i++) { @@ -7171,9 +7181,12 @@ static void disas_simd_zip_trn(DisasContext *s, uint= 32_t insn) =20 write_vec_element(s, tcg_resl, rd, 0, MO_64); tcg_temp_free_i64(tcg_resl); - write_vec_element(s, tcg_resh, rd, 1, MO_64); - tcg_temp_free_i64(tcg_resh); - clear_vec_high(s, true, rd); + + if (is_q) { + write_vec_element(s, tcg_resh, rd, 1, MO_64); + tcg_temp_free_i64(tcg_resh); + } + clear_vec_high(s, is_q, rd); } =20 /* --=20 2.20.1