From nobody Thu May 16 14:23:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1586955882; cv=none; d=zohomail.com; s=zohoarc; b=QAupQG7b9w+U6F68OcDLvtCn28tiUfpYg+OhF8Cm4ghwYmIFVT62B38EN7TpvmFdfcSV0DNn2V7iulwzyPqZbC9Fnk5OMXlQCGioL3VPYA8d2DSTs4WENlXbL4oU+NTX7Eb4QCpaNcuL454ZVlixABHNl5N49qVv2s6TOuFoH14= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1586955882; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0dcojw3pfq0EBnrJXIiT/Sh0JzAVywjT95QUZsriteI=; b=F8ToG+zQQAOZpAhe/2OUK9KURmoOj3iwv8JYbBLNtkei0/A99nMFsxONy+yQQrHgfPt/S2VME06aQKpnCarvvGm7hjmYzoUltxyHI5rylfNY8NL3n9gszfs48HbLlTu664dM3QGdL7J/VzPrCTvcpkZKjy7kxb81F6N2qhtY5/0= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1586955882554594.3047819823025; Wed, 15 Apr 2020 06:04:42 -0700 (PDT) Received: from localhost ([::1]:49626 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jOhib-0000lW-2S for importer@patchew.org; Wed, 15 Apr 2020 09:04:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33541) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jOhgP-00073U-2c for qemu-devel@nongnu.org; Wed, 15 Apr 2020 09:02:26 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jOhgN-0004A3-Tr for qemu-devel@nongnu.org; Wed, 15 Apr 2020 09:02:24 -0400 Received: from charlie.dont.surf ([128.199.63.193]:48526) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jOhgL-00044j-AH; Wed, 15 Apr 2020 09:02:21 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id D5D93BF9DF; Wed, 15 Apr 2020 13:02:19 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v2 01/16] nvme: fix pci doorbell size calculation Date: Wed, 15 Apr 2020 15:01:44 +0200 Message-Id: <20200415130159.611361-2-its@irrelevant.dk> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200415130159.611361-1-its@irrelevant.dk> References: <20200415130159.611361-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 128.199.63.193 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen The size of the BAR is 0x1000 (main registers) + 8 bytes for each queue. Currently, the size of the BAR is calculated like so: n->reg_size =3D pow2ceil(0x1004 + 2 * (n->num_queues + 1) * 4); Since the 'num_queues' parameter already accounts for the admin queue, this should in any case not need to be incremented by one. Also, the size should be initialized to (0x1000). n->reg_size =3D pow2ceil(0x1000 + 2 * n->num_queues * 4); This, with the default value of num_queues (64), we will set aside room for 1 admin queue and 63 I/O queues (4 bytes per doorbell, 2 doorbells per queue). Signed-off-by: Klaus Jensen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by. Reviewed-by's ;) Reviewed-by: Keith Busch Reviewed-by: Maxim Levitsky --- hw/block/nvme.c | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index d28335cbf377..5b5f75c9d29e 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -43,6 +43,9 @@ #include "trace.h" #include "nvme.h" =20 +#define NVME_REG_SIZE 0x1000 +#define NVME_DB_SIZE 4 + #define NVME_GUEST_ERR(trace, fmt, ...) \ do { \ (trace_##trace)(__VA_ARGS__); \ @@ -1345,7 +1348,9 @@ static void nvme_realize(PCIDevice *pci_dev, Error **= errp) pcie_endpoint_cap_init(pci_dev, 0x80); =20 n->num_namespaces =3D 1; - n->reg_size =3D pow2ceil(0x1004 + 2 * (n->num_queues + 1) * 4); + + /* num_queues is really number of pairs, so each has two doorbells */ + n->reg_size =3D pow2ceil(NVME_REG_SIZE + 2 * n->num_queues * NVME_DB_S= IZE); n->ns_size =3D bs_size / (uint64_t)n->num_namespaces; =20 n->namespaces =3D g_new0(NvmeNamespace, n->num_namespaces); --=20 2.26.0 From nobody Thu May 16 14:23:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1586956207; cv=none; d=zohomail.com; s=zohoarc; b=RuM8O25Q6RrtsDQX/od74r/krt4RuYRMGDBTqBwgqREa6z2kJvrFpDGeXp7+qn9vSoYZzmthAmB5UZCBv5+UXu+wHnv8yJMpwyghD2P+uBRFOVX2wWwDxZnyMJNW+2RYw4mVZp3ZLYAnoW16lBcg3oapurGp0wSxL75QtHrSQ/A= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1586956207; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ft35Sf0ySYMiBxUZ2+3bfyCi2Dw86e6+o0LNmmtkSBs=; b=huY9zsUPPP0WoQI3apFxEj5FT/vkfuXD4kPc/+KwnQv+rGz8x1Tgcs+IutHJYIGdCmzqJsqu3ykRoFEdATNObKAkP0H15ntXASPRPqpW+c/evndsgXYFzM+dCr0gAmepTkaI0drU6IhPVkUvt48X9qq1nbB5y+mYa0KQCPAKBFY= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1586956207074909.3184874633417; Wed, 15 Apr 2020 06:10:07 -0700 (PDT) Received: from localhost ([::1]:49772 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jOhnp-0003LS-Hf for importer@patchew.org; Wed, 15 Apr 2020 09:10:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33774) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jOhgb-0007M0-Qs for qemu-devel@nongnu.org; Wed, 15 Apr 2020 09:02:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jOhgW-0004OW-O8 for qemu-devel@nongnu.org; Wed, 15 Apr 2020 09:02:37 -0400 Received: from charlie.dont.surf ([128.199.63.193]:48534) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jOhgL-00045I-Q7; Wed, 15 Apr 2020 09:02:22 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id 6E827BF9F3; Wed, 15 Apr 2020 13:02:20 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v2 02/16] nvme: rename trace events to pci_nvme Date: Wed, 15 Apr 2020 15:01:45 +0200 Message-Id: <20200415130159.611361-3-its@irrelevant.dk> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200415130159.611361-1-its@irrelevant.dk> References: <20200415130159.611361-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 128.199.63.193 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen Change the prefix of all nvme device related trace events to 'pci_nvme' to not clash with trace events from the nvme block driver. Signed-off-by: Klaus Jensen Acked-by. Reviewed-by's ;) Reviewed-by: Keith Busch Reviewed-by: Maxim Levitsky Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/block/nvme.c | 190 +++++++++++++++++++++--------------------- hw/block/trace-events | 172 +++++++++++++++++++------------------- 2 files changed, 180 insertions(+), 182 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 5b5f75c9d29e..931ddeb26ba0 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -115,16 +115,16 @@ static void nvme_irq_assert(NvmeCtrl *n, NvmeCQueue *= cq) { if (cq->irq_enabled) { if (msix_enabled(&(n->parent_obj))) { - trace_nvme_irq_msix(cq->vector); + trace_pci_nvme_irq_msix(cq->vector); msix_notify(&(n->parent_obj), cq->vector); } else { - trace_nvme_irq_pin(); + trace_pci_nvme_irq_pin(); assert(cq->cqid < 64); n->irq_status |=3D 1 << cq->cqid; nvme_irq_check(n); } } else { - trace_nvme_irq_masked(); + trace_pci_nvme_irq_masked(); } } =20 @@ -149,7 +149,7 @@ static uint16_t nvme_map_prp(QEMUSGList *qsg, QEMUIOVec= tor *iov, uint64_t prp1, int num_prps =3D (len >> n->page_bits) + 1; =20 if (unlikely(!prp1)) { - trace_nvme_err_invalid_prp(); + trace_pci_nvme_err_invalid_prp(); return NVME_INVALID_FIELD | NVME_DNR; } else if (n->cmbsz && prp1 >=3D n->ctrl_mem.addr && prp1 < n->ctrl_mem.addr + int128_get64(n->ctrl_mem.size)) { @@ -163,7 +163,7 @@ static uint16_t nvme_map_prp(QEMUSGList *qsg, QEMUIOVec= tor *iov, uint64_t prp1, len -=3D trans_len; if (len) { if (unlikely(!prp2)) { - trace_nvme_err_invalid_prp2_missing(); + trace_pci_nvme_err_invalid_prp2_missing(); goto unmap; } if (len > n->page_size) { @@ -179,7 +179,7 @@ static uint16_t nvme_map_prp(QEMUSGList *qsg, QEMUIOVec= tor *iov, uint64_t prp1, =20 if (i =3D=3D n->max_prp_ents - 1 && len > n->page_size) { if (unlikely(!prp_ent || prp_ent & (n->page_size - 1))= ) { - trace_nvme_err_invalid_prplist_ent(prp_ent); + trace_pci_nvme_err_invalid_prplist_ent(prp_ent); goto unmap; } =20 @@ -192,7 +192,7 @@ static uint16_t nvme_map_prp(QEMUSGList *qsg, QEMUIOVec= tor *iov, uint64_t prp1, } =20 if (unlikely(!prp_ent || prp_ent & (n->page_size - 1))) { - trace_nvme_err_invalid_prplist_ent(prp_ent); + trace_pci_nvme_err_invalid_prplist_ent(prp_ent); goto unmap; } =20 @@ -207,7 +207,7 @@ static uint16_t nvme_map_prp(QEMUSGList *qsg, QEMUIOVec= tor *iov, uint64_t prp1, } } else { if (unlikely(prp2 & (n->page_size - 1))) { - trace_nvme_err_invalid_prp2_align(prp2); + trace_pci_nvme_err_invalid_prp2_align(prp2); goto unmap; } if (qsg->nsg) { @@ -255,20 +255,20 @@ static uint16_t nvme_dma_read_prp(NvmeCtrl *n, uint8_= t *ptr, uint32_t len, QEMUIOVector iov; uint16_t status =3D NVME_SUCCESS; =20 - trace_nvme_dma_read(prp1, prp2); + trace_pci_nvme_dma_read(prp1, prp2); =20 if (nvme_map_prp(&qsg, &iov, prp1, prp2, len, n)) { return NVME_INVALID_FIELD | NVME_DNR; } if (qsg.nsg > 0) { if (unlikely(dma_buf_read(ptr, len, &qsg))) { - trace_nvme_err_invalid_dma(); + trace_pci_nvme_err_invalid_dma(); status =3D NVME_INVALID_FIELD | NVME_DNR; } qemu_sglist_destroy(&qsg); } else { if (unlikely(qemu_iovec_from_buf(&iov, 0, ptr, len) !=3D len)) { - trace_nvme_err_invalid_dma(); + trace_pci_nvme_err_invalid_dma(); status =3D NVME_INVALID_FIELD | NVME_DNR; } qemu_iovec_destroy(&iov); @@ -357,7 +357,7 @@ static uint16_t nvme_write_zeros(NvmeCtrl *n, NvmeNames= pace *ns, NvmeCmd *cmd, uint32_t count =3D nlb << data_shift; =20 if (unlikely(slba + nlb > ns->id_ns.nsze)) { - trace_nvme_err_invalid_lba_range(slba, nlb, ns->id_ns.nsze); + trace_pci_nvme_err_invalid_lba_range(slba, nlb, ns->id_ns.nsze); return NVME_LBA_RANGE | NVME_DNR; } =20 @@ -385,11 +385,11 @@ static uint16_t nvme_rw(NvmeCtrl *n, NvmeNamespace *n= s, NvmeCmd *cmd, int is_write =3D rw->opcode =3D=3D NVME_CMD_WRITE ? 1 : 0; enum BlockAcctType acct =3D is_write ? BLOCK_ACCT_WRITE : BLOCK_ACCT_R= EAD; =20 - trace_nvme_rw(is_write ? "write" : "read", nlb, data_size, slba); + trace_pci_nvme_rw(is_write ? "write" : "read", nlb, data_size, slba); =20 if (unlikely((slba + nlb) > ns->id_ns.nsze)) { block_acct_invalid(blk_get_stats(n->conf.blk), acct); - trace_nvme_err_invalid_lba_range(slba, nlb, ns->id_ns.nsze); + trace_pci_nvme_err_invalid_lba_range(slba, nlb, ns->id_ns.nsze); return NVME_LBA_RANGE | NVME_DNR; } =20 @@ -424,7 +424,7 @@ static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeCmd *cmd, = NvmeRequest *req) uint32_t nsid =3D le32_to_cpu(cmd->nsid); =20 if (unlikely(nsid =3D=3D 0 || nsid > n->num_namespaces)) { - trace_nvme_err_invalid_ns(nsid, n->num_namespaces); + trace_pci_nvme_err_invalid_ns(nsid, n->num_namespaces); return NVME_INVALID_NSID | NVME_DNR; } =20 @@ -438,7 +438,7 @@ static uint16_t nvme_io_cmd(NvmeCtrl *n, NvmeCmd *cmd, = NvmeRequest *req) case NVME_CMD_READ: return nvme_rw(n, ns, cmd, req); default: - trace_nvme_err_invalid_opc(cmd->opcode); + trace_pci_nvme_err_invalid_opc(cmd->opcode); return NVME_INVALID_OPCODE | NVME_DNR; } } @@ -463,11 +463,11 @@ static uint16_t nvme_del_sq(NvmeCtrl *n, NvmeCmd *cmd) uint16_t qid =3D le16_to_cpu(c->qid); =20 if (unlikely(!qid || nvme_check_sqid(n, qid))) { - trace_nvme_err_invalid_del_sq(qid); + trace_pci_nvme_err_invalid_del_sq(qid); return NVME_INVALID_QID | NVME_DNR; } =20 - trace_nvme_del_sq(qid); + trace_pci_nvme_del_sq(qid); =20 sq =3D n->sq[qid]; while (!QTAILQ_EMPTY(&sq->out_req_list)) { @@ -531,26 +531,26 @@ static uint16_t nvme_create_sq(NvmeCtrl *n, NvmeCmd *= cmd) uint16_t qflags =3D le16_to_cpu(c->sq_flags); uint64_t prp1 =3D le64_to_cpu(c->prp1); =20 - trace_nvme_create_sq(prp1, sqid, cqid, qsize, qflags); + trace_pci_nvme_create_sq(prp1, sqid, cqid, qsize, qflags); =20 if (unlikely(!cqid || nvme_check_cqid(n, cqid))) { - trace_nvme_err_invalid_create_sq_cqid(cqid); + trace_pci_nvme_err_invalid_create_sq_cqid(cqid); return NVME_INVALID_CQID | NVME_DNR; } if (unlikely(!sqid || !nvme_check_sqid(n, sqid))) { - trace_nvme_err_invalid_create_sq_sqid(sqid); + trace_pci_nvme_err_invalid_create_sq_sqid(sqid); return NVME_INVALID_QID | NVME_DNR; } if (unlikely(!qsize || qsize > NVME_CAP_MQES(n->bar.cap))) { - trace_nvme_err_invalid_create_sq_size(qsize); + trace_pci_nvme_err_invalid_create_sq_size(qsize); return NVME_MAX_QSIZE_EXCEEDED | NVME_DNR; } if (unlikely(!prp1 || prp1 & (n->page_size - 1))) { - trace_nvme_err_invalid_create_sq_addr(prp1); + trace_pci_nvme_err_invalid_create_sq_addr(prp1); return NVME_INVALID_FIELD | NVME_DNR; } if (unlikely(!(NVME_SQ_FLAGS_PC(qflags)))) { - trace_nvme_err_invalid_create_sq_qflags(NVME_SQ_FLAGS_PC(qflags)); + trace_pci_nvme_err_invalid_create_sq_qflags(NVME_SQ_FLAGS_PC(qflag= s)); return NVME_INVALID_FIELD | NVME_DNR; } sq =3D g_malloc0(sizeof(*sq)); @@ -576,17 +576,17 @@ static uint16_t nvme_del_cq(NvmeCtrl *n, NvmeCmd *cmd) uint16_t qid =3D le16_to_cpu(c->qid); =20 if (unlikely(!qid || nvme_check_cqid(n, qid))) { - trace_nvme_err_invalid_del_cq_cqid(qid); + trace_pci_nvme_err_invalid_del_cq_cqid(qid); return NVME_INVALID_CQID | NVME_DNR; } =20 cq =3D n->cq[qid]; if (unlikely(!QTAILQ_EMPTY(&cq->sq_list))) { - trace_nvme_err_invalid_del_cq_notempty(qid); + trace_pci_nvme_err_invalid_del_cq_notempty(qid); return NVME_INVALID_QUEUE_DEL; } nvme_irq_deassert(n, cq); - trace_nvme_del_cq(qid); + trace_pci_nvme_del_cq(qid); nvme_free_cq(cq, n); return NVME_SUCCESS; } @@ -619,27 +619,27 @@ static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeCmd *= cmd) uint16_t qflags =3D le16_to_cpu(c->cq_flags); uint64_t prp1 =3D le64_to_cpu(c->prp1); =20 - trace_nvme_create_cq(prp1, cqid, vector, qsize, qflags, - NVME_CQ_FLAGS_IEN(qflags) !=3D 0); + trace_pci_nvme_create_cq(prp1, cqid, vector, qsize, qflags, + NVME_CQ_FLAGS_IEN(qflags) !=3D 0); =20 if (unlikely(!cqid || !nvme_check_cqid(n, cqid))) { - trace_nvme_err_invalid_create_cq_cqid(cqid); + trace_pci_nvme_err_invalid_create_cq_cqid(cqid); return NVME_INVALID_CQID | NVME_DNR; } if (unlikely(!qsize || qsize > NVME_CAP_MQES(n->bar.cap))) { - trace_nvme_err_invalid_create_cq_size(qsize); + trace_pci_nvme_err_invalid_create_cq_size(qsize); return NVME_MAX_QSIZE_EXCEEDED | NVME_DNR; } if (unlikely(!prp1)) { - trace_nvme_err_invalid_create_cq_addr(prp1); + trace_pci_nvme_err_invalid_create_cq_addr(prp1); return NVME_INVALID_FIELD | NVME_DNR; } if (unlikely(vector > n->num_queues)) { - trace_nvme_err_invalid_create_cq_vector(vector); + trace_pci_nvme_err_invalid_create_cq_vector(vector); return NVME_INVALID_IRQ_VECTOR | NVME_DNR; } if (unlikely(!(NVME_CQ_FLAGS_PC(qflags)))) { - trace_nvme_err_invalid_create_cq_qflags(NVME_CQ_FLAGS_PC(qflags)); + trace_pci_nvme_err_invalid_create_cq_qflags(NVME_CQ_FLAGS_PC(qflag= s)); return NVME_INVALID_FIELD | NVME_DNR; } =20 @@ -654,7 +654,7 @@ static uint16_t nvme_identify_ctrl(NvmeCtrl *n, NvmeIde= ntify *c) uint64_t prp1 =3D le64_to_cpu(c->prp1); uint64_t prp2 =3D le64_to_cpu(c->prp2); =20 - trace_nvme_identify_ctrl(); + trace_pci_nvme_identify_ctrl(); =20 return nvme_dma_read_prp(n, (uint8_t *)&n->id_ctrl, sizeof(n->id_ctrl), prp1, prp2); @@ -667,10 +667,10 @@ static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeIde= ntify *c) uint64_t prp1 =3D le64_to_cpu(c->prp1); uint64_t prp2 =3D le64_to_cpu(c->prp2); =20 - trace_nvme_identify_ns(nsid); + trace_pci_nvme_identify_ns(nsid); =20 if (unlikely(nsid =3D=3D 0 || nsid > n->num_namespaces)) { - trace_nvme_err_invalid_ns(nsid, n->num_namespaces); + trace_pci_nvme_err_invalid_ns(nsid, n->num_namespaces); return NVME_INVALID_NSID | NVME_DNR; } =20 @@ -690,7 +690,7 @@ static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeI= dentify *c) uint16_t ret; int i, j =3D 0; =20 - trace_nvme_identify_nslist(min_nsid); + trace_pci_nvme_identify_nslist(min_nsid); =20 list =3D g_malloc0(data_len); for (i =3D 0; i < n->num_namespaces; i++) { @@ -719,14 +719,14 @@ static uint16_t nvme_identify(NvmeCtrl *n, NvmeCmd *c= md) case 0x02: return nvme_identify_nslist(n, c); default: - trace_nvme_err_invalid_identify_cns(le32_to_cpu(c->cns)); + trace_pci_nvme_err_invalid_identify_cns(le32_to_cpu(c->cns)); return NVME_INVALID_FIELD | NVME_DNR; } } =20 static inline void nvme_set_timestamp(NvmeCtrl *n, uint64_t ts) { - trace_nvme_setfeat_timestamp(ts); + trace_pci_nvme_setfeat_timestamp(ts); =20 n->host_timestamp =3D le64_to_cpu(ts); n->timestamp_set_qemu_clock_ms =3D qemu_clock_get_ms(QEMU_CLOCK_VIRTUA= L); @@ -759,7 +759,7 @@ static inline uint64_t nvme_get_timestamp(const NvmeCtr= l *n) /* If the host timestamp is non-zero, set the timestamp origin */ ts.origin =3D n->host_timestamp ? 0x01 : 0x00; =20 - trace_nvme_getfeat_timestamp(ts.all); + trace_pci_nvme_getfeat_timestamp(ts.all); =20 return cpu_to_le64(ts.all); } @@ -783,17 +783,17 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeCmd= *cmd, NvmeRequest *req) switch (dw10) { case NVME_VOLATILE_WRITE_CACHE: result =3D blk_enable_write_cache(n->conf.blk); - trace_nvme_getfeat_vwcache(result ? "enabled" : "disabled"); + trace_pci_nvme_getfeat_vwcache(result ? "enabled" : "disabled"); break; case NVME_NUMBER_OF_QUEUES: result =3D cpu_to_le32((n->num_queues - 2) | ((n->num_queues - 2) = << 16)); - trace_nvme_getfeat_numq(result); + trace_pci_nvme_getfeat_numq(result); break; case NVME_TIMESTAMP: return nvme_get_feature_timestamp(n, cmd); break; default: - trace_nvme_err_invalid_getfeat(dw10); + trace_pci_nvme_err_invalid_getfeat(dw10); return NVME_INVALID_FIELD | NVME_DNR; } =20 @@ -829,9 +829,9 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeCmd *= cmd, NvmeRequest *req) blk_set_enable_write_cache(n->conf.blk, dw11 & 1); break; case NVME_NUMBER_OF_QUEUES: - trace_nvme_setfeat_numq((dw11 & 0xFFFF) + 1, - ((dw11 >> 16) & 0xFFFF) + 1, - n->num_queues - 1, n->num_queues - 1); + trace_pci_nvme_setfeat_numq((dw11 & 0xFFFF) + 1, + ((dw11 >> 16) & 0xFFFF) + 1, + n->num_queues - 1, n->num_queues - 1); req->cqe.result =3D cpu_to_le32((n->num_queues - 2) | ((n->num_queues - 2) << 16)); break; @@ -841,7 +841,7 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeCmd *= cmd, NvmeRequest *req) break; =20 default: - trace_nvme_err_invalid_setfeat(dw10); + trace_pci_nvme_err_invalid_setfeat(dw10); return NVME_INVALID_FIELD | NVME_DNR; } return NVME_SUCCESS; @@ -865,7 +865,7 @@ static uint16_t nvme_admin_cmd(NvmeCtrl *n, NvmeCmd *cm= d, NvmeRequest *req) case NVME_ADM_CMD_GET_FEATURES: return nvme_get_feature(n, cmd, req); default: - trace_nvme_err_invalid_admin_opc(cmd->opcode); + trace_pci_nvme_err_invalid_admin_opc(cmd->opcode); return NVME_INVALID_OPCODE | NVME_DNR; } } @@ -928,77 +928,77 @@ static int nvme_start_ctrl(NvmeCtrl *n) uint32_t page_size =3D 1 << page_bits; =20 if (unlikely(n->cq[0])) { - trace_nvme_err_startfail_cq(); + trace_pci_nvme_err_startfail_cq(); return -1; } if (unlikely(n->sq[0])) { - trace_nvme_err_startfail_sq(); + trace_pci_nvme_err_startfail_sq(); return -1; } if (unlikely(!n->bar.asq)) { - trace_nvme_err_startfail_nbarasq(); + trace_pci_nvme_err_startfail_nbarasq(); return -1; } if (unlikely(!n->bar.acq)) { - trace_nvme_err_startfail_nbaracq(); + trace_pci_nvme_err_startfail_nbaracq(); return -1; } if (unlikely(n->bar.asq & (page_size - 1))) { - trace_nvme_err_startfail_asq_misaligned(n->bar.asq); + trace_pci_nvme_err_startfail_asq_misaligned(n->bar.asq); return -1; } if (unlikely(n->bar.acq & (page_size - 1))) { - trace_nvme_err_startfail_acq_misaligned(n->bar.acq); + trace_pci_nvme_err_startfail_acq_misaligned(n->bar.acq); return -1; } if (unlikely(NVME_CC_MPS(n->bar.cc) < NVME_CAP_MPSMIN(n->bar.cap))) { - trace_nvme_err_startfail_page_too_small( + trace_pci_nvme_err_startfail_page_too_small( NVME_CC_MPS(n->bar.cc), NVME_CAP_MPSMIN(n->bar.cap)); return -1; } if (unlikely(NVME_CC_MPS(n->bar.cc) > NVME_CAP_MPSMAX(n->bar.cap))) { - trace_nvme_err_startfail_page_too_large( + trace_pci_nvme_err_startfail_page_too_large( NVME_CC_MPS(n->bar.cc), NVME_CAP_MPSMAX(n->bar.cap)); return -1; } if (unlikely(NVME_CC_IOCQES(n->bar.cc) < NVME_CTRL_CQES_MIN(n->id_ctrl.cqes))) { - trace_nvme_err_startfail_cqent_too_small( + trace_pci_nvme_err_startfail_cqent_too_small( NVME_CC_IOCQES(n->bar.cc), NVME_CTRL_CQES_MIN(n->bar.cap)); return -1; } if (unlikely(NVME_CC_IOCQES(n->bar.cc) > NVME_CTRL_CQES_MAX(n->id_ctrl.cqes))) { - trace_nvme_err_startfail_cqent_too_large( + trace_pci_nvme_err_startfail_cqent_too_large( NVME_CC_IOCQES(n->bar.cc), NVME_CTRL_CQES_MAX(n->bar.cap)); return -1; } if (unlikely(NVME_CC_IOSQES(n->bar.cc) < NVME_CTRL_SQES_MIN(n->id_ctrl.sqes))) { - trace_nvme_err_startfail_sqent_too_small( + trace_pci_nvme_err_startfail_sqent_too_small( NVME_CC_IOSQES(n->bar.cc), NVME_CTRL_SQES_MIN(n->bar.cap)); return -1; } if (unlikely(NVME_CC_IOSQES(n->bar.cc) > NVME_CTRL_SQES_MAX(n->id_ctrl.sqes))) { - trace_nvme_err_startfail_sqent_too_large( + trace_pci_nvme_err_startfail_sqent_too_large( NVME_CC_IOSQES(n->bar.cc), NVME_CTRL_SQES_MAX(n->bar.cap)); return -1; } if (unlikely(!NVME_AQA_ASQS(n->bar.aqa))) { - trace_nvme_err_startfail_asqent_sz_zero(); + trace_pci_nvme_err_startfail_asqent_sz_zero(); return -1; } if (unlikely(!NVME_AQA_ACQS(n->bar.aqa))) { - trace_nvme_err_startfail_acqent_sz_zero(); + trace_pci_nvme_err_startfail_acqent_sz_zero(); return -1; } =20 @@ -1021,14 +1021,14 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offs= et, uint64_t data, unsigned size) { if (unlikely(offset & (sizeof(uint32_t) - 1))) { - NVME_GUEST_ERR(nvme_ub_mmiowr_misaligned32, + NVME_GUEST_ERR(pci_nvme_ub_mmiowr_misaligned32, "MMIO write not 32-bit aligned," " offset=3D0x%"PRIx64"", offset); /* should be ignored, fall through for now */ } =20 if (unlikely(size < sizeof(uint32_t))) { - NVME_GUEST_ERR(nvme_ub_mmiowr_toosmall, + NVME_GUEST_ERR(pci_nvme_ub_mmiowr_toosmall, "MMIO write smaller than 32-bits," " offset=3D0x%"PRIx64", size=3D%u", offset, size); @@ -1038,32 +1038,30 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offs= et, uint64_t data, switch (offset) { case 0xc: /* INTMS */ if (unlikely(msix_enabled(&(n->parent_obj)))) { - NVME_GUEST_ERR(nvme_ub_mmiowr_intmask_with_msix, + NVME_GUEST_ERR(pci_nvme_ub_mmiowr_intmask_with_msix, "undefined access to interrupt mask set" " when MSI-X is enabled"); /* should be ignored, fall through for now */ } n->bar.intms |=3D data & 0xffffffff; n->bar.intmc =3D n->bar.intms; - trace_nvme_mmio_intm_set(data & 0xffffffff, - n->bar.intmc); + trace_pci_nvme_mmio_intm_set(data & 0xffffffff, n->bar.intmc); nvme_irq_check(n); break; case 0x10: /* INTMC */ if (unlikely(msix_enabled(&(n->parent_obj)))) { - NVME_GUEST_ERR(nvme_ub_mmiowr_intmask_with_msix, + NVME_GUEST_ERR(pci_nvme_ub_mmiowr_intmask_with_msix, "undefined access to interrupt mask clr" " when MSI-X is enabled"); /* should be ignored, fall through for now */ } n->bar.intms &=3D ~(data & 0xffffffff); n->bar.intmc =3D n->bar.intms; - trace_nvme_mmio_intm_clr(data & 0xffffffff, - n->bar.intmc); + trace_pci_nvme_mmio_intm_clr(data & 0xffffffff, n->bar.intmc); nvme_irq_check(n); break; case 0x14: /* CC */ - trace_nvme_mmio_cfg(data & 0xffffffff); + trace_pci_nvme_mmio_cfg(data & 0xffffffff); /* Windows first sends data, then sends enable bit */ if (!NVME_CC_EN(data) && !NVME_CC_EN(n->bar.cc) && !NVME_CC_SHN(data) && !NVME_CC_SHN(n->bar.cc)) @@ -1074,42 +1072,42 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offs= et, uint64_t data, if (NVME_CC_EN(data) && !NVME_CC_EN(n->bar.cc)) { n->bar.cc =3D data; if (unlikely(nvme_start_ctrl(n))) { - trace_nvme_err_startfail(); + trace_pci_nvme_err_startfail(); n->bar.csts =3D NVME_CSTS_FAILED; } else { - trace_nvme_mmio_start_success(); + trace_pci_nvme_mmio_start_success(); n->bar.csts =3D NVME_CSTS_READY; } } else if (!NVME_CC_EN(data) && NVME_CC_EN(n->bar.cc)) { - trace_nvme_mmio_stopped(); + trace_pci_nvme_mmio_stopped(); nvme_clear_ctrl(n); n->bar.csts &=3D ~NVME_CSTS_READY; } if (NVME_CC_SHN(data) && !(NVME_CC_SHN(n->bar.cc))) { - trace_nvme_mmio_shutdown_set(); + trace_pci_nvme_mmio_shutdown_set(); nvme_clear_ctrl(n); n->bar.cc =3D data; n->bar.csts |=3D NVME_CSTS_SHST_COMPLETE; } else if (!NVME_CC_SHN(data) && NVME_CC_SHN(n->bar.cc)) { - trace_nvme_mmio_shutdown_cleared(); + trace_pci_nvme_mmio_shutdown_cleared(); n->bar.csts &=3D ~NVME_CSTS_SHST_COMPLETE; n->bar.cc =3D data; } break; case 0x1C: /* CSTS */ if (data & (1 << 4)) { - NVME_GUEST_ERR(nvme_ub_mmiowr_ssreset_w1c_unsupported, + NVME_GUEST_ERR(pci_nvme_ub_mmiowr_ssreset_w1c_unsupported, "attempted to W1C CSTS.NSSRO" " but CAP.NSSRS is zero (not supported)"); } else if (data !=3D 0) { - NVME_GUEST_ERR(nvme_ub_mmiowr_ro_csts, + NVME_GUEST_ERR(pci_nvme_ub_mmiowr_ro_csts, "attempted to set a read only bit" " of controller status"); } break; case 0x20: /* NSSR */ if (data =3D=3D 0x4E564D65) { - trace_nvme_ub_mmiowr_ssreset_unsupported(); + trace_pci_nvme_ub_mmiowr_ssreset_unsupported(); } else { /* The spec says that writes of other values have no effect */ return; @@ -1117,35 +1115,35 @@ static void nvme_write_bar(NvmeCtrl *n, hwaddr offs= et, uint64_t data, break; case 0x24: /* AQA */ n->bar.aqa =3D data & 0xffffffff; - trace_nvme_mmio_aqattr(data & 0xffffffff); + trace_pci_nvme_mmio_aqattr(data & 0xffffffff); break; case 0x28: /* ASQ */ n->bar.asq =3D data; - trace_nvme_mmio_asqaddr(data); + trace_pci_nvme_mmio_asqaddr(data); break; case 0x2c: /* ASQ hi */ n->bar.asq |=3D data << 32; - trace_nvme_mmio_asqaddr_hi(data, n->bar.asq); + trace_pci_nvme_mmio_asqaddr_hi(data, n->bar.asq); break; case 0x30: /* ACQ */ - trace_nvme_mmio_acqaddr(data); + trace_pci_nvme_mmio_acqaddr(data); n->bar.acq =3D data; break; case 0x34: /* ACQ hi */ n->bar.acq |=3D data << 32; - trace_nvme_mmio_acqaddr_hi(data, n->bar.acq); + trace_pci_nvme_mmio_acqaddr_hi(data, n->bar.acq); break; case 0x38: /* CMBLOC */ - NVME_GUEST_ERR(nvme_ub_mmiowr_cmbloc_reserved, + NVME_GUEST_ERR(pci_nvme_ub_mmiowr_cmbloc_reserved, "invalid write to reserved CMBLOC" " when CMBSZ is zero, ignored"); return; case 0x3C: /* CMBSZ */ - NVME_GUEST_ERR(nvme_ub_mmiowr_cmbsz_readonly, + NVME_GUEST_ERR(pci_nvme_ub_mmiowr_cmbsz_readonly, "invalid write to read only CMBSZ, ignored"); return; default: - NVME_GUEST_ERR(nvme_ub_mmiowr_invalid, + NVME_GUEST_ERR(pci_nvme_ub_mmiowr_invalid, "invalid MMIO write," " offset=3D0x%"PRIx64", data=3D%"PRIx64"", offset, data); @@ -1160,12 +1158,12 @@ static uint64_t nvme_mmio_read(void *opaque, hwaddr= addr, unsigned size) uint64_t val =3D 0; =20 if (unlikely(addr & (sizeof(uint32_t) - 1))) { - NVME_GUEST_ERR(nvme_ub_mmiord_misaligned32, + NVME_GUEST_ERR(pci_nvme_ub_mmiord_misaligned32, "MMIO read not 32-bit aligned," " offset=3D0x%"PRIx64"", addr); /* should RAZ, fall through for now */ } else if (unlikely(size < sizeof(uint32_t))) { - NVME_GUEST_ERR(nvme_ub_mmiord_toosmall, + NVME_GUEST_ERR(pci_nvme_ub_mmiord_toosmall, "MMIO read smaller than 32-bits," " offset=3D0x%"PRIx64"", addr); /* should RAZ, fall through for now */ @@ -1174,7 +1172,7 @@ static uint64_t nvme_mmio_read(void *opaque, hwaddr a= ddr, unsigned size) if (addr < sizeof(n->bar)) { memcpy(&val, ptr + addr, size); } else { - NVME_GUEST_ERR(nvme_ub_mmiord_invalid_ofs, + NVME_GUEST_ERR(pci_nvme_ub_mmiord_invalid_ofs, "MMIO read beyond last register," " offset=3D0x%"PRIx64", returning 0", addr); } @@ -1187,7 +1185,7 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr,= int val) uint32_t qid; =20 if (unlikely(addr & ((1 << 2) - 1))) { - NVME_GUEST_ERR(nvme_ub_db_wr_misaligned, + NVME_GUEST_ERR(pci_nvme_ub_db_wr_misaligned, "doorbell write not 32-bit aligned," " offset=3D0x%"PRIx64", ignoring", addr); return; @@ -1202,7 +1200,7 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr,= int val) =20 qid =3D (addr - (0x1000 + (1 << 2))) >> 3; if (unlikely(nvme_check_cqid(n, qid))) { - NVME_GUEST_ERR(nvme_ub_db_wr_invalid_cq, + NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_cq, "completion queue doorbell write" " for nonexistent queue," " sqid=3D%"PRIu32", ignoring", qid); @@ -1211,7 +1209,7 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr,= int val) =20 cq =3D n->cq[qid]; if (unlikely(new_head >=3D cq->size)) { - NVME_GUEST_ERR(nvme_ub_db_wr_invalid_cqhead, + NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_cqhead, "completion queue doorbell write value" " beyond queue size, sqid=3D%"PRIu32"," " new_head=3D%"PRIu16", ignoring", @@ -1240,7 +1238,7 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr,= int val) =20 qid =3D (addr - 0x1000) >> 3; if (unlikely(nvme_check_sqid(n, qid))) { - NVME_GUEST_ERR(nvme_ub_db_wr_invalid_sq, + NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_sq, "submission queue doorbell write" " for nonexistent queue," " sqid=3D%"PRIu32", ignoring", qid); @@ -1249,7 +1247,7 @@ static void nvme_process_db(NvmeCtrl *n, hwaddr addr,= int val) =20 sq =3D n->sq[qid]; if (unlikely(new_tail >=3D sq->size)) { - NVME_GUEST_ERR(nvme_ub_db_wr_invalid_sqtail, + NVME_GUEST_ERR(pci_nvme_ub_db_wr_invalid_sqtail, "submission queue doorbell write value" " beyond queue size, sqid=3D%"PRIu32"," " new_tail=3D%"PRIu16", ignoring", diff --git a/hw/block/trace-events b/hw/block/trace-events index bf6d11b58b85..1725abd92121 100644 --- a/hw/block/trace-events +++ b/hw/block/trace-events @@ -29,96 +29,96 @@ hd_geometry_guess(void *blk, uint32_t cyls, uint32_t he= ads, uint32_t secs, int t =20 # nvme.c # nvme traces for successful events -nvme_irq_msix(uint32_t vector) "raising MSI-X IRQ vector %u" -nvme_irq_pin(void) "pulsing IRQ pin" -nvme_irq_masked(void) "IRQ is masked" -nvme_dma_read(uint64_t prp1, uint64_t prp2) "DMA read, prp1=3D0x%"PRIx64" = prp2=3D0x%"PRIx64"" -nvme_rw(const char *verb, uint32_t blk_count, uint64_t byte_count, uint64_= t lba) "%s %"PRIu32" blocks (%"PRIu64" bytes) from LBA %"PRIu64"" -nvme_create_sq(uint64_t addr, uint16_t sqid, uint16_t cqid, uint16_t qsize= , uint16_t qflags) "create submission queue, addr=3D0x%"PRIx64", sqid=3D%"P= RIu16", cqid=3D%"PRIu16", qsize=3D%"PRIu16", qflags=3D%"PRIu16"" -nvme_create_cq(uint64_t addr, uint16_t cqid, uint16_t vector, uint16_t siz= e, uint16_t qflags, int ien) "create completion queue, addr=3D0x%"PRIx64", = cqid=3D%"PRIu16", vector=3D%"PRIu16", qsize=3D%"PRIu16", qflags=3D%"PRIu16"= , ien=3D%d" -nvme_del_sq(uint16_t qid) "deleting submission queue sqid=3D%"PRIu16"" -nvme_del_cq(uint16_t cqid) "deleted completion queue, cqid=3D%"PRIu16"" -nvme_identify_ctrl(void) "identify controller" -nvme_identify_ns(uint16_t ns) "identify namespace, nsid=3D%"PRIu16"" -nvme_identify_nslist(uint16_t ns) "identify namespace list, nsid=3D%"PRIu1= 6"" -nvme_getfeat_vwcache(const char* result) "get feature volatile write cache= , result=3D%s" -nvme_getfeat_numq(int result) "get feature number of queues, result=3D%d" -nvme_setfeat_numq(int reqcq, int reqsq, int gotcq, int gotsq) "requested c= q_count=3D%d sq_count=3D%d, responding with cq_count=3D%d sq_count=3D%d" -nvme_setfeat_timestamp(uint64_t ts) "set feature timestamp =3D 0x%"PRIx64"" -nvme_getfeat_timestamp(uint64_t ts) "get feature timestamp =3D 0x%"PRIx64"" -nvme_mmio_intm_set(uint64_t data, uint64_t new_mask) "wrote MMIO, interrup= t mask set, data=3D0x%"PRIx64", new_mask=3D0x%"PRIx64"" -nvme_mmio_intm_clr(uint64_t data, uint64_t new_mask) "wrote MMIO, interrup= t mask clr, data=3D0x%"PRIx64", new_mask=3D0x%"PRIx64"" -nvme_mmio_cfg(uint64_t data) "wrote MMIO, config controller config=3D0x%"P= RIx64"" -nvme_mmio_aqattr(uint64_t data) "wrote MMIO, admin queue attributes=3D0x%"= PRIx64"" -nvme_mmio_asqaddr(uint64_t data) "wrote MMIO, admin submission queue addre= ss=3D0x%"PRIx64"" -nvme_mmio_acqaddr(uint64_t data) "wrote MMIO, admin completion queue addre= ss=3D0x%"PRIx64"" -nvme_mmio_asqaddr_hi(uint64_t data, uint64_t new_addr) "wrote MMIO, admin = submission queue high half=3D0x%"PRIx64", new_address=3D0x%"PRIx64"" -nvme_mmio_acqaddr_hi(uint64_t data, uint64_t new_addr) "wrote MMIO, admin = completion queue high half=3D0x%"PRIx64", new_address=3D0x%"PRIx64"" -nvme_mmio_start_success(void) "setting controller enable bit succeeded" -nvme_mmio_stopped(void) "cleared controller enable bit" -nvme_mmio_shutdown_set(void) "shutdown bit set" -nvme_mmio_shutdown_cleared(void) "shutdown bit cleared" +pci_nvme_irq_msix(uint32_t vector) "raising MSI-X IRQ vector %u" +pci_nvme_irq_pin(void) "pulsing IRQ pin" +pci_nvme_irq_masked(void) "IRQ is masked" +pci_nvme_dma_read(uint64_t prp1, uint64_t prp2) "DMA read, prp1=3D0x%"PRIx= 64" prp2=3D0x%"PRIx64"" +pci_nvme_rw(const char *verb, uint32_t blk_count, uint64_t byte_count, uin= t64_t lba) "%s %"PRIu32" blocks (%"PRIu64" bytes) from LBA %"PRIu64"" +pci_nvme_create_sq(uint64_t addr, uint16_t sqid, uint16_t cqid, uint16_t q= size, uint16_t qflags) "create submission queue, addr=3D0x%"PRIx64", sqid= =3D%"PRIu16", cqid=3D%"PRIu16", qsize=3D%"PRIu16", qflags=3D%"PRIu16"" +pci_nvme_create_cq(uint64_t addr, uint16_t cqid, uint16_t vector, uint16_t= size, uint16_t qflags, int ien) "create completion queue, addr=3D0x%"PRIx6= 4", cqid=3D%"PRIu16", vector=3D%"PRIu16", qsize=3D%"PRIu16", qflags=3D%"PRI= u16", ien=3D%d" +pci_nvme_del_sq(uint16_t qid) "deleting submission queue sqid=3D%"PRIu16"" +pci_nvme_del_cq(uint16_t cqid) "deleted completion queue, cqid=3D%"PRIu16"" +pci_nvme_identify_ctrl(void) "identify controller" +pci_nvme_identify_ns(uint16_t ns) "identify namespace, nsid=3D%"PRIu16"" +pci_nvme_identify_nslist(uint16_t ns) "identify namespace list, nsid=3D%"P= RIu16"" +pci_nvme_getfeat_vwcache(const char* result) "get feature volatile write c= ache, result=3D%s" +pci_nvme_getfeat_numq(int result) "get feature number of queues, result=3D= %d" +pci_nvme_setfeat_numq(int reqcq, int reqsq, int gotcq, int gotsq) "request= ed cq_count=3D%d sq_count=3D%d, responding with cq_count=3D%d sq_count=3D%d" +pci_nvme_setfeat_timestamp(uint64_t ts) "set feature timestamp =3D 0x%"PRI= x64"" +pci_nvme_getfeat_timestamp(uint64_t ts) "get feature timestamp =3D 0x%"PRI= x64"" +pci_nvme_mmio_intm_set(uint64_t data, uint64_t new_mask) "wrote MMIO, inte= rrupt mask set, data=3D0x%"PRIx64", new_mask=3D0x%"PRIx64"" +pci_nvme_mmio_intm_clr(uint64_t data, uint64_t new_mask) "wrote MMIO, inte= rrupt mask clr, data=3D0x%"PRIx64", new_mask=3D0x%"PRIx64"" +pci_nvme_mmio_cfg(uint64_t data) "wrote MMIO, config controller config=3D0= x%"PRIx64"" +pci_nvme_mmio_aqattr(uint64_t data) "wrote MMIO, admin queue attributes=3D= 0x%"PRIx64"" +pci_nvme_mmio_asqaddr(uint64_t data) "wrote MMIO, admin submission queue a= ddress=3D0x%"PRIx64"" +pci_nvme_mmio_acqaddr(uint64_t data) "wrote MMIO, admin completion queue a= ddress=3D0x%"PRIx64"" +pci_nvme_mmio_asqaddr_hi(uint64_t data, uint64_t new_addr) "wrote MMIO, ad= min submission queue high half=3D0x%"PRIx64", new_address=3D0x%"PRIx64"" +pci_nvme_mmio_acqaddr_hi(uint64_t data, uint64_t new_addr) "wrote MMIO, ad= min completion queue high half=3D0x%"PRIx64", new_address=3D0x%"PRIx64"" +pci_nvme_mmio_start_success(void) "setting controller enable bit succeeded" +pci_nvme_mmio_stopped(void) "cleared controller enable bit" +pci_nvme_mmio_shutdown_set(void) "shutdown bit set" +pci_nvme_mmio_shutdown_cleared(void) "shutdown bit cleared" =20 # nvme traces for error conditions -nvme_err_invalid_dma(void) "PRP/SGL is too small for transfer size" -nvme_err_invalid_prplist_ent(uint64_t prplist) "PRP list entry is null or = not page aligned: 0x%"PRIx64"" -nvme_err_invalid_prp2_align(uint64_t prp2) "PRP2 is not page aligned: 0x%"= PRIx64"" -nvme_err_invalid_prp2_missing(void) "PRP2 is null and more data to be tran= sferred" -nvme_err_invalid_prp(void) "invalid PRP" -nvme_err_invalid_ns(uint32_t ns, uint32_t limit) "invalid namespace %u not= within 1-%u" -nvme_err_invalid_opc(uint8_t opc) "invalid opcode 0x%"PRIx8"" -nvme_err_invalid_admin_opc(uint8_t opc) "invalid admin opcode 0x%"PRIx8"" -nvme_err_invalid_lba_range(uint64_t start, uint64_t len, uint64_t limit) "= Invalid LBA start=3D%"PRIu64" len=3D%"PRIu64" limit=3D%"PRIu64"" -nvme_err_invalid_del_sq(uint16_t qid) "invalid submission queue deletion, = sid=3D%"PRIu16"" -nvme_err_invalid_create_sq_cqid(uint16_t cqid) "failed creating submission= queue, invalid cqid=3D%"PRIu16"" -nvme_err_invalid_create_sq_sqid(uint16_t sqid) "failed creating submission= queue, invalid sqid=3D%"PRIu16"" -nvme_err_invalid_create_sq_size(uint16_t qsize) "failed creating submissio= n queue, invalid qsize=3D%"PRIu16"" -nvme_err_invalid_create_sq_addr(uint64_t addr) "failed creating submission= queue, addr=3D0x%"PRIx64"" -nvme_err_invalid_create_sq_qflags(uint16_t qflags) "failed creating submis= sion queue, qflags=3D%"PRIu16"" -nvme_err_invalid_del_cq_cqid(uint16_t cqid) "failed deleting completion qu= eue, cqid=3D%"PRIu16"" -nvme_err_invalid_del_cq_notempty(uint16_t cqid) "failed deleting completio= n queue, it is not empty, cqid=3D%"PRIu16"" -nvme_err_invalid_create_cq_cqid(uint16_t cqid) "failed creating completion= queue, cqid=3D%"PRIu16"" -nvme_err_invalid_create_cq_size(uint16_t size) "failed creating completion= queue, size=3D%"PRIu16"" -nvme_err_invalid_create_cq_addr(uint64_t addr) "failed creating completion= queue, addr=3D0x%"PRIx64"" -nvme_err_invalid_create_cq_vector(uint16_t vector) "failed creating comple= tion queue, vector=3D%"PRIu16"" -nvme_err_invalid_create_cq_qflags(uint16_t qflags) "failed creating comple= tion queue, qflags=3D%"PRIu16"" -nvme_err_invalid_identify_cns(uint16_t cns) "identify, invalid cns=3D0x%"P= RIx16"" -nvme_err_invalid_getfeat(int dw10) "invalid get features, dw10=3D0x%"PRIx3= 2"" -nvme_err_invalid_setfeat(uint32_t dw10) "invalid set features, dw10=3D0x%"= PRIx32"" -nvme_err_startfail_cq(void) "nvme_start_ctrl failed because there are non-= admin completion queues" -nvme_err_startfail_sq(void) "nvme_start_ctrl failed because there are non-= admin submission queues" -nvme_err_startfail_nbarasq(void) "nvme_start_ctrl failed because the admin= submission queue address is null" -nvme_err_startfail_nbaracq(void) "nvme_start_ctrl failed because the admin= completion queue address is null" -nvme_err_startfail_asq_misaligned(uint64_t addr) "nvme_start_ctrl failed b= ecause the admin submission queue address is misaligned: 0x%"PRIx64"" -nvme_err_startfail_acq_misaligned(uint64_t addr) "nvme_start_ctrl failed b= ecause the admin completion queue address is misaligned: 0x%"PRIx64"" -nvme_err_startfail_page_too_small(uint8_t log2ps, uint8_t maxlog2ps) "nvme= _start_ctrl failed because the page size is too small: log2size=3D%u, min= =3D%u" -nvme_err_startfail_page_too_large(uint8_t log2ps, uint8_t maxlog2ps) "nvme= _start_ctrl failed because the page size is too large: log2size=3D%u, max= =3D%u" -nvme_err_startfail_cqent_too_small(uint8_t log2ps, uint8_t maxlog2ps) "nvm= e_start_ctrl failed because the completion queue entry size is too small: l= og2size=3D%u, min=3D%u" -nvme_err_startfail_cqent_too_large(uint8_t log2ps, uint8_t maxlog2ps) "nvm= e_start_ctrl failed because the completion queue entry size is too large: l= og2size=3D%u, max=3D%u" -nvme_err_startfail_sqent_too_small(uint8_t log2ps, uint8_t maxlog2ps) "nvm= e_start_ctrl failed because the submission queue entry size is too small: l= og2size=3D%u, min=3D%u" -nvme_err_startfail_sqent_too_large(uint8_t log2ps, uint8_t maxlog2ps) "nvm= e_start_ctrl failed because the submission queue entry size is too large: l= og2size=3D%u, max=3D%u" -nvme_err_startfail_asqent_sz_zero(void) "nvme_start_ctrl failed because th= e admin submission queue size is zero" -nvme_err_startfail_acqent_sz_zero(void) "nvme_start_ctrl failed because th= e admin completion queue size is zero" -nvme_err_startfail(void) "setting controller enable bit failed" +pci_nvme_err_invalid_dma(void) "PRP/SGL is too small for transfer size" +pci_nvme_err_invalid_prplist_ent(uint64_t prplist) "PRP list entry is null= or not page aligned: 0x%"PRIx64"" +pci_nvme_err_invalid_prp2_align(uint64_t prp2) "PRP2 is not page aligned: = 0x%"PRIx64"" +pci_nvme_err_invalid_prp2_missing(void) "PRP2 is null and more data to be = transferred" +pci_nvme_err_invalid_prp(void) "invalid PRP" +pci_nvme_err_invalid_ns(uint32_t ns, uint32_t limit) "invalid namespace %u= not within 1-%u" +pci_nvme_err_invalid_opc(uint8_t opc) "invalid opcode 0x%"PRIx8"" +pci_nvme_err_invalid_admin_opc(uint8_t opc) "invalid admin opcode 0x%"PRIx= 8"" +pci_nvme_err_invalid_lba_range(uint64_t start, uint64_t len, uint64_t limi= t) "Invalid LBA start=3D%"PRIu64" len=3D%"PRIu64" limit=3D%"PRIu64"" +pci_nvme_err_invalid_del_sq(uint16_t qid) "invalid submission queue deleti= on, sid=3D%"PRIu16"" +pci_nvme_err_invalid_create_sq_cqid(uint16_t cqid) "failed creating submis= sion queue, invalid cqid=3D%"PRIu16"" +pci_nvme_err_invalid_create_sq_sqid(uint16_t sqid) "failed creating submis= sion queue, invalid sqid=3D%"PRIu16"" +pci_nvme_err_invalid_create_sq_size(uint16_t qsize) "failed creating submi= ssion queue, invalid qsize=3D%"PRIu16"" +pci_nvme_err_invalid_create_sq_addr(uint64_t addr) "failed creating submis= sion queue, addr=3D0x%"PRIx64"" +pci_nvme_err_invalid_create_sq_qflags(uint16_t qflags) "failed creating su= bmission queue, qflags=3D%"PRIu16"" +pci_nvme_err_invalid_del_cq_cqid(uint16_t cqid) "failed deleting completio= n queue, cqid=3D%"PRIu16"" +pci_nvme_err_invalid_del_cq_notempty(uint16_t cqid) "failed deleting compl= etion queue, it is not empty, cqid=3D%"PRIu16"" +pci_nvme_err_invalid_create_cq_cqid(uint16_t cqid) "failed creating comple= tion queue, cqid=3D%"PRIu16"" +pci_nvme_err_invalid_create_cq_size(uint16_t size) "failed creating comple= tion queue, size=3D%"PRIu16"" +pci_nvme_err_invalid_create_cq_addr(uint64_t addr) "failed creating comple= tion queue, addr=3D0x%"PRIx64"" +pci_nvme_err_invalid_create_cq_vector(uint16_t vector) "failed creating co= mpletion queue, vector=3D%"PRIu16"" +pci_nvme_err_invalid_create_cq_qflags(uint16_t qflags) "failed creating co= mpletion queue, qflags=3D%"PRIu16"" +pci_nvme_err_invalid_identify_cns(uint16_t cns) "identify, invalid cns=3D0= x%"PRIx16"" +pci_nvme_err_invalid_getfeat(int dw10) "invalid get features, dw10=3D0x%"P= RIx32"" +pci_nvme_err_invalid_setfeat(uint32_t dw10) "invalid set features, dw10=3D= 0x%"PRIx32"" +pci_nvme_err_startfail_cq(void) "nvme_start_ctrl failed because there are = non-admin completion queues" +pci_nvme_err_startfail_sq(void) "nvme_start_ctrl failed because there are = non-admin submission queues" +pci_nvme_err_startfail_nbarasq(void) "nvme_start_ctrl failed because the a= dmin submission queue address is null" +pci_nvme_err_startfail_nbaracq(void) "nvme_start_ctrl failed because the a= dmin completion queue address is null" +pci_nvme_err_startfail_asq_misaligned(uint64_t addr) "nvme_start_ctrl fail= ed because the admin submission queue address is misaligned: 0x%"PRIx64"" +pci_nvme_err_startfail_acq_misaligned(uint64_t addr) "nvme_start_ctrl fail= ed because the admin completion queue address is misaligned: 0x%"PRIx64"" +pci_nvme_err_startfail_page_too_small(uint8_t log2ps, uint8_t maxlog2ps) "= nvme_start_ctrl failed because the page size is too small: log2size=3D%u, m= in=3D%u" +pci_nvme_err_startfail_page_too_large(uint8_t log2ps, uint8_t maxlog2ps) "= nvme_start_ctrl failed because the page size is too large: log2size=3D%u, m= ax=3D%u" +pci_nvme_err_startfail_cqent_too_small(uint8_t log2ps, uint8_t maxlog2ps) = "nvme_start_ctrl failed because the completion queue entry size is too smal= l: log2size=3D%u, min=3D%u" +pci_nvme_err_startfail_cqent_too_large(uint8_t log2ps, uint8_t maxlog2ps) = "nvme_start_ctrl failed because the completion queue entry size is too larg= e: log2size=3D%u, max=3D%u" +pci_nvme_err_startfail_sqent_too_small(uint8_t log2ps, uint8_t maxlog2ps) = "nvme_start_ctrl failed because the submission queue entry size is too smal= l: log2size=3D%u, min=3D%u" +pci_nvme_err_startfail_sqent_too_large(uint8_t log2ps, uint8_t maxlog2ps) = "nvme_start_ctrl failed because the submission queue entry size is too larg= e: log2size=3D%u, max=3D%u" +pci_nvme_err_startfail_asqent_sz_zero(void) "nvme_start_ctrl failed becaus= e the admin submission queue size is zero" +pci_nvme_err_startfail_acqent_sz_zero(void) "nvme_start_ctrl failed becaus= e the admin completion queue size is zero" +pci_nvme_err_startfail(void) "setting controller enable bit failed" =20 # Traces for undefined behavior -nvme_ub_mmiowr_misaligned32(uint64_t offset) "MMIO write not 32-bit aligne= d, offset=3D0x%"PRIx64"" -nvme_ub_mmiowr_toosmall(uint64_t offset, unsigned size) "MMIO write smalle= r than 32 bits, offset=3D0x%"PRIx64", size=3D%u" -nvme_ub_mmiowr_intmask_with_msix(void) "undefined access to interrupt mask= set when MSI-X is enabled" -nvme_ub_mmiowr_ro_csts(void) "attempted to set a read only bit of controll= er status" -nvme_ub_mmiowr_ssreset_w1c_unsupported(void) "attempted to W1C CSTS.NSSRO = but CAP.NSSRS is zero (not supported)" -nvme_ub_mmiowr_ssreset_unsupported(void) "attempted NVM subsystem reset bu= t CAP.NSSRS is zero (not supported)" -nvme_ub_mmiowr_cmbloc_reserved(void) "invalid write to reserved CMBLOC whe= n CMBSZ is zero, ignored" -nvme_ub_mmiowr_cmbsz_readonly(void) "invalid write to read only CMBSZ, ign= ored" -nvme_ub_mmiowr_invalid(uint64_t offset, uint64_t data) "invalid MMIO write= , offset=3D0x%"PRIx64", data=3D0x%"PRIx64"" -nvme_ub_mmiord_misaligned32(uint64_t offset) "MMIO read not 32-bit aligned= , offset=3D0x%"PRIx64"" -nvme_ub_mmiord_toosmall(uint64_t offset) "MMIO read smaller than 32-bits, = offset=3D0x%"PRIx64"" -nvme_ub_mmiord_invalid_ofs(uint64_t offset) "MMIO read beyond last registe= r, offset=3D0x%"PRIx64", returning 0" -nvme_ub_db_wr_misaligned(uint64_t offset) "doorbell write not 32-bit align= ed, offset=3D0x%"PRIx64", ignoring" -nvme_ub_db_wr_invalid_cq(uint32_t qid) "completion queue doorbell write fo= r nonexistent queue, cqid=3D%"PRIu32", ignoring" -nvme_ub_db_wr_invalid_cqhead(uint32_t qid, uint16_t new_head) "completion = queue doorbell write value beyond queue size, cqid=3D%"PRIu32", new_head=3D= %"PRIu16", ignoring" -nvme_ub_db_wr_invalid_sq(uint32_t qid) "submission queue doorbell write fo= r nonexistent queue, sqid=3D%"PRIu32", ignoring" -nvme_ub_db_wr_invalid_sqtail(uint32_t qid, uint16_t new_tail) "submission = queue doorbell write value beyond queue size, sqid=3D%"PRIu32", new_head=3D= %"PRIu16", ignoring" +pci_nvme_ub_mmiowr_misaligned32(uint64_t offset) "MMIO write not 32-bit al= igned, offset=3D0x%"PRIx64"" +pci_nvme_ub_mmiowr_toosmall(uint64_t offset, unsigned size) "MMIO write sm= aller than 32 bits, offset=3D0x%"PRIx64", size=3D%u" +pci_nvme_ub_mmiowr_intmask_with_msix(void) "undefined access to interrupt = mask set when MSI-X is enabled" +pci_nvme_ub_mmiowr_ro_csts(void) "attempted to set a read only bit of cont= roller status" +pci_nvme_ub_mmiowr_ssreset_w1c_unsupported(void) "attempted to W1C CSTS.NS= SRO but CAP.NSSRS is zero (not supported)" +pci_nvme_ub_mmiowr_ssreset_unsupported(void) "attempted NVM subsystem rese= t but CAP.NSSRS is zero (not supported)" +pci_nvme_ub_mmiowr_cmbloc_reserved(void) "invalid write to reserved CMBLOC= when CMBSZ is zero, ignored" +pci_nvme_ub_mmiowr_cmbsz_readonly(void) "invalid write to read only CMBSZ,= ignored" +pci_nvme_ub_mmiowr_invalid(uint64_t offset, uint64_t data) "invalid MMIO w= rite, offset=3D0x%"PRIx64", data=3D0x%"PRIx64"" +pci_nvme_ub_mmiord_misaligned32(uint64_t offset) "MMIO read not 32-bit ali= gned, offset=3D0x%"PRIx64"" +pci_nvme_ub_mmiord_toosmall(uint64_t offset) "MMIO read smaller than 32-bi= ts, offset=3D0x%"PRIx64"" +pci_nvme_ub_mmiord_invalid_ofs(uint64_t offset) "MMIO read beyond last reg= ister, offset=3D0x%"PRIx64", returning 0" +pci_nvme_ub_db_wr_misaligned(uint64_t offset) "doorbell write not 32-bit a= ligned, offset=3D0x%"PRIx64", ignoring" +pci_nvme_ub_db_wr_invalid_cq(uint32_t qid) "completion queue doorbell writ= e for nonexistent queue, cqid=3D%"PRIu32", ignoring" +pci_nvme_ub_db_wr_invalid_cqhead(uint32_t qid, uint16_t new_head) "complet= ion queue doorbell write value beyond queue size, cqid=3D%"PRIu32", new_hea= d=3D%"PRIu16", ignoring" +pci_nvme_ub_db_wr_invalid_sq(uint32_t qid) "submission queue doorbell writ= e for nonexistent queue, sqid=3D%"PRIu32", ignoring" +pci_nvme_ub_db_wr_invalid_sqtail(uint32_t qid, uint16_t new_tail) "submiss= ion queue doorbell write value beyond queue size, sqid=3D%"PRIu32", new_hea= d=3D%"PRIu16", ignoring" =20 # xen-block.c xen_block_realize(const char *type, uint32_t disk, uint32_t partition) "%s= d%up%u" --=20 2.26.0 From nobody Thu May 16 14:23:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) 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smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1586956032475347.3182632420902; Wed, 15 Apr 2020 06:07:12 -0700 (PDT) Received: from localhost ([::1]:49684 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jOhl1-0004F6-5i for importer@patchew.org; Wed, 15 Apr 2020 09:07:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33720) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jOhgV-0007Ek-69 for qemu-devel@nongnu.org; Wed, 15 Apr 2020 09:02:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jOhgU-0004Mb-34 for qemu-devel@nongnu.org; Wed, 15 Apr 2020 09:02:31 -0400 Received: from charlie.dont.surf ([128.199.63.193]:48538) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jOhgN-00045e-Dh; Wed, 15 Apr 2020 09:02:23 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id 0219ABFA0B; Wed, 15 Apr 2020 13:02:20 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v2 03/16] nvme: remove superfluous breaks Date: Wed, 15 Apr 2020 15:01:46 +0200 Message-Id: <20200415130159.611361-4-its@irrelevant.dk> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200415130159.611361-1-its@irrelevant.dk> References: <20200415130159.611361-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 128.199.63.193 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen These break statements was left over when commit 3036a626e9ef ("nvme: add Get/Set Feature Timestamp support") was merged. Signed-off-by: Klaus Jensen Acked-by: Keith Busch Reviewed-by: Maxim Levitsky Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by. Reviewed-by's ;) Reviewed-by: Keith Busch --- hw/block/nvme.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 931ddeb26ba0..a947050209a1 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -791,7 +791,6 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeCmd *= cmd, NvmeRequest *req) break; case NVME_TIMESTAMP: return nvme_get_feature_timestamp(n, cmd); - break; default: trace_pci_nvme_err_invalid_getfeat(dw10); return NVME_INVALID_FIELD | NVME_DNR; @@ -835,11 +834,8 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeCmd = *cmd, NvmeRequest *req) req->cqe.result =3D cpu_to_le32((n->num_queues - 2) | ((n->num_queues - 2) << 16)); break; - case NVME_TIMESTAMP: return nvme_set_feature_timestamp(n, cmd); - break; - default: trace_pci_nvme_err_invalid_setfeat(dw10); return NVME_INVALID_FIELD | NVME_DNR; --=20 2.26.0 From nobody Thu May 16 14:23:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1586956031; cv=none; d=zohomail.com; s=zohoarc; b=lBNSGW3iyL1S/DIfZNt3efPMj5SMLKFiiAEEeRGzTNz8J4R2v6mZVfiT8SizOkwDLXxnIhGrCZqgGupIDqUGyLOefMx2fSo/0pelTic+Rmi/xxhaVp0GWQac0SlCFF85uYlL3270n3dCgk7ny7rAmVCUwOL9ptbiAMC46aOXefs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1586956031; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Trk3ZR1DSEcaUx6x7kBguDKndRyZlBSEzTTeouWQ32s=; b=Grf/TKqOcYpFmZQVV7Qd4VlKAf6MCSLoqOO3jSxpv8wng3QnsVMaTVTyLZsovexZC+KjwZ3hInuyf30tZgFd79HbIOtFbAwP+dwifz8fxHpRKlGBMZ2LiYCe2txvlUfESm6uPKyp0WmLWy6EfYgLd60EuS7kfreUErsU1+jGIYQ= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1586956031231304.5111692970469; Wed, 15 Apr 2020 06:07:11 -0700 (PDT) Received: from localhost ([::1]:49682 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jOhkz-00048Z-Rf for importer@patchew.org; Wed, 15 Apr 2020 09:07:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33680) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jOhgT-0007AN-Ah for qemu-devel@nongnu.org; Wed, 15 Apr 2020 09:02:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jOhgR-0004HT-G2 for qemu-devel@nongnu.org; Wed, 15 Apr 2020 09:02:29 -0400 Received: from charlie.dont.surf ([128.199.63.193]:48556) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jOhgM-00045w-Rw; Wed, 15 Apr 2020 09:02:23 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id 65E51BFB38; Wed, 15 Apr 2020 13:02:21 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v2 04/16] nvme: move device parameters to separate struct Date: Wed, 15 Apr 2020 15:01:47 +0200 Message-Id: <20200415130159.611361-5-its@irrelevant.dk> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200415130159.611361-1-its@irrelevant.dk> References: <20200415130159.611361-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 128.199.63.193 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen Move device configuration parameters to separate struct to make it explicit what is configurable and what is set internally. Signed-off-by: Klaus Jensen Signed-off-by: Klaus Jensen Acked-by: Keith Busch Reviewed-by: Maxim Levitsky Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by. Reviewed-by's ;) Reviewed-by: Keith Busch --- hw/block/nvme.c | 45 +++++++++++++++++++++++---------------------- hw/block/nvme.h | 16 +++++++++++++--- 2 files changed, 36 insertions(+), 25 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index a947050209a1..a2b15a0ebd87 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -67,12 +67,12 @@ static void nvme_addr_read(NvmeCtrl *n, hwaddr addr, vo= id *buf, int size) =20 static int nvme_check_sqid(NvmeCtrl *n, uint16_t sqid) { - return sqid < n->num_queues && n->sq[sqid] !=3D NULL ? 0 : -1; + return sqid < n->params.num_queues && n->sq[sqid] !=3D NULL ? 0 : -1; } =20 static int nvme_check_cqid(NvmeCtrl *n, uint16_t cqid) { - return cqid < n->num_queues && n->cq[cqid] !=3D NULL ? 0 : -1; + return cqid < n->params.num_queues && n->cq[cqid] !=3D NULL ? 0 : -1; } =20 static void nvme_inc_cq_tail(NvmeCQueue *cq) @@ -634,7 +634,7 @@ static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeCmd *cm= d) trace_pci_nvme_err_invalid_create_cq_addr(prp1); return NVME_INVALID_FIELD | NVME_DNR; } - if (unlikely(vector > n->num_queues)) { + if (unlikely(vector > n->params.num_queues)) { trace_pci_nvme_err_invalid_create_cq_vector(vector); return NVME_INVALID_IRQ_VECTOR | NVME_DNR; } @@ -786,7 +786,8 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeCmd *= cmd, NvmeRequest *req) trace_pci_nvme_getfeat_vwcache(result ? "enabled" : "disabled"); break; case NVME_NUMBER_OF_QUEUES: - result =3D cpu_to_le32((n->num_queues - 2) | ((n->num_queues - 2) = << 16)); + result =3D cpu_to_le32((n->params.num_queues - 2) | + ((n->params.num_queues - 2) << 16)); trace_pci_nvme_getfeat_numq(result); break; case NVME_TIMESTAMP: @@ -830,9 +831,10 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeCmd = *cmd, NvmeRequest *req) case NVME_NUMBER_OF_QUEUES: trace_pci_nvme_setfeat_numq((dw11 & 0xFFFF) + 1, ((dw11 >> 16) & 0xFFFF) + 1, - n->num_queues - 1, n->num_queues - 1); - req->cqe.result =3D - cpu_to_le32((n->num_queues - 2) | ((n->num_queues - 2) << 16)); + n->params.num_queues - 1, + n->params.num_queues - 1); + req->cqe.result =3D cpu_to_le32((n->params.num_queues - 2) | + ((n->params.num_queues - 2) << 16)); break; case NVME_TIMESTAMP: return nvme_set_feature_timestamp(n, cmd); @@ -903,12 +905,12 @@ static void nvme_clear_ctrl(NvmeCtrl *n) =20 blk_drain(n->conf.blk); =20 - for (i =3D 0; i < n->num_queues; i++) { + for (i =3D 0; i < n->params.num_queues; i++) { if (n->sq[i] !=3D NULL) { nvme_free_sq(n->sq[i], n); } } - for (i =3D 0; i < n->num_queues; i++) { + for (i =3D 0; i < n->params.num_queues; i++) { if (n->cq[i] !=3D NULL) { nvme_free_cq(n->cq[i], n); } @@ -1309,7 +1311,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error **= errp) int64_t bs_size; uint8_t *pci_conf; =20 - if (!n->num_queues) { + if (!n->params.num_queues) { error_setg(errp, "num_queues can't be zero"); return; } @@ -1325,7 +1327,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error **= errp) return; } =20 - if (!n->serial) { + if (!n->params.serial) { error_setg(errp, "serial property not set"); return; } @@ -1344,25 +1346,26 @@ static void nvme_realize(PCIDevice *pci_dev, Error = **errp) n->num_namespaces =3D 1; =20 /* num_queues is really number of pairs, so each has two doorbells */ - n->reg_size =3D pow2ceil(NVME_REG_SIZE + 2 * n->num_queues * NVME_DB_S= IZE); + n->reg_size =3D pow2ceil(NVME_REG_SIZE + + 2 * n->params.num_queues * NVME_DB_SIZE); n->ns_size =3D bs_size / (uint64_t)n->num_namespaces; =20 n->namespaces =3D g_new0(NvmeNamespace, n->num_namespaces); - n->sq =3D g_new0(NvmeSQueue *, n->num_queues); - n->cq =3D g_new0(NvmeCQueue *, n->num_queues); + n->sq =3D g_new0(NvmeSQueue *, n->params.num_queues); + n->cq =3D g_new0(NvmeCQueue *, n->params.num_queues); =20 memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme", n->reg_size); pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, &n->iomem); - msix_init_exclusive_bar(pci_dev, n->num_queues, 4, NULL); + msix_init_exclusive_bar(pci_dev, n->params.num_queues, 4, NULL); =20 id->vid =3D cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID)); id->ssvid =3D cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR= _ID)); strpadcpy((char *)id->mn, sizeof(id->mn), "QEMU NVMe Ctrl", ' '); strpadcpy((char *)id->fr, sizeof(id->fr), "1.0", ' '); - strpadcpy((char *)id->sn, sizeof(id->sn), n->serial, ' '); + strpadcpy((char *)id->sn, sizeof(id->sn), n->params.serial, ' '); id->rab =3D 6; id->ieee[0] =3D 0x00; id->ieee[1] =3D 0x02; @@ -1391,7 +1394,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error **= errp) n->bar.vs =3D 0x00010200; n->bar.intmc =3D n->bar.intms =3D 0; =20 - if (n->cmb_size_mb) { + if (n->params.cmb_size_mb) { =20 NVME_CMBLOC_SET_BIR(n->bar.cmbloc, 2); NVME_CMBLOC_SET_OFST(n->bar.cmbloc, 0); @@ -1402,7 +1405,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error **= errp) NVME_CMBSZ_SET_RDS(n->bar.cmbsz, 1); NVME_CMBSZ_SET_WDS(n->bar.cmbsz, 1); NVME_CMBSZ_SET_SZU(n->bar.cmbsz, 2); /* MBs */ - NVME_CMBSZ_SET_SZ(n->bar.cmbsz, n->cmb_size_mb); + NVME_CMBSZ_SET_SZ(n->bar.cmbsz, n->params.cmb_size_mb); =20 n->cmbloc =3D n->bar.cmbloc; n->cmbsz =3D n->bar.cmbsz; @@ -1441,7 +1444,7 @@ static void nvme_exit(PCIDevice *pci_dev) g_free(n->cq); g_free(n->sq); =20 - if (n->cmb_size_mb) { + if (n->params.cmb_size_mb) { g_free(n->cmbuf); } msix_uninit_exclusive_bar(pci_dev); @@ -1449,9 +1452,7 @@ static void nvme_exit(PCIDevice *pci_dev) =20 static Property nvme_props[] =3D { DEFINE_BLOCK_PROPERTIES(NvmeCtrl, conf), - DEFINE_PROP_STRING("serial", NvmeCtrl, serial), - DEFINE_PROP_UINT32("cmb_size_mb", NvmeCtrl, cmb_size_mb, 0), - DEFINE_PROP_UINT32("num_queues", NvmeCtrl, num_queues, 64), + DEFINE_NVME_PROPERTIES(NvmeCtrl, params), DEFINE_PROP_END_OF_LIST(), }; =20 diff --git a/hw/block/nvme.h b/hw/block/nvme.h index 557194ee1954..9957c4a200e2 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -1,7 +1,19 @@ #ifndef HW_NVME_H #define HW_NVME_H + #include "block/nvme.h" =20 +#define DEFINE_NVME_PROPERTIES(_state, _props) \ + DEFINE_PROP_STRING("serial", _state, _props.serial), \ + DEFINE_PROP_UINT32("cmb_size_mb", _state, _props.cmb_size_mb, 0), \ + DEFINE_PROP_UINT32("num_queues", _state, _props.num_queues, 64) + +typedef struct NvmeParams { + char *serial; + uint32_t num_queues; + uint32_t cmb_size_mb; +} NvmeParams; + typedef struct NvmeAsyncEvent { QSIMPLEQ_ENTRY(NvmeAsyncEvent) entry; NvmeAerResult result; @@ -63,6 +75,7 @@ typedef struct NvmeCtrl { MemoryRegion ctrl_mem; NvmeBar bar; BlockConf conf; + NvmeParams params; =20 uint32_t page_size; uint16_t page_bits; @@ -71,10 +84,8 @@ typedef struct NvmeCtrl { uint16_t sqe_size; uint32_t reg_size; uint32_t num_namespaces; - uint32_t num_queues; uint32_t max_q_ents; uint64_t ns_size; - uint32_t cmb_size_mb; uint32_t cmbsz; uint32_t cmbloc; uint8_t *cmbuf; @@ -82,7 +93,6 @@ typedef struct NvmeCtrl { uint64_t host_timestamp; /* Timestamp sent by the h= ost */ uint64_t timestamp_set_qemu_clock_ms; /* QEMU clock time */ =20 - char *serial; NvmeNamespace *namespaces; NvmeSQueue **sq; NvmeCQueue **cq; --=20 2.26.0 From nobody Thu May 16 14:23:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1586956182; cv=none; d=zohomail.com; s=zohoarc; b=X6GCSIzCxADIuOsZyEAdpTlm4d9MBtpcS3aRNG8WGnzgvcmaZu4J1TXpaUciwNIJBgDJkrKQFgM87xsY705KpGanui7fo1RbWWkZ8V8Xr+i32XdHjYvw/Xua7HjWGZXxEtYm0zoxZSr+k1s1rF6ZkDVOqiqOQBlZFh0fB+GEnl8= ARC-Message-Signature: i=1; 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Wed, 15 Apr 2020 09:09:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33724) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jOhgV-0007F7-BD for qemu-devel@nongnu.org; Wed, 15 Apr 2020 09:02:32 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jOhgU-0004Mi-95 for qemu-devel@nongnu.org; Wed, 15 Apr 2020 09:02:31 -0400 Received: from charlie.dont.surf ([128.199.63.193]:48560) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jOhgN-00045z-0c; Wed, 15 Apr 2020 09:02:23 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id CE692BFD25; Wed, 15 Apr 2020 13:02:21 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v2 05/16] nvme: use constants in identify Date: Wed, 15 Apr 2020 15:01:48 +0200 Message-Id: <20200415130159.611361-6-its@irrelevant.dk> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200415130159.611361-1-its@irrelevant.dk> References: <20200415130159.611361-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 128.199.63.193 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen Signed-off-by: Klaus Jensen Reviewed-by: Maxim Levitsky Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by. Reviewed-by's ;) Reviewed-by: Keith Busch --- hw/block/nvme.c | 8 ++++---- include/block/nvme.h | 8 ++++++++ 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index a2b15a0ebd87..563cccae6795 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -682,7 +682,7 @@ static uint16_t nvme_identify_ns(NvmeCtrl *n, NvmeIdent= ify *c) =20 static uint16_t nvme_identify_nslist(NvmeCtrl *n, NvmeIdentify *c) { - static const int data_len =3D 4 * KiB; + static const int data_len =3D NVME_IDENTIFY_DATA_SIZE; uint32_t min_nsid =3D le32_to_cpu(c->nsid); uint64_t prp1 =3D le64_to_cpu(c->prp1); uint64_t prp2 =3D le64_to_cpu(c->prp2); @@ -712,11 +712,11 @@ static uint16_t nvme_identify(NvmeCtrl *n, NvmeCmd *c= md) NvmeIdentify *c =3D (NvmeIdentify *)cmd; =20 switch (le32_to_cpu(c->cns)) { - case 0x00: + case NVME_ID_CNS_NS: return nvme_identify_ns(n, c); - case 0x01: + case NVME_ID_CNS_CTRL: return nvme_identify_ctrl(n, c); - case 0x02: + case NVME_ID_CNS_NS_ACTIVE_LIST: return nvme_identify_nslist(n, c); default: trace_pci_nvme_err_invalid_identify_cns(le32_to_cpu(c->cns)); diff --git a/include/block/nvme.h b/include/block/nvme.h index 8fb941c6537c..c2fd01cf2f1d 100644 --- a/include/block/nvme.h +++ b/include/block/nvme.h @@ -533,6 +533,14 @@ typedef struct NvmePSD { uint8_t resv[16]; } NvmePSD; =20 +#define NVME_IDENTIFY_DATA_SIZE 4096 + +enum { + NVME_ID_CNS_NS =3D 0x0, + NVME_ID_CNS_CTRL =3D 0x1, + NVME_ID_CNS_NS_ACTIVE_LIST =3D 0x2, +}; + typedef struct NvmeIdCtrl { uint16_t vid; uint16_t ssvid; --=20 2.26.0 From nobody Thu May 16 14:23:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; 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Wed, 15 Apr 2020 06:04:47 -0700 (PDT) Received: from localhost ([::1]:49628 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jOhig-0000td-NJ for importer@patchew.org; Wed, 15 Apr 2020 09:04:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33634) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jOhgR-00076q-Hf for qemu-devel@nongnu.org; Wed, 15 Apr 2020 09:02:29 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jOhgQ-0004Fd-Au for qemu-devel@nongnu.org; Wed, 15 Apr 2020 09:02:27 -0400 Received: from charlie.dont.surf ([128.199.63.193]:48568) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jOhgN-00046E-FC; Wed, 15 Apr 2020 09:02:23 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id 3C1C8BFD2C; Wed, 15 Apr 2020 13:02:22 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v2 06/16] nvme: refactor nvme_addr_read Date: Wed, 15 Apr 2020 15:01:49 +0200 Message-Id: <20200415130159.611361-7-its@irrelevant.dk> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200415130159.611361-1-its@irrelevant.dk> References: <20200415130159.611361-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 128.199.63.193 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen Pull the controller memory buffer check to its own function. The check will be used on its own in later patches. Signed-off-by: Klaus Jensen Acked-by: Keith Busch Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by. Reviewed-by's ;) Reviewed-by: Keith Busch Reviewed-by: Maxim Levitsky --- hw/block/nvme.c | 16 ++++++++++++---- 1 file changed, 12 insertions(+), 4 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 563cccae6795..d026985f62d0 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -55,14 +55,22 @@ =20 static void nvme_process_sq(void *opaque); =20 +static bool nvme_addr_is_cmb(NvmeCtrl *n, hwaddr addr) +{ + hwaddr low =3D n->ctrl_mem.addr; + hwaddr hi =3D n->ctrl_mem.addr + int128_get64(n->ctrl_mem.size); + + return addr >=3D low && addr < hi; +} + static void nvme_addr_read(NvmeCtrl *n, hwaddr addr, void *buf, int size) { - if (n->cmbsz && addr >=3D n->ctrl_mem.addr && - addr < (n->ctrl_mem.addr + int128_get64(n->ctrl_mem.size))= ) { + if (n->cmbsz && nvme_addr_is_cmb(n, addr)) { memcpy(buf, (void *)&n->cmbuf[addr - n->ctrl_mem.addr], size); - } else { - pci_dma_read(&n->parent_obj, addr, buf, size); + return; } + + pci_dma_read(&n->parent_obj, addr, buf, size); } =20 static int nvme_check_sqid(NvmeCtrl *n, uint16_t sqid) --=20 2.26.0 From nobody Thu May 16 14:23:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1586956118; cv=none; d=zohomail.com; s=zohoarc; b=k/MOcpRdKXg+38lWhe2ObptOoqfSk18qEwbMureGPRU+/kLVeLYLq5Q2WTXKD4f2s7prHhSLECbC1qGxJcgbRHIRH6DGTRiYhppHpv3N91JoT8VIQA4UYgQHkceCPB9zpVNjpTz3WC2+xBDChGcnED82YcVwKwj3MFbJ+lanmiU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1586956118; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=FAVWtLgbSV7wqm7bLMCYl0FKW2NlRaK7PeRMB0Oiga8=; b=eNzdzbMueO6axw+oOw8ZqtGuhmhAOizptPX0LU4qkBIHrhekKtyShFyaC2G61S7puE+BJ7/XixNmq9zX0baxYBzutxorDvysCPSTnx27YvdEwhN1DsmoNEwvdiAjnIlp1yuUtW+0iT2Vl85X6GViyTQAimhlkWhwetIvR5AYdWQ= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 158695611886231.629791512145175; Wed, 15 Apr 2020 06:08:38 -0700 (PDT) Received: from localhost ([::1]:49728 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jOhmP-0007zw-HH for importer@patchew.org; Wed, 15 Apr 2020 09:08:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33728) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jOhgV-0007Fo-JL for qemu-devel@nongnu.org; Wed, 15 Apr 2020 09:02:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jOhgT-0004MS-TJ for qemu-devel@nongnu.org; Wed, 15 Apr 2020 09:02:31 -0400 Received: from charlie.dont.surf ([128.199.63.193]:48574) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jOhgN-000476-Rm; Wed, 15 Apr 2020 09:02:24 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id 9D0AABFD2F; Wed, 15 Apr 2020 13:02:22 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v2 07/16] nvme: add max_ioqpairs device parameter Date: Wed, 15 Apr 2020 15:01:50 +0200 Message-Id: <20200415130159.611361-8-its@irrelevant.dk> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200415130159.611361-1-its@irrelevant.dk> References: <20200415130159.611361-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 128.199.63.193 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen The num_queues device paramater has a slightly confusing meaning because it accounts for the admin queue pair which is not really optional. Secondly, it is really a maximum value of queues allowed. Add a new max_ioqpairs parameter that only accounts for I/O queue pairs, but keep num_queues for compatibility. Signed-off-by: Klaus Jensen Reviewed-by: Maxim Levitsky Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by. Reviewed-by's ;) Reviewed-by: Keith Busch --- hw/block/nvme.c | 48 +++++++++++++++++++++++++++++------------------- hw/block/nvme.h | 6 ++++-- 2 files changed, 33 insertions(+), 21 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index d026985f62d0..8092c1b46eb1 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -19,7 +19,7 @@ * -drive file=3D,if=3Dnone,id=3D * -device nvme,drive=3D,serial=3D,id=3D, \ * cmb_size_mb=3D, \ - * num_queues=3D + * max_ioqpairs=3D * * Note cmb_size_mb denotes size of CMB in MB. CMB is assumed to be at * offset 0 in BAR2 and supports only WDS, RDS and SQS for now. @@ -27,6 +27,7 @@ =20 #include "qemu/osdep.h" #include "qemu/units.h" +#include "qemu/error-report.h" #include "hw/block/block.h" #include "hw/pci/msix.h" #include "hw/pci/pci.h" @@ -75,12 +76,12 @@ static void nvme_addr_read(NvmeCtrl *n, hwaddr addr, vo= id *buf, int size) =20 static int nvme_check_sqid(NvmeCtrl *n, uint16_t sqid) { - return sqid < n->params.num_queues && n->sq[sqid] !=3D NULL ? 0 : -1; + return sqid < n->params.max_ioqpairs + 1 && n->sq[sqid] !=3D NULL ? 0 = : -1; } =20 static int nvme_check_cqid(NvmeCtrl *n, uint16_t cqid) { - return cqid < n->params.num_queues && n->cq[cqid] !=3D NULL ? 0 : -1; + return cqid < n->params.max_ioqpairs + 1 && n->cq[cqid] !=3D NULL ? 0 = : -1; } =20 static void nvme_inc_cq_tail(NvmeCQueue *cq) @@ -642,7 +643,7 @@ static uint16_t nvme_create_cq(NvmeCtrl *n, NvmeCmd *cm= d) trace_pci_nvme_err_invalid_create_cq_addr(prp1); return NVME_INVALID_FIELD | NVME_DNR; } - if (unlikely(vector > n->params.num_queues)) { + if (unlikely(vector > n->params.max_ioqpairs + 1)) { trace_pci_nvme_err_invalid_create_cq_vector(vector); return NVME_INVALID_IRQ_VECTOR | NVME_DNR; } @@ -794,8 +795,8 @@ static uint16_t nvme_get_feature(NvmeCtrl *n, NvmeCmd *= cmd, NvmeRequest *req) trace_pci_nvme_getfeat_vwcache(result ? "enabled" : "disabled"); break; case NVME_NUMBER_OF_QUEUES: - result =3D cpu_to_le32((n->params.num_queues - 2) | - ((n->params.num_queues - 2) << 16)); + result =3D cpu_to_le32((n->params.max_ioqpairs - 1) | + ((n->params.max_ioqpairs - 1) << 16)); trace_pci_nvme_getfeat_numq(result); break; case NVME_TIMESTAMP: @@ -839,10 +840,10 @@ static uint16_t nvme_set_feature(NvmeCtrl *n, NvmeCmd= *cmd, NvmeRequest *req) case NVME_NUMBER_OF_QUEUES: trace_pci_nvme_setfeat_numq((dw11 & 0xFFFF) + 1, ((dw11 >> 16) & 0xFFFF) + 1, - n->params.num_queues - 1, - n->params.num_queues - 1); - req->cqe.result =3D cpu_to_le32((n->params.num_queues - 2) | - ((n->params.num_queues - 2) << 16)); + n->params.max_ioqpairs, + n->params.max_ioqpairs); + req->cqe.result =3D cpu_to_le32((n->params.max_ioqpairs - 1) | + ((n->params.max_ioqpairs - 1) << 16)= ); break; case NVME_TIMESTAMP: return nvme_set_feature_timestamp(n, cmd); @@ -913,12 +914,12 @@ static void nvme_clear_ctrl(NvmeCtrl *n) =20 blk_drain(n->conf.blk); =20 - for (i =3D 0; i < n->params.num_queues; i++) { + for (i =3D 0; i < n->params.max_ioqpairs + 1; i++) { if (n->sq[i] !=3D NULL) { nvme_free_sq(n->sq[i], n); } } - for (i =3D 0; i < n->params.num_queues; i++) { + for (i =3D 0; i < n->params.max_ioqpairs + 1; i++) { if (n->cq[i] !=3D NULL) { nvme_free_cq(n->cq[i], n); } @@ -1319,8 +1320,17 @@ static void nvme_realize(PCIDevice *pci_dev, Error *= *errp) int64_t bs_size; uint8_t *pci_conf; =20 - if (!n->params.num_queues) { - error_setg(errp, "num_queues can't be zero"); + if (n->params.num_queues) { + warn_report("num_queues is deprecated; please use max_ioqpairs " + "instead"); + + n->params.max_ioqpairs =3D n->params.num_queues - 1; + } + + if (n->params.max_ioqpairs < 1 || + n->params.max_ioqpairs > PCI_MSIX_FLAGS_QSIZE) { + error_setg(errp, "max_ioqpairs must be between 1 and %d", + PCI_MSIX_FLAGS_QSIZE); return; } =20 @@ -1353,21 +1363,21 @@ static void nvme_realize(PCIDevice *pci_dev, Error = **errp) =20 n->num_namespaces =3D 1; =20 - /* num_queues is really number of pairs, so each has two doorbells */ + /* add one to max_ioqpairs to account for the admin queue pair */ n->reg_size =3D pow2ceil(NVME_REG_SIZE + - 2 * n->params.num_queues * NVME_DB_SIZE); + 2 * (n->params.max_ioqpairs + 1) * NVME_DB_SIZE= ); n->ns_size =3D bs_size / (uint64_t)n->num_namespaces; =20 n->namespaces =3D g_new0(NvmeNamespace, n->num_namespaces); - n->sq =3D g_new0(NvmeSQueue *, n->params.num_queues); - n->cq =3D g_new0(NvmeCQueue *, n->params.num_queues); + n->sq =3D g_new0(NvmeSQueue *, n->params.max_ioqpairs + 1); + n->cq =3D g_new0(NvmeCQueue *, n->params.max_ioqpairs + 1); =20 memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme", n->reg_size); pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, &n->iomem); - msix_init_exclusive_bar(pci_dev, n->params.num_queues, 4, NULL); + msix_init_exclusive_bar(pci_dev, n->params.max_ioqpairs + 1, 4, NULL); =20 id->vid =3D cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID)); id->ssvid =3D cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR= _ID)); diff --git a/hw/block/nvme.h b/hw/block/nvme.h index 9957c4a200e2..1617787af2e9 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -6,11 +6,13 @@ #define DEFINE_NVME_PROPERTIES(_state, _props) \ DEFINE_PROP_STRING("serial", _state, _props.serial), \ DEFINE_PROP_UINT32("cmb_size_mb", _state, _props.cmb_size_mb, 0), \ - DEFINE_PROP_UINT32("num_queues", _state, _props.num_queues, 64) + DEFINE_PROP_UINT32("num_queues", _state, _props.num_queues, 0), \ + DEFINE_PROP_UINT32("max_ioqpairs", _state, _props.max_ioqpairs, 64) =20 typedef struct NvmeParams { char *serial; - uint32_t num_queues; + uint32_t num_queues; /* deprecated since 5.1 */ + uint32_t max_ioqpairs; uint32_t cmb_size_mb; } NvmeParams; =20 --=20 2.26.0 From nobody Thu May 16 14:23:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Wed, 15 Apr 2020 09:02:24 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id 0A19FBFD37; Wed, 15 Apr 2020 13:02:23 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v2 08/16] nvme: remove redundant cmbloc/cmbsz members Date: Wed, 15 Apr 2020 15:01:51 +0200 Message-Id: <20200415130159.611361-9-its@irrelevant.dk> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200415130159.611361-1-its@irrelevant.dk> References: <20200415130159.611361-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 128.199.63.193 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen Signed-off-by: Klaus Jensen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by. Reviewed-by's ;) Reviewed-by: Keith Busch Reviewed-by: Maxim Levitsky --- hw/block/nvme.c | 7 ++----- hw/block/nvme.h | 2 -- 2 files changed, 2 insertions(+), 7 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 8092c1b46eb1..44856e873fd1 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -66,7 +66,7 @@ static bool nvme_addr_is_cmb(NvmeCtrl *n, hwaddr addr) =20 static void nvme_addr_read(NvmeCtrl *n, hwaddr addr, void *buf, int size) { - if (n->cmbsz && nvme_addr_is_cmb(n, addr)) { + if (n->bar.cmbsz && nvme_addr_is_cmb(n, addr)) { memcpy(buf, (void *)&n->cmbuf[addr - n->ctrl_mem.addr], size); return; } @@ -160,7 +160,7 @@ static uint16_t nvme_map_prp(QEMUSGList *qsg, QEMUIOVec= tor *iov, uint64_t prp1, if (unlikely(!prp1)) { trace_pci_nvme_err_invalid_prp(); return NVME_INVALID_FIELD | NVME_DNR; - } else if (n->cmbsz && prp1 >=3D n->ctrl_mem.addr && + } else if (n->bar.cmbsz && prp1 >=3D n->ctrl_mem.addr && prp1 < n->ctrl_mem.addr + int128_get64(n->ctrl_mem.size)) { qsg->nsg =3D 0; qemu_iovec_init(iov, num_prps); @@ -1425,9 +1425,6 @@ static void nvme_realize(PCIDevice *pci_dev, Error **= errp) NVME_CMBSZ_SET_SZU(n->bar.cmbsz, 2); /* MBs */ NVME_CMBSZ_SET_SZ(n->bar.cmbsz, n->params.cmb_size_mb); =20 - n->cmbloc =3D n->bar.cmbloc; - n->cmbsz =3D n->bar.cmbsz; - n->cmbuf =3D g_malloc0(NVME_CMBSZ_GETSIZE(n->bar.cmbsz)); memory_region_init_io(&n->ctrl_mem, OBJECT(n), &nvme_cmb_ops, n, "nvme-cmb", NVME_CMBSZ_GETSIZE(n->bar.cmbsz)= ); diff --git a/hw/block/nvme.h b/hw/block/nvme.h index 1617787af2e9..7eecfd3a50f6 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -88,8 +88,6 @@ typedef struct NvmeCtrl { uint32_t num_namespaces; uint32_t max_q_ents; uint64_t ns_size; - uint32_t cmbsz; - uint32_t cmbloc; uint8_t *cmbuf; uint64_t irq_status; uint64_t host_timestamp; /* Timestamp sent by the h= ost */ --=20 2.26.0 From nobody Thu May 16 14:23:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Wed, 15 Apr 2020 09:02:24 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id 71DD2BFD3D; Wed, 15 Apr 2020 13:02:23 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v2 09/16] nvme: factor out property/constraint checks Date: Wed, 15 Apr 2020 15:01:52 +0200 Message-Id: <20200415130159.611361-10-its@irrelevant.dk> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200415130159.611361-1-its@irrelevant.dk> References: <20200415130159.611361-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 128.199.63.193 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen Signed-off-by: Klaus Jensen Acked-by. Reviewed-by's ;) Reviewed-by: Keith Busch Reviewed-by: Maxim Levitsky Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/block/nvme.c | 43 ++++++++++++++++++++++++++++--------------- 1 file changed, 28 insertions(+), 15 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 44856e873fd1..5f9ebbd6a1d5 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1311,24 +1311,19 @@ static const MemoryRegionOps nvme_cmb_ops =3D { }, }; =20 -static void nvme_realize(PCIDevice *pci_dev, Error **errp) +static void nvme_check_constraints(NvmeCtrl *n, Error **errp) { - NvmeCtrl *n =3D NVME(pci_dev); - NvmeIdCtrl *id =3D &n->id_ctrl; + NvmeParams *params =3D &n->params; =20 - int i; - int64_t bs_size; - uint8_t *pci_conf; - - if (n->params.num_queues) { + if (params->num_queues) { warn_report("num_queues is deprecated; please use max_ioqpairs " "instead"); =20 - n->params.max_ioqpairs =3D n->params.num_queues - 1; + params->max_ioqpairs =3D params->num_queues - 1; } =20 - if (n->params.max_ioqpairs < 1 || - n->params.max_ioqpairs > PCI_MSIX_FLAGS_QSIZE) { + if (params->max_ioqpairs < 1 || + params->max_ioqpairs > PCI_MSIX_FLAGS_QSIZE) { error_setg(errp, "max_ioqpairs must be between 1 and %d", PCI_MSIX_FLAGS_QSIZE); return; @@ -1339,16 +1334,34 @@ static void nvme_realize(PCIDevice *pci_dev, Error = **errp) return; } =20 + if (!params->serial) { + error_setg(errp, "serial property not set"); + return; + } +} + +static void nvme_realize(PCIDevice *pci_dev, Error **errp) +{ + NvmeCtrl *n =3D NVME(pci_dev); + NvmeIdCtrl *id =3D &n->id_ctrl; + Error *err =3D NULL; + + int i; + int64_t bs_size; + uint8_t *pci_conf; + + nvme_check_constraints(n, &err); + if (err) { + error_propagate(errp, err); + return; + } + bs_size =3D blk_getlength(n->conf.blk); if (bs_size < 0) { error_setg(errp, "could not get backing file size"); return; } =20 - if (!n->params.serial) { - error_setg(errp, "serial property not set"); - return; - } blkconf_blocksizes(&n->conf); if (!blkconf_apply_backend_options(&n->conf, blk_is_read_only(n->conf.= blk), false, errp)) { --=20 2.26.0 From nobody Thu May 16 14:23:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Wed, 15 Apr 2020 09:02:25 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id D4FC4BFD4F; Wed, 15 Apr 2020 13:02:23 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v2 10/16] nvme: factor out device state setup Date: Wed, 15 Apr 2020 15:01:53 +0200 Message-Id: <20200415130159.611361-11-its@irrelevant.dk> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200415130159.611361-1-its@irrelevant.dk> References: <20200415130159.611361-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 128.199.63.193 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen Signed-off-by: Klaus Jensen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by. Reviewed-by's ;) Reviewed-by: Keith Busch Reviewed-by: Maxim Levitsky --- hw/block/nvme.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 5f9ebbd6a1d5..45a352b63d89 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1340,6 +1340,17 @@ static void nvme_check_constraints(NvmeCtrl *n, Erro= r **errp) } } =20 +static void nvme_init_state(NvmeCtrl *n) +{ + n->num_namespaces =3D 1; + /* add one to max_ioqpairs to account for the admin queue pair */ + n->reg_size =3D pow2ceil(NVME_REG_SIZE + + 2 * (n->params.max_ioqpairs + 1) * NVME_DB_SIZE= ); + n->namespaces =3D g_new0(NvmeNamespace, n->num_namespaces); + n->sq =3D g_new0(NvmeSQueue *, n->params.max_ioqpairs + 1); + n->cq =3D g_new0(NvmeCQueue *, n->params.max_ioqpairs + 1); +} + static void nvme_realize(PCIDevice *pci_dev, Error **errp) { NvmeCtrl *n =3D NVME(pci_dev); @@ -1356,6 +1367,8 @@ static void nvme_realize(PCIDevice *pci_dev, Error **= errp) return; } =20 + nvme_init_state(n); + bs_size =3D blk_getlength(n->conf.blk); if (bs_size < 0) { error_setg(errp, "could not get backing file size"); @@ -1374,17 +1387,8 @@ static void nvme_realize(PCIDevice *pci_dev, Error *= *errp) pci_config_set_class(pci_dev->config, PCI_CLASS_STORAGE_EXPRESS); pcie_endpoint_cap_init(pci_dev, 0x80); =20 - n->num_namespaces =3D 1; - - /* add one to max_ioqpairs to account for the admin queue pair */ - n->reg_size =3D pow2ceil(NVME_REG_SIZE + - 2 * (n->params.max_ioqpairs + 1) * NVME_DB_SIZE= ); n->ns_size =3D bs_size / (uint64_t)n->num_namespaces; =20 - n->namespaces =3D g_new0(NvmeNamespace, n->num_namespaces); - n->sq =3D g_new0(NvmeSQueue *, n->params.max_ioqpairs + 1); - n->cq =3D g_new0(NvmeCQueue *, n->params.max_ioqpairs + 1); - memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme", n->reg_size); pci_register_bar(pci_dev, 0, --=20 2.26.0 From nobody Thu May 16 14:23:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Wed, 15 Apr 2020 09:02:46 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id 4867EBF7AF; Wed, 15 Apr 2020 13:02:24 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v2 11/16] nvme: factor out block backend setup Date: Wed, 15 Apr 2020 15:01:54 +0200 Message-Id: <20200415130159.611361-12-its@irrelevant.dk> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200415130159.611361-1-its@irrelevant.dk> References: <20200415130159.611361-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 128.199.63.193 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen Signed-off-by: Klaus Jensen Acked-by. Reviewed-by's ;) Reviewed-by: Keith Busch Reviewed-by: Maxim Levitsky Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/block/nvme.c | 13 ++++++++++--- 1 file changed, 10 insertions(+), 3 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 45a352b63d89..80da0825d295 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1351,6 +1351,13 @@ static void nvme_init_state(NvmeCtrl *n) n->cq =3D g_new0(NvmeCQueue *, n->params.max_ioqpairs + 1); } =20 +static void nvme_init_blk(NvmeCtrl *n, Error **errp) +{ + blkconf_blocksizes(&n->conf); + blkconf_apply_backend_options(&n->conf, blk_is_read_only(n->conf.blk), + false, errp); +} + static void nvme_realize(PCIDevice *pci_dev, Error **errp) { NvmeCtrl *n =3D NVME(pci_dev); @@ -1375,9 +1382,9 @@ static void nvme_realize(PCIDevice *pci_dev, Error **= errp) return; } =20 - blkconf_blocksizes(&n->conf); - if (!blkconf_apply_backend_options(&n->conf, blk_is_read_only(n->conf.= blk), - false, errp)) { + nvme_init_blk(n, &err); + if (err) { + error_propagate(errp, err); return; } =20 --=20 2.26.0 From nobody Thu May 16 14:23:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1586956411; cv=none; d=zohomail.com; s=zohoarc; b=Zng8SqceK1MPzicniSysLZzEP6ahUzDQcoyrbXVRT6nNioOuDJ1l72zwjIFRZnq7/GjIOQjfA9B4BETdZE2RxuCma108FiKimh5x24HwMAv0fPAQCoB7ogSQUvZ11BNKvqIi575qHz9/YAhnTLnLIKGqSyrTz5Uru7qbDaneaRk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1586956411; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=B1FEH0jug2DynmvFCrv9tybB11TVL/iyG1OfXDULxbA=; b=CoIttIiQOjECPLRQ3b2yE2SxNatBanAqDW82WZWukWQdzsEwpjykmvRKOcBsF5me1hkagV0Ct6Pn6lj72C9GdHOX5r+JE6G7CnLxpCIrGInimi/FEEXAXPLb3IWiAynWISGM1SBt0H4tCPPsKam+PyIWczzIyUomzzt6GMPYqx8= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1586956411424342.71699117284504; Wed, 15 Apr 2020 06:13:31 -0700 (PDT) Received: from localhost ([::1]:49858 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jOhr7-0000eA-VG for importer@patchew.org; Wed, 15 Apr 2020 09:13:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33904) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jOhgt-0007YB-TW for qemu-devel@nongnu.org; Wed, 15 Apr 2020 09:02:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jOhgs-0004aU-QE for qemu-devel@nongnu.org; Wed, 15 Apr 2020 09:02:55 -0400 Received: from charlie.dont.surf ([128.199.63.193]:48626) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jOhgl-0004DI-Py; Wed, 15 Apr 2020 09:02:47 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id B5E06BF9F3; Wed, 15 Apr 2020 13:02:24 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v2 12/16] nvme: add namespace helpers Date: Wed, 15 Apr 2020 15:01:55 +0200 Message-Id: <20200415130159.611361-13-its@irrelevant.dk> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200415130159.611361-1-its@irrelevant.dk> References: <20200415130159.611361-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 128.199.63.193 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen Introduce some small helpers to make the next patches easier on the eye. Signed-off-by: Klaus Jensen Acked-by. Reviewed-by's ;) Reviewed-by: Keith Busch Reviewed-by: Maxim Levitsky Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/block/nvme.c | 3 +-- hw/block/nvme.h | 16 ++++++++++++++++ 2 files changed, 17 insertions(+), 2 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 80da0825d295..d5244102252c 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1469,8 +1469,7 @@ static void nvme_realize(PCIDevice *pci_dev, Error **= errp) id_ns->dps =3D 0; id_ns->lbaf[0].ds =3D BDRV_SECTOR_BITS; id_ns->ncap =3D id_ns->nuse =3D id_ns->nsze =3D - cpu_to_le64(n->ns_size >> - id_ns->lbaf[NVME_ID_NS_FLBAS_INDEX(ns->id_ns.flbas)].ds); + cpu_to_le64(nvme_ns_nlbas(n, ns)); } } =20 diff --git a/hw/block/nvme.h b/hw/block/nvme.h index 7eecfd3a50f6..dd932a9e7ebc 100644 --- a/hw/block/nvme.h +++ b/hw/block/nvme.h @@ -67,6 +67,17 @@ typedef struct NvmeNamespace { NvmeIdNs id_ns; } NvmeNamespace; =20 +static inline NvmeLBAF *nvme_ns_lbaf(NvmeNamespace *ns) +{ + NvmeIdNs *id_ns =3D &ns->id_ns; + return &id_ns->lbaf[NVME_ID_NS_FLBAS_INDEX(id_ns->flbas)]; +} + +static inline uint8_t nvme_ns_lbads(NvmeNamespace *ns) +{ + return nvme_ns_lbaf(ns)->ds; +} + #define TYPE_NVME "nvme" #define NVME(obj) \ OBJECT_CHECK(NvmeCtrl, (obj), TYPE_NVME) @@ -101,4 +112,9 @@ typedef struct NvmeCtrl { NvmeIdCtrl id_ctrl; } NvmeCtrl; =20 +static inline uint64_t nvme_ns_nlbas(NvmeCtrl *n, NvmeNamespace *ns) +{ + return n->ns_size >> nvme_ns_lbads(ns); +} + #endif /* HW_NVME_H */ --=20 2.26.0 From nobody Thu May 16 14:23:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1586956307; cv=none; d=zohomail.com; s=zohoarc; b=NtWR/P2fpkJ7SCTq68pbaT1G2lqUwjVar0sYPgm0m4zSKiRWeFc3n7IEuzVlQUHGCyKOBJAFCrvqgeRIRlxVVwaNS+qTnJVT7QZm9HmlUEyGMztMgeDGUiV0W1twUmYpsv8iG5Dckj38hG5D23FeVUsP2460BOf58tpfByH74HE= ARC-Message-Signature: i=1; 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Wed, 15 Apr 2020 09:11:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33881) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jOhgo-0007Vy-VK for qemu-devel@nongnu.org; Wed, 15 Apr 2020 09:02:54 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jOhgn-0004Xr-K1 for qemu-devel@nongnu.org; Wed, 15 Apr 2020 09:02:50 -0400 Received: from charlie.dont.surf ([128.199.63.193]:48636) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jOhgk-0004Dn-Je; Wed, 15 Apr 2020 09:02:46 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id 22765BFD52; Wed, 15 Apr 2020 13:02:25 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v2 13/16] nvme: factor out namespace setup Date: Wed, 15 Apr 2020 15:01:56 +0200 Message-Id: <20200415130159.611361-14-its@irrelevant.dk> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200415130159.611361-1-its@irrelevant.dk> References: <20200415130159.611361-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 128.199.63.193 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen Signed-off-by: Klaus Jensen Acked-by. Reviewed-by's ;) Reviewed-by: Keith Busch Reviewed-by: Maxim Levitsky Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/block/nvme.c | 46 ++++++++++++++++++++++++++-------------------- 1 file changed, 26 insertions(+), 20 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index d5244102252c..2b007115c302 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1358,6 +1358,27 @@ static void nvme_init_blk(NvmeCtrl *n, Error **errp) false, errp); } =20 +static void nvme_init_namespace(NvmeCtrl *n, NvmeNamespace *ns, Error **er= rp) +{ + int64_t bs_size; + NvmeIdNs *id_ns =3D &ns->id_ns; + + bs_size =3D blk_getlength(n->conf.blk); + if (bs_size < 0) { + error_setg_errno(errp, -bs_size, "could not get backing file size"= ); + return; + } + + n->ns_size =3D bs_size; + + id_ns->lbaf[0].ds =3D BDRV_SECTOR_BITS; + id_ns->nsze =3D cpu_to_le64(nvme_ns_nlbas(n, ns)); + + /* no thin provisioning */ + id_ns->ncap =3D id_ns->nsze; + id_ns->nuse =3D id_ns->ncap; +} + static void nvme_realize(PCIDevice *pci_dev, Error **errp) { NvmeCtrl *n =3D NVME(pci_dev); @@ -1365,7 +1386,6 @@ static void nvme_realize(PCIDevice *pci_dev, Error **= errp) Error *err =3D NULL; =20 int i; - int64_t bs_size; uint8_t *pci_conf; =20 nvme_check_constraints(n, &err); @@ -1376,12 +1396,6 @@ static void nvme_realize(PCIDevice *pci_dev, Error *= *errp) =20 nvme_init_state(n); =20 - bs_size =3D blk_getlength(n->conf.blk); - if (bs_size < 0) { - error_setg(errp, "could not get backing file size"); - return; - } - nvme_init_blk(n, &err); if (err) { error_propagate(errp, err); @@ -1394,8 +1408,6 @@ static void nvme_realize(PCIDevice *pci_dev, Error **= errp) pci_config_set_class(pci_dev->config, PCI_CLASS_STORAGE_EXPRESS); pcie_endpoint_cap_init(pci_dev, 0x80); =20 - n->ns_size =3D bs_size / (uint64_t)n->num_namespaces; - memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme", n->reg_size); pci_register_bar(pci_dev, 0, @@ -1459,17 +1471,11 @@ static void nvme_realize(PCIDevice *pci_dev, Error = **errp) } =20 for (i =3D 0; i < n->num_namespaces; i++) { - NvmeNamespace *ns =3D &n->namespaces[i]; - NvmeIdNs *id_ns =3D &ns->id_ns; - id_ns->nsfeat =3D 0; - id_ns->nlbaf =3D 0; - id_ns->flbas =3D 0; - id_ns->mc =3D 0; - id_ns->dpc =3D 0; - id_ns->dps =3D 0; - id_ns->lbaf[0].ds =3D BDRV_SECTOR_BITS; - id_ns->ncap =3D id_ns->nuse =3D id_ns->nsze =3D - cpu_to_le64(nvme_ns_nlbas(n, ns)); + nvme_init_namespace(n, &n->namespaces[i], &err); + if (err) { + error_propagate(errp, err); + return; + } } } =20 --=20 2.26.0 From nobody Thu May 16 14:23:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1586956439; cv=none; d=zohomail.com; s=zohoarc; b=m/OcMHtXByaRqU1hbqxGcovQN7l/WGicPNyvvMHQ+vYwBIZEd2o1YU1HE4HEPKjPsk5Zs06kL54WeISH0G4d6JpixowQpPYp86ZoYp7hg+F91+Rt9nYtWGNqr6yyg+eQTY4WNr9Xecp+9ASBcvQ0utJof+JcA/cqv1LTQAVJzGk= ARC-Message-Signature: i=1; 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Wed, 15 Apr 2020 09:13:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:33909) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jOhgu-0007YF-8x for qemu-devel@nongnu.org; Wed, 15 Apr 2020 09:02:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jOhgt-0004ag-6f for qemu-devel@nongnu.org; Wed, 15 Apr 2020 09:02:56 -0400 Received: from charlie.dont.surf ([128.199.63.193]:48642) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jOhgl-0004En-Pf; Wed, 15 Apr 2020 09:02:47 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id 813E4BFB38; Wed, 15 Apr 2020 13:02:25 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v2 14/16] nvme: factor out pci setup Date: Wed, 15 Apr 2020 15:01:57 +0200 Message-Id: <20200415130159.611361-15-its@irrelevant.dk> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200415130159.611361-1-its@irrelevant.dk> References: <20200415130159.611361-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 128.199.63.193 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen Signed-off-by: Klaus Jensen Acked-by. Reviewed-by's ;) Reviewed-by: Keith Busch Reviewed-by: Maxim Levitsky Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- hw/block/nvme.c | 30 ++++++++++++++++++------------ 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 2b007115c302..906ae595025a 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1379,6 +1379,22 @@ static void nvme_init_namespace(NvmeCtrl *n, NvmeNam= espace *ns, Error **errp) id_ns->nuse =3D id_ns->ncap; } =20 +static void nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev) +{ + uint8_t *pci_conf =3D pci_dev->config; + + pci_conf[PCI_INTERRUPT_PIN] =3D 1; + pci_config_set_prog_interface(pci_conf, 0x2); + pci_config_set_class(pci_conf, PCI_CLASS_STORAGE_EXPRESS); + pcie_endpoint_cap_init(pci_dev, 0x80); + + memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, "nvme", + n->reg_size); + pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | + PCI_BASE_ADDRESS_MEM_TYPE_64, &n->iomem); + msix_init_exclusive_bar(pci_dev, n->params.max_ioqpairs + 1, 4, NULL); +} + static void nvme_realize(PCIDevice *pci_dev, Error **errp) { NvmeCtrl *n =3D NVME(pci_dev); @@ -1402,19 +1418,9 @@ static void nvme_realize(PCIDevice *pci_dev, Error *= *errp) return; } =20 + nvme_init_pci(n, pci_dev); + pci_conf =3D pci_dev->config; - pci_conf[PCI_INTERRUPT_PIN] =3D 1; - pci_config_set_prog_interface(pci_dev->config, 0x2); - pci_config_set_class(pci_dev->config, PCI_CLASS_STORAGE_EXPRESS); - pcie_endpoint_cap_init(pci_dev, 0x80); - - memory_region_init_io(&n->iomem, OBJECT(n), &nvme_mmio_ops, n, - "nvme", n->reg_size); - pci_register_bar(pci_dev, 0, - PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, - &n->iomem); - msix_init_exclusive_bar(pci_dev, n->params.max_ioqpairs + 1, 4, NULL); - id->vid =3D cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID)); id->ssvid =3D cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR= _ID)); strpadcpy((char *)id->mn, sizeof(id->mn), "QEMU NVMe Ctrl", ' '); --=20 2.26.0 From nobody Thu May 16 14:23:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Wed, 15 Apr 2020 09:02:47 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id 04BFABFD5C; Wed, 15 Apr 2020 13:02:25 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v2 15/16] nvme: factor out cmb setup Date: Wed, 15 Apr 2020 15:01:58 +0200 Message-Id: <20200415130159.611361-16-its@irrelevant.dk> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200415130159.611361-1-its@irrelevant.dk> References: <20200415130159.611361-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 128.199.63.193 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen Signed-off-by: Klaus Jensen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by. Reviewed-by's ;) Reviewed-by: Keith Busch Reviewed-by: Maxim Levitsky --- hw/block/nvme.c | 49 +++++++++++++++++++++++++++---------------------- 1 file changed, 27 insertions(+), 22 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 906ae595025a..4c28d75e0fc8 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -46,6 +46,7 @@ =20 #define NVME_REG_SIZE 0x1000 #define NVME_DB_SIZE 4 +#define NVME_CMB_BIR 2 =20 #define NVME_GUEST_ERR(trace, fmt, ...) \ do { \ @@ -1379,6 +1380,28 @@ static void nvme_init_namespace(NvmeCtrl *n, NvmeNam= espace *ns, Error **errp) id_ns->nuse =3D id_ns->ncap; } =20 +static void nvme_init_cmb(NvmeCtrl *n, PCIDevice *pci_dev) +{ + NVME_CMBLOC_SET_BIR(n->bar.cmbloc, NVME_CMB_BIR); + NVME_CMBLOC_SET_OFST(n->bar.cmbloc, 0); + + NVME_CMBSZ_SET_SQS(n->bar.cmbsz, 1); + NVME_CMBSZ_SET_CQS(n->bar.cmbsz, 0); + NVME_CMBSZ_SET_LISTS(n->bar.cmbsz, 0); + NVME_CMBSZ_SET_RDS(n->bar.cmbsz, 1); + NVME_CMBSZ_SET_WDS(n->bar.cmbsz, 1); + NVME_CMBSZ_SET_SZU(n->bar.cmbsz, 2); /* MBs */ + NVME_CMBSZ_SET_SZ(n->bar.cmbsz, n->params.cmb_size_mb); + + n->cmbuf =3D g_malloc0(NVME_CMBSZ_GETSIZE(n->bar.cmbsz)); + memory_region_init_io(&n->ctrl_mem, OBJECT(n), &nvme_cmb_ops, n, + "nvme-cmb", NVME_CMBSZ_GETSIZE(n->bar.cmbsz)); + pci_register_bar(pci_dev, NVME_CMBLOC_BIR(n->bar.cmbloc), + PCI_BASE_ADDRESS_SPACE_MEMORY | + PCI_BASE_ADDRESS_MEM_TYPE_64 | + PCI_BASE_ADDRESS_MEM_PREFETCH, &n->ctrl_mem); +} + static void nvme_init_pci(NvmeCtrl *n, PCIDevice *pci_dev) { uint8_t *pci_conf =3D pci_dev->config; @@ -1393,6 +1416,10 @@ static void nvme_init_pci(NvmeCtrl *n, PCIDevice *pc= i_dev) pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64, &n->iomem); msix_init_exclusive_bar(pci_dev, n->params.max_ioqpairs + 1, 4, NULL); + + if (n->params.cmb_size_mb) { + nvme_init_cmb(n, pci_dev); + } } =20 static void nvme_realize(PCIDevice *pci_dev, Error **errp) @@ -1454,28 +1481,6 @@ static void nvme_realize(PCIDevice *pci_dev, Error *= *errp) n->bar.vs =3D 0x00010200; n->bar.intmc =3D n->bar.intms =3D 0; =20 - if (n->params.cmb_size_mb) { - - NVME_CMBLOC_SET_BIR(n->bar.cmbloc, 2); - NVME_CMBLOC_SET_OFST(n->bar.cmbloc, 0); - - NVME_CMBSZ_SET_SQS(n->bar.cmbsz, 1); - NVME_CMBSZ_SET_CQS(n->bar.cmbsz, 0); - NVME_CMBSZ_SET_LISTS(n->bar.cmbsz, 0); - NVME_CMBSZ_SET_RDS(n->bar.cmbsz, 1); - NVME_CMBSZ_SET_WDS(n->bar.cmbsz, 1); - NVME_CMBSZ_SET_SZU(n->bar.cmbsz, 2); /* MBs */ - NVME_CMBSZ_SET_SZ(n->bar.cmbsz, n->params.cmb_size_mb); - - n->cmbuf =3D g_malloc0(NVME_CMBSZ_GETSIZE(n->bar.cmbsz)); - memory_region_init_io(&n->ctrl_mem, OBJECT(n), &nvme_cmb_ops, n, - "nvme-cmb", NVME_CMBSZ_GETSIZE(n->bar.cmbsz)= ); - pci_register_bar(pci_dev, NVME_CMBLOC_BIR(n->bar.cmbloc), - PCI_BASE_ADDRESS_SPACE_MEMORY | PCI_BASE_ADDRESS_MEM_TYPE_64 | - PCI_BASE_ADDRESS_MEM_PREFETCH, &n->ctrl_mem); - - } - for (i =3D 0; i < n->num_namespaces; i++) { nvme_init_namespace(n, &n->namespaces[i], &err); if (err) { --=20 2.26.0 From nobody Thu May 16 14:23:35 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Wed, 15 Apr 2020 09:02:47 -0400 Received: from apples.local (80-167-98-190-cable.dk.customer.tdc.net [80.167.98.190]) by charlie.dont.surf (Postfix) with ESMTPSA id 76ECFBFD5F; Wed, 15 Apr 2020 13:02:26 +0000 (UTC) From: Klaus Jensen To: qemu-block@nongnu.org Subject: [PATCH v2 16/16] nvme: factor out controller identify setup Date: Wed, 15 Apr 2020 15:01:59 +0200 Message-Id: <20200415130159.611361-17-its@irrelevant.dk> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200415130159.611361-1-its@irrelevant.dk> References: <20200415130159.611361-1-its@irrelevant.dk> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 128.199.63.193 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Kevin Wolf , Beata Michalska , Klaus Jensen , qemu-devel@nongnu.org, Max Reitz , Klaus Jensen , Keith Busch , Javier Gonzalez , Maxim Levitsky , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Klaus Jensen Signed-off-by: Klaus Jensen Reviewed-by: Philippe Mathieu-Daud=C3=A9 Acked-by. Reviewed-by's ;) Reviewed-by: Keith Busch Reviewed-by: Maxim Levitsky --- hw/block/nvme.c | 52 +++++++++++++++++++++++++++---------------------- 1 file changed, 29 insertions(+), 23 deletions(-) diff --git a/hw/block/nvme.c b/hw/block/nvme.c index 4c28d75e0fc8..804f24719dce 100644 --- a/hw/block/nvme.c +++ b/hw/block/nvme.c @@ -1422,32 +1422,11 @@ static void nvme_init_pci(NvmeCtrl *n, PCIDevice *p= ci_dev) } } =20 -static void nvme_realize(PCIDevice *pci_dev, Error **errp) +static void nvme_init_ctrl(NvmeCtrl *n, PCIDevice *pci_dev) { - NvmeCtrl *n =3D NVME(pci_dev); NvmeIdCtrl *id =3D &n->id_ctrl; - Error *err =3D NULL; + uint8_t *pci_conf =3D pci_dev->config; =20 - int i; - uint8_t *pci_conf; - - nvme_check_constraints(n, &err); - if (err) { - error_propagate(errp, err); - return; - } - - nvme_init_state(n); - - nvme_init_blk(n, &err); - if (err) { - error_propagate(errp, err); - return; - } - - nvme_init_pci(n, pci_dev); - - pci_conf =3D pci_dev->config; id->vid =3D cpu_to_le16(pci_get_word(pci_conf + PCI_VENDOR_ID)); id->ssvid =3D cpu_to_le16(pci_get_word(pci_conf + PCI_SUBSYSTEM_VENDOR= _ID)); strpadcpy((char *)id->mn, sizeof(id->mn), "QEMU NVMe Ctrl", ' '); @@ -1481,6 +1460,33 @@ static void nvme_realize(PCIDevice *pci_dev, Error *= *errp) n->bar.vs =3D 0x00010200; n->bar.intmc =3D n->bar.intms =3D 0; =20 + +} + +static void nvme_realize(PCIDevice *pci_dev, Error **errp) +{ + NvmeCtrl *n =3D NVME(pci_dev); + Error *err =3D NULL; + + int i; + + nvme_check_constraints(n, &err); + if (err) { + error_propagate(errp, err); + return; + } + + + nvme_init_state(n); + nvme_init_blk(n, &err); + if (err) { + error_propagate(errp, err); + return; + } + + nvme_init_pci(n, pci_dev); + nvme_init_ctrl(n, pci_dev); + for (i =3D 0; i < n->num_namespaces; i++) { nvme_init_namespace(n, &n->namespaces[i], &err); if (err) { --=20 2.26.0