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[83.42.57.116]) by smtp.gmail.com with ESMTPSA id d13sm12563559wrv.34.2020.04.12.15.37.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Apr 2020 15:37:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=p12zY90y1Bd/6q5GYHr9+QcqvAZOBpOvraHjQFK6FGo=; b=dQbz9LWP4CUHYwL9IsAzCeLPJ2Jnbwt3fEzV4t7GEE9SZjZ5dQ0dloPLYFDP81kDqO TPhuf/RRZL/VpaFz86QS5UAVBZVaThqxYy3jbnIeJ915sjz79HVXmwMlSIRLUMafZd82 clRYp2SAQj2cEMSaHIwS/RVdMqHAkWYVRGA2L5TIHWsTVBzmHDJhgl6hFJowOW0sZxo/ um7AcAEQ67ZUasBnJRxmnua9ZoEJ2H0MxfuA8G8yJgxSSkdekNA8A9Lo45bT7Cb0BNU0 oOejyPdVtCRDaPolK3dqj1UzwqY7rTvU/uJfc5RlK5Pwby/Q/6QOhtVNHOtZKatObS9e 8gmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=p12zY90y1Bd/6q5GYHr9+QcqvAZOBpOvraHjQFK6FGo=; b=QoVdnERrIGoeMM2uG8hp7ZZAKfCDAFQjybkC/oaQMjNmtSsHmY6KJuup8TmwFqBwQP J/kFEcIIUazCN4DnVZfpNioHPBI0tmEmh38tnUlC4yAKPV/Qi2Jp+yl8v1CqQl/J8mWY mWk2euxZ9I+/w/wFsFreyEx4867uHdICE6nAeYYtwPeDgaB6GPrqvFkMaSNEEfgQdCYD 9OsquUEJPGeraf1csV057L1ex/3tIwscwMd0fs9P257Clf7B6GP994NXGUB+Q/ddojSF /VBl9tWZYVY9c2q6y39e1BXh2tXc9WSZt69K7Y9lkgi84x1ltDyFM3r8xaHLBfwLzz5L r66Q== X-Gm-Message-State: AGi0PuakwNbOhHMh8y3ro7oo45CIclZMF3tBQq7YiP+2IjhySHlINYuE 4t0aYz+VY8vMKdO9sljoHtzoLVtTT9kxog== X-Google-Smtp-Source: APiQypIdtklaWgF7eJbTP4PpyDPoa6GPetn8GiVPl4PwWG1TGQaRAKzqYHcgcV/+VC20LcQMgEGTsg== X-Received: by 2002:a5d:45cf:: with SMTP id b15mr15479621wrs.274.1586731061947; Sun, 12 Apr 2020 15:37:41 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH-for-5.1 v3 23/24] hw/riscv/sifive_u: Move some code from realize() to init() Date: Mon, 13 Apr 2020 00:36:18 +0200 Message-Id: <20200412223619.11284-24-f4bug@amsat.org> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200412223619.11284-1-f4bug@amsat.org> References: <20200412223619.11284-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Peter Maydell , Sagar Karandikar , "Michael S. Tsirkin" , Jeff Cody , Jason Wang , Alistair Francis , "Edgar E. Iglesias" , Subbaraya Sundeep , qemu-block@nongnu.org, Markus Armbruster , Max Reitz , Joel Stanley , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Xie Changlong , Alistair Francis , Beniamino Galvani , qemu-arm@nongnu.org, Peter Chubb , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Palmer Dabbelt , David Gibson , Kevin Wolf , qemu-riscv@nongnu.org, Andrew Jeffery , Wen Congyang , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Jean-Christophe Dubois , qemu-ppc@nongnu.org, Bastian Koppelmann , Paolo Bonzini Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Coccinelle reported: $ spatch ... --timeout 60 --sp-file \ scripts/coccinelle/simplify-init-realize-error_propagate.cocci HANDLING: ./hw/riscv/sifive_u.c >>> possible moves from riscv_sifive_u_soc_init() to riscv_sifive_u_soc_r= ealize() in ./hw/riscv/sifive_u.c:473 Move the calls using &error_abort which don't depend on input updated before realize() to init(). Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis --- v3: Typo 'depend of' -> 'depend on' (eblake) --- hw/riscv/sifive_u.c | 42 ++++++++++++++++++++++-------------------- 1 file changed, 22 insertions(+), 20 deletions(-) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 96177c1977..7bf1f30a35 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -406,6 +406,8 @@ static void riscv_sifive_u_init(MachineState *machine) static void riscv_sifive_u_soc_init(Object *obj) { MachineState *ms =3D MACHINE(qdev_get_machine()); + const struct MemmapEntry *memmap =3D sifive_u_memmap; + MemoryRegion *system_memory =3D get_system_memory(); SiFiveUSoCState *s =3D RISCV_U_SOC(obj); =20 object_initialize_child(obj, "e-cluster", &s->e_cluster, @@ -443,6 +445,26 @@ static void riscv_sifive_u_soc_init(Object *obj) TYPE_CADENCE_GEM); object_property_set_int(OBJECT(&s->gem), GEM_REVISION, "revision", &error_abort); + + /* boot rom */ + memory_region_init_rom(&s->mask_rom, obj, "riscv.sifive.u.mrom", + memmap[SIFIVE_U_MROM].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base, + &s->mask_rom); + + /* + * Add L2-LIM at reset size. + * This should be reduced in size as the L2 Cache Controller WayEnable + * register is incremented. Unfortunately I don't see a nice (or any) = way + * to handle reducing or blocking out the L2 LIM while still allowing = it + * be re returned to all enabled after a reset. For the time being, ju= st + * leave it enabled all the time. This won't break anything, but will = be + * too generous to misbehaving guests. + */ + memory_region_init_ram(&s->l2lim_mem, NULL, "riscv.sifive.u.l2lim", + memmap[SIFIVE_U_L2LIM].size, &error_fatal); + memory_region_add_subregion(system_memory, memmap[SIFIVE_U_L2LIM].base, + &s->l2lim_mem); } =20 static bool sifive_u_get_start_in_flash(Object *obj, Error **errp) @@ -500,26 +522,6 @@ static void riscv_sifive_u_soc_realize(DeviceState *de= v, Error **errp) object_property_set_bool(OBJECT(&s->u_cluster), true, "realized", &error_abort); =20 - /* boot rom */ - memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.u.mrom= ", - memmap[SIFIVE_U_MROM].size, &error_fatal); - memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base, - &s->mask_rom); - - /* - * Add L2-LIM at reset size. - * This should be reduced in size as the L2 Cache Controller WayEnable - * register is incremented. Unfortunately I don't see a nice (or any) = way - * to handle reducing or blocking out the L2 LIM while still allowing = it - * be re returned to all enabled after a reset. For the time being, ju= st - * leave it enabled all the time. This won't break anything, but will = be - * too generous to misbehaving guests. - */ - memory_region_init_ram(&s->l2lim_mem, NULL, "riscv.sifive.u.l2lim", - memmap[SIFIVE_U_L2LIM].size, &error_fatal); - memory_region_add_subregion(system_memory, memmap[SIFIVE_U_L2LIM].base, - &s->l2lim_mem); - /* create PLIC hart topology configuration string */ plic_hart_config_len =3D (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1) * ms->smp.cpus; --=20 2.21.1