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[83.42.57.116]) by smtp.gmail.com with ESMTPSA id r3sm12797798wrm.35.2020.04.12.14.29.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 12 Apr 2020 14:29:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0Gwk+omGQ520vgI5+JQYZuT2VgvX+0dicPgG2UZcDzk=; b=eVimAW8LJ/3xN40DXev6aOL40qLrsVif/IsVb6ny9/OwZqDC+VMIn70ECpdnTN3uQP F+Xoxh4izpZsb0+NLHgvxk52FzjcDsA52BYsZKrYCTVhwjhV7Z7AZ9CKN1zzWLFOBp+V PIf9Inf9RzZTxq3ClaKllBmEkeP6h2mfm5nJRPVQl1rJ+7uEvwx2iZNo8enFaF4vm3l8 rgsVHfGeor8XCC/UlxbUqg+Ktxbqwi/0N4GElg0l4HH0VxB3FO5PuMqgPx5ZuWOH2n2x psIe7nyIMEqKO6lF0cGuSXfMteMM9c6hWBL3YTZv+Uh2cjkBNMWYdlGUTHM1HRKMsNA8 Zasw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=0Gwk+omGQ520vgI5+JQYZuT2VgvX+0dicPgG2UZcDzk=; b=X5TNt+31ZXHAml+0dskDQZH4PFt4fHXKtYCzs/07uBV0tSJcvHLotnmUCzq9oi4Mxl j23wWt1UudVZc0JyeTQhAfgqXoh0CQ6iu1yJmWgaaAMDRUk7uNWmVXjhTUAhfW8Z0eTv DmFq9N0VLDh7pCT45MkGbkhNb8W/+av3y5EOI00H6PpiG3bC6+PTE+Lj4tBd0vY7cbEY b7PC9DZr+ncK+ZwK189pTPUApBjAlkmmOBcTEjQteMheZy9oATA/HqvAxAiiShubZDOS j47PhTnbRUphTRg0K3nkGzoyO+OLcaOSUNQdGaFh6JYsLigoNGYqShZF0C1/6WoYYk73 8bkw== X-Gm-Message-State: AGi0Pub91yTgiPkkRbihQsqvkIpUUrsVwMQsWynfJVGIaWpm94lezGa2 YITRnTawW56H5zvCTpxSS2vM/YUXMhc= X-Google-Smtp-Source: APiQypKfJyIo22oyMsO5+U7aw2dN66I1B2tx9eKMzXjP+oytyf38uq2SIyrHTIR3W8qlyCFOBBHtew== X-Received: by 2002:a1c:750a:: with SMTP id o10mr15561640wmc.161.1586726989044; Sun, 12 Apr 2020 14:29:49 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH-for-5.1 2/3] hw/mips/mips_int: Use qdev gpio rather than qemu_allocate_irqs() Date: Sun, 12 Apr 2020 23:29:42 +0200 Message-Id: <20200412212943.4117-3-f4bug@amsat.org> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200412212943.4117-1-f4bug@amsat.org> References: <20200412212943.4117-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::341 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-block@nongnu.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aleksandar Markovic , Stafford Horne , John Snow , Aleksandar Rikalo , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Switch to using the qdev gpio API which is preferred over qemu_allocate_irqs(). One step to eventually deprecate and remove qemu_allocate_irqs() one day. Patch created mechanically using spatch with this script inspired from commit d6ef883d9d7: @@ typedef qemu_irq; identifier irqs, handler; expression opaque, count, i; @@ - qemu_irq *irqs; ... - irqs =3D qemu_allocate_irqs(handler, opaque, count); + qdev_init_gpio_in(DEVICE(opaque), handler, count); <+... - irqs[i] + qdev_get_gpio_in(DEVICE(opaque), i) ...+> ?- g_free(irqs); Inspired-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/mips/mips_int.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c index 796730b11d..91788c51a9 100644 --- a/hw/mips/mips_int.c +++ b/hw/mips/mips_int.c @@ -74,14 +74,12 @@ static void cpu_mips_irq_request(void *opaque, int irq,= int level) void cpu_mips_irq_init_cpu(MIPSCPU *cpu) { CPUMIPSState *env =3D &cpu->env; - qemu_irq *qi; int i; =20 - qi =3D qemu_allocate_irqs(cpu_mips_irq_request, cpu, 8); + qdev_init_gpio_in(DEVICE(cpu), cpu_mips_irq_request, 8); for (i =3D 0; i < 8; i++) { - env->irq[i] =3D qi[i]; + env->irq[i] =3D qdev_get_gpio_in(DEVICE(cpu), i); } - g_free(qi); } =20 void cpu_mips_soft_irq(CPUMIPSState *env, int irq, int level) --=20 2.21.1