From nobody Tue Feb 10 07:43:12 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1586578733; cv=none; d=zohomail.com; s=zohoarc; b=JkWApZIjKL/NTVoioCTPBwTZJ5zjLKH71NyE+h+/35cFfqG/o8vnvwAznNz20qicoNo0COBIZUwndcv0a4HLQ+Zuzho/efGiSH547Ndnb4J7mw/4+jgU96QtfkI4muHpq/Nmm9L3cMSviNvXAvpa6qUI00Cv2H8K1KAkUjBFmxo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1586578733; h=Content-Type:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=y6mN4EK+/UJUtIMhKfvMCOAI8q+po/AQ7oNo/O7qm0Q=; b=DSiBJwF/UGuPNqMmz0X2Wos1Czge+BEQ00D4IDJmnkRFU9Bcf358IUTBPJAp7wD2Szj9RAqWXWD/klqE+jZnoJv6M/iMF1sHeLb9HXpWjz3NVrOvw8WdfqsrpgdFhqgVMyFKLcmPiN0rxbqt8zcpwRh3A810Q/wBViLqyne6EiI= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 15865787333841017.1358159224013; Fri, 10 Apr 2020 21:18:53 -0700 (PDT) Received: from localhost ([::1]:48580 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jN7bX-0004iR-66 for importer@patchew.org; Sat, 11 Apr 2020 00:18:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47115) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jN7ZZ-0000GT-Tv for qemu-devel@nongnu.org; Sat, 11 Apr 2020 00:16:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jN7ZY-0006VR-Qs for qemu-devel@nongnu.org; Sat, 11 Apr 2020 00:16:49 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:43826 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jN7ZY-0006OO-FO; Sat, 11 Apr 2020 00:16:48 -0400 Received: from DGGEMS408-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 7F044A2A2B3C4F1BD898; Sat, 11 Apr 2020 12:16:45 +0800 (CST) Received: from huawei.com (10.173.222.107) by DGGEMS408-HUB.china.huawei.com (10.3.19.208) with Microsoft SMTP Server id 14.3.487.0; Sat, 11 Apr 2020 12:16:39 +0800 From: Yifei Jiang To: , Subject: [PATCH RFC v2 9/9] target/riscv: add host cpu type Date: Sat, 11 Apr 2020 12:14:27 +0800 Message-ID: <20200411041427.14828-10-jiangyifei@huawei.com> X-Mailer: git-send-email 2.14.1.windows.1 In-Reply-To: <20200411041427.14828-1-jiangyifei@huawei.com> References: <20200411041427.14828-1-jiangyifei@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.173.222.107] X-CFilter-Loop: Reflected X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: victor.zhangxiaofeng@huawei.com, zhang.zhanghailiang@huawei.com, sagark@eecs.berkeley.edu, yinyipeng1@huawei.com, kbastian@mail.uni-paderborn.de, anup.patel@wdc.com, Alistair.Francis@wdc.com, kvm-riscv@lists.infradead.org, palmer@dabbelt.com, Yifei Jiang , dengkai1@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Currently, host cpu is inherited simply. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/cpu.c | 6 ++++++ target/riscv/cpu.h | 1 + 2 files changed, 7 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6a6af13ab9..e5b42c3a54 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -203,6 +203,10 @@ static void rv64imacu_nommu_cpu_init(Object *obj) set_feature(env, RISCV_FEATURE_PMP); } =20 +static void riscv_host_cpu_init(Object *obj) +{ +} + #endif =20 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) @@ -615,6 +619,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_CPU(TYPE_RISCV_CPU_BASE32, riscv_base32_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_in= it), + DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), /* Depreacted */ DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_in= it), @@ -623,6 +628,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_in= it), + DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), /* Deprecated */ DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_in= it), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index dcff112c5f..4901fd8061 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -39,6 +39,7 @@ #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") +#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") /* Deprecated */ #define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nom= mu") #define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9= .1") --=20 2.19.1