From nobody Fri May 10 08:50:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1586350797; cv=none; d=zohomail.com; s=zohoarc; b=Rjnd29L1CADWi/R/7o6ypIpQ4gPDYQPUScPGG8TGiNxjFHaWqGlyv69GtCCS2TLmgWgj4F8y0ZX3G5SWYRl1+PYPtdnUqspyz1C4xHRwszxoO2BIcl4Q0BZcnlK2iWj48A5SOV7tNKJCz2HBJ1fW+Iq2YyHqpu1f4cka7HDycBY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1586350797; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=M50y8SJFSlTT6/+3kXmj5+qiXG1gCBvdQOdKwXbiUHY=; b=BEE17x2nIurzl7KfhoQ/3gHkItnpXIOUxPIxgpZUPqv9DDjfMTZA9TGqX6Nv+YzmYxgKDwYFWR3TBurj13a89gZQ1zDtF8efGZvVoereg4Gox/GshV/+rSuM1XdEJiNWK4eMvu2+WeLjNdGC3NuYPa3G7HUGTDXri3ro/u7/BPY= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1586350797842798.7343497257672; Wed, 8 Apr 2020 05:59:57 -0700 (PDT) Received: from localhost ([::1]:35704 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jMAJ9-0001gY-Sc for importer@patchew.org; Wed, 08 Apr 2020 08:59:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39726) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jMAI6-0008VF-7A for qemu-devel@nongnu.org; Wed, 08 Apr 2020 08:58:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jMAI4-00057H-LL for qemu-devel@nongnu.org; Wed, 08 Apr 2020 08:58:50 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:3734 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jMAI4-00054j-1P for qemu-devel@nongnu.org; Wed, 08 Apr 2020 08:58:48 -0400 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id D4944FF1204E8B325098; Wed, 8 Apr 2020 20:58:39 +0800 (CST) Received: from DESKTOP-D7EVK5B.china.huawei.com (10.173.221.29) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.487.0; Wed, 8 Apr 2020 20:58:32 +0800 From: Yubo Miao To: , , Subject: [PATCH v6 1/8] acpi: Extract two APIs from acpi_dsdt_add_pci Date: Wed, 8 Apr 2020 20:58:09 +0800 Message-ID: <20200408125816.955-2-miaoyubo@huawei.com> X-Mailer: git-send-email 2.24.1.windows.2 In-Reply-To: <20200408125816.955-1-miaoyubo@huawei.com> References: <20200408125816.955-1-miaoyubo@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.173.221.29] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.191 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: berrange@redhat.com, mst@redhat.com, qemu-devel@nongnu.org, xiexiangyou@huawei.com, miaoyubo@huawei.com, imammedo@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: miaoyubo Extract two APIs acpi_dsdt_add_pci_route_table and acpi_dsdt_add_pci_osc form acpi_dsdt_add_pci. The first API is used to specify the pci route table and the second API is used to declare the operation system capabilities. These two APIs would be used to specify the pxb-pcie in DSDT. Signed-off-by: miaoyubo --- hw/arm/virt-acpi-build.c | 129 ++++++++++++++++++++++----------------- 1 file changed, 72 insertions(+), 57 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 7ef0733d71..e8ba09855c 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -146,29 +146,11 @@ static void acpi_dsdt_add_virtio(Aml *scope, } } =20 -static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, - uint32_t irq, bool use_highmem, bool highmem= _ecam) +static void acpi_dsdt_add_pci_route_table(Aml *dev, Aml *scope, + uint32_t irq) { - int ecam_id =3D VIRT_ECAM_ID(highmem_ecam); - Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf; int i, slot_no; - hwaddr base_mmio =3D memmap[VIRT_PCIE_MMIO].base; - hwaddr size_mmio =3D memmap[VIRT_PCIE_MMIO].size; - hwaddr base_pio =3D memmap[VIRT_PCIE_PIO].base; - hwaddr size_pio =3D memmap[VIRT_PCIE_PIO].size; - hwaddr base_ecam =3D memmap[ecam_id].base; - hwaddr size_ecam =3D memmap[ecam_id].size; - int nr_pcie_buses =3D size_ecam / PCIE_MMCFG_SIZE_MIN; - - Aml *dev =3D aml_device("%s", "PCI0"); - aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); - aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); - aml_append(dev, aml_name_decl("_SEG", aml_int(0))); - aml_append(dev, aml_name_decl("_BBN", aml_int(0))); - aml_append(dev, aml_name_decl("_UID", aml_string("PCI0"))); - aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device"))); - aml_append(dev, aml_name_decl("_CCA", aml_int(1))); - + Aml *method, *crs; /* Declare the PCI Routing Table. */ Aml *rt_pkg =3D aml_varpackage(PCI_SLOT_MAX * PCI_NUM_PINS); for (slot_no =3D 0; slot_no < PCI_SLOT_MAX; slot_no++) { @@ -204,41 +186,11 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMa= pEntry *memmap, aml_append(dev_gsi, method); aml_append(dev, dev_gsi); } +} =20 - method =3D aml_method("_CBA", 0, AML_NOTSERIALIZED); - aml_append(method, aml_return(aml_int(base_ecam))); - aml_append(dev, method); - - method =3D aml_method("_CRS", 0, AML_NOTSERIALIZED); - Aml *rbuf =3D aml_resource_template(); - aml_append(rbuf, - aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, - 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, - nr_pcie_buses)); - aml_append(rbuf, - aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, - AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_m= mio, - base_mmio + size_mmio - 1, 0x0000, size_mmio)); - aml_append(rbuf, - aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, - AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_= pio, - size_pio)); - - if (use_highmem) { - hwaddr base_mmio_high =3D memmap[VIRT_HIGH_PCIE_MMIO].base; - hwaddr size_mmio_high =3D memmap[VIRT_HIGH_PCIE_MMIO].size; - - aml_append(rbuf, - aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, - AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, - base_mmio_high, - base_mmio_high + size_mmio_high - 1, 0x0000, - size_mmio_high)); - } - - aml_append(method, aml_return(rbuf)); - aml_append(dev, method); - +static void acpi_dsdt_add_pci_osc(Aml *dev, Aml *scope) +{ + Aml *method, *UUID, *ifctx, *ifctx1, *elsectx, *buf; /* Declare an _OSC (OS Control Handoff) method */ aml_append(dev, aml_name_decl("SUPP", aml_int(0))); aml_append(dev, aml_name_decl("CTRL", aml_int(0))); @@ -246,7 +198,8 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapE= ntry *memmap, aml_append(method, aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); =20 - /* PCI Firmware Specification 3.0 + /* + * PCI Firmware Specification 3.0 * 4.5.1. _OSC Interface for PCI Host Bridge Devices * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is * identified by the Universal Unique IDentifier (UUID) @@ -291,7 +244,8 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapE= ntry *memmap, =20 method =3D aml_method("_DSM", 4, AML_NOTSERIALIZED); =20 - /* PCI Firmware Specification 3.0 + /* + * PCI Firmware Specification 3.0 * 4.6.1. _DSM for PCI Express Slot Information * The UUID in _DSM in this context is * {E5C937D0-3553-4D7A-9117-EA4D19C3434D} @@ -309,6 +263,67 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMap= Entry *memmap, buf =3D aml_buffer(1, byte_list); aml_append(method, aml_return(buf)); aml_append(dev, method); +} + +static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, + uint32_t irq, bool use_highmem, bool highmem= _ecam) +{ + int ecam_id =3D VIRT_ECAM_ID(highmem_ecam); + Aml *method, *crs; + hwaddr base_mmio =3D memmap[VIRT_PCIE_MMIO].base; + hwaddr size_mmio =3D memmap[VIRT_PCIE_MMIO].size; + hwaddr base_pio =3D memmap[VIRT_PCIE_PIO].base; + hwaddr size_pio =3D memmap[VIRT_PCIE_PIO].size; + hwaddr base_ecam =3D memmap[ecam_id].base; + hwaddr size_ecam =3D memmap[ecam_id].size; + int nr_pcie_buses =3D size_ecam / PCIE_MMCFG_SIZE_MIN; + + Aml *dev =3D aml_device("%s", "PCI0"); + aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); + aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); + aml_append(dev, aml_name_decl("_SEG", aml_int(0))); + aml_append(dev, aml_name_decl("_BBN", aml_int(0))); + aml_append(dev, aml_name_decl("_UID", aml_string("PCI0"))); + aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device"))); + aml_append(dev, aml_name_decl("_CCA", aml_int(1))); + + acpi_dsdt_add_pci_route_table(dev, scope, irq); + + method =3D aml_method("_CBA", 0, AML_NOTSERIALIZED); + aml_append(method, aml_return(aml_int(base_ecam))); + aml_append(dev, method); + + method =3D aml_method("_CRS", 0, AML_NOTSERIALIZED); + Aml *rbuf =3D aml_resource_template(); + aml_append(rbuf, + aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, + 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, + nr_pcie_buses)); + aml_append(rbuf, + aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, + AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_m= mio, + base_mmio + size_mmio - 1, 0x0000, size_mmio)); + aml_append(rbuf, + aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, + AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_= pio, + size_pio)); + + if (use_highmem) { + hwaddr base_mmio_high =3D memmap[VIRT_HIGH_PCIE_MMIO].base; + hwaddr size_mmio_high =3D memmap[VIRT_HIGH_PCIE_MMIO].size; + + aml_append(rbuf, + aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, + AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, + base_mmio_high, + base_mmio_high + size_mmio_high - 1, 0x0000, + size_mmio_high)); + } + + aml_append(method, aml_return(rbuf)); + aml_append(dev, method); + + acpi_dsdt_add_pci_osc(dev, scope); =20 Aml *dev_res0 =3D aml_device("%s", "RES0"); aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02"))); --=20 2.19.1 From nobody Fri May 10 08:50:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1586350799; cv=none; d=zohomail.com; s=zohoarc; b=lCAF8D5wQiLnrg5AHct7lcfTRMzCH6Csl46J/ZS5DNbUKez5ruX0pP58RUrw9U9WUoXoYGjyrK/wsobb+lz7Y9AdSNlvsSfwu+Hi1stb1DddhLXlxWAgihvPMmRkUwtT908NQSOAO73TJ5U39d3g2wQu0cV1EH5DSycLa9nmGxI= ARC-Message-Signature: i=1; a=rsa-sha256; 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Wed, 08 Apr 2020 08:59:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39719) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jMAI6-0008VE-6t for qemu-devel@nongnu.org; Wed, 08 Apr 2020 08:58:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jMAI4-000578-D5 for qemu-devel@nongnu.org; Wed, 08 Apr 2020 08:58:49 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:3735 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jMAI4-00054k-1T for qemu-devel@nongnu.org; Wed, 08 Apr 2020 08:58:48 -0400 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id DB99FAAF32453AD37B68; Wed, 8 Apr 2020 20:58:39 +0800 (CST) Received: from DESKTOP-D7EVK5B.china.huawei.com (10.173.221.29) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.487.0; Wed, 8 Apr 2020 20:58:32 +0800 From: Yubo Miao To: , , Subject: [PATCH v6 2/8] fw_cfg: Write the extra roots into the fw_cfg Date: Wed, 8 Apr 2020 20:58:10 +0800 Message-ID: <20200408125816.955-3-miaoyubo@huawei.com> X-Mailer: git-send-email 2.24.1.windows.2 In-Reply-To: <20200408125816.955-1-miaoyubo@huawei.com> References: <20200408125816.955-1-miaoyubo@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.173.221.29] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.191 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: berrange@redhat.com, mst@redhat.com, qemu-devel@nongnu.org, xiexiangyou@huawei.com, miaoyubo@huawei.com, imammedo@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: miaoyubo Write the extra roots into the fw_cfg therefore the uefi could get the extra roots. Only if the uefi know there are extra roots, the config space of devices behind the root could be obtained. Signed-off-by: miaoyubo --- hw/arm/virt.c | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 7dc96abf72..0fdfe4129c 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -77,6 +77,7 @@ #include "hw/acpi/generic_event_device.h" #include "hw/virtio/virtio-iommu.h" #include "hw/char/pl011.h" +#include "hw/pci/pci_bus.h" =20 #define DEFINE_VIRT_MACHINE_LATEST(major, minor, latest) \ static void virt_##major##_##minor##_class_init(ObjectClass *oc, \ @@ -1435,6 +1436,12 @@ void virt_machine_done(Notifier *notifier, void *dat= a) ARMCPU *cpu =3D ARM_CPU(first_cpu); struct arm_boot_info *info =3D &vms->bootinfo; AddressSpace *as =3D arm_boot_address_space(cpu, info); + PCIHostState *s =3D OBJECT_CHECK(PCIHostState, + object_resolve_path_type("", + "pcie-host-bridge", NULL), + TYPE_PCI_HOST_BRIDGE); + + PCIBus *bus =3D s->bus; =20 /* * If the user provided a dtb, we assume the dynamic sysbus nodes @@ -1453,6 +1460,22 @@ void virt_machine_done(Notifier *notifier, void *dat= a) exit(1); } =20 + if (bus) { + int extra_hosts =3D 0; + QLIST_FOREACH(bus, &bus->child, sibling) { + /* look for expander root buses */ + if (pci_bus_is_root(bus)) { + extra_hosts++; + } + } + if (extra_hosts && vms->fw_cfg) { + uint64_t *val =3D g_malloc(sizeof(*val)); + *val =3D cpu_to_le64(extra_hosts); + fw_cfg_add_file(vms->fw_cfg, + "etc/extra-pci-roots", val, sizeof(*val)); + } + } + virt_acpi_setup(vms); virt_build_smbios(vms); } --=20 2.19.1 From nobody Fri May 10 08:50:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1586350802; cv=none; d=zohomail.com; s=zohoarc; b=c83pINtqgMOf+Pa/t0pBOH7SDV2wbKz25eO2ijVGTmzwDXcZMpqIQ7YI8ir70j3iepsSmg3/5xtgCmCGDkwBNPx+SRAgbFMme39Dtqz1PGh3MM9w3Ifmnb/pBPZqrvH2tl/yyv7tXTkfaymXigNAWRYwTLI2IgCIeVMkcMz5ON0= ARC-Message-Signature: i=1; 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Wed, 08 Apr 2020 09:00:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39777) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jMAI7-0008VR-7h for qemu-devel@nongnu.org; Wed, 08 Apr 2020 08:58:53 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jMAI4-00057N-Mq for qemu-devel@nongnu.org; Wed, 08 Apr 2020 08:58:51 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:3666 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jMAI4-00054h-1O for qemu-devel@nongnu.org; Wed, 08 Apr 2020 08:58:48 -0400 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 0F1E7D26D27C882CD86E; Wed, 8 Apr 2020 20:58:40 +0800 (CST) Received: from DESKTOP-D7EVK5B.china.huawei.com (10.173.221.29) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.487.0; Wed, 8 Apr 2020 20:58:33 +0800 From: Yubo Miao To: , , Subject: [PATCH v6 3/8] acpi: Extract crs build form acpi_build.c Date: Wed, 8 Apr 2020 20:58:11 +0800 Message-ID: <20200408125816.955-4-miaoyubo@huawei.com> X-Mailer: git-send-email 2.24.1.windows.2 In-Reply-To: <20200408125816.955-1-miaoyubo@huawei.com> References: <20200408125816.955-1-miaoyubo@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.173.221.29] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.190 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: berrange@redhat.com, mst@redhat.com, qemu-devel@nongnu.org, xiexiangyou@huawei.com, miaoyubo@huawei.com, imammedo@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: miaoyubo Extract crs build form acpi_build.c, the function could also be used to build the crs for pxbs for arm. The resources are composed by two parts: 1. The bar space of pci-bridge/pcie-root-ports 2. The resources devices behind PXBs need. The base and limit of memory/io are obtained from the config via two APIs: pci_bridge_get_base and pci_bridge_get_limit Signed-off-by: miaoyubo --- hw/acpi/aml-build.c | 275 ++++++++++++++++++++++++++++++++++ hw/i386/acpi-build.c | 285 ------------------------------------ include/hw/acpi/aml-build.h | 25 ++++ 3 files changed, 300 insertions(+), 285 deletions(-) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index 2c3702b882..252349d96d 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -26,6 +26,9 @@ #include "qemu/bitops.h" #include "sysemu/numa.h" #include "hw/boards.h" +#include "hw/pci/pci_host.h" +#include "hw/pci/pci_bus.h" +#include "hw/pci/pci_bridge.h" =20 static GArray *build_alloc_array(void) { @@ -54,6 +57,125 @@ static void build_append_array(GArray *array, GArray *v= al) =20 #define ACPI_NAMESEG_LEN 4 =20 +void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit) +{ + CrsRangeEntry *entry; + + entry =3D g_malloc(sizeof(*entry)); + entry->base =3D base; + entry->limit =3D limit; + + g_ptr_array_add(ranges, entry); +} + +static void crs_range_free(gpointer data) +{ + CrsRangeEntry *entry =3D (CrsRangeEntry *)data; + g_free(entry); +} + +void crs_range_set_init(CrsRangeSet *range_set) +{ + range_set->io_ranges =3D g_ptr_array_new_with_free_func(crs_range_free= ); + range_set->mem_ranges =3D g_ptr_array_new_with_free_func(crs_range_fre= e); + range_set->mem_64bit_ranges =3D + g_ptr_array_new_with_free_func(crs_range_free); +} + +void crs_range_set_free(CrsRangeSet *range_set) +{ + g_ptr_array_free(range_set->io_ranges, true); + g_ptr_array_free(range_set->mem_ranges, true); + g_ptr_array_free(range_set->mem_64bit_ranges, true); +} + +static gint crs_range_compare(gconstpointer a, gconstpointer b) +{ + CrsRangeEntry *entry_a =3D *(CrsRangeEntry **)a; + CrsRangeEntry *entry_b =3D *(CrsRangeEntry **)b; + + if (entry_a->base < entry_b->base) { + return -1; + } else if (entry_a->base > entry_b->base) { + return 1; + } else { + return 0; + } +} + +/* + * crs_replace_with_free_ranges - given the 'used' ranges within [start - = end] + * interval, computes the 'free' ranges from the same interval. + * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function + * will return { [base - a1], [a2 - b1], [b2 - limit] }. + */ +void crs_replace_with_free_ranges(GPtrArray *ranges, + uint64_t start, uint64_t end) +{ + GPtrArray *free_ranges =3D g_ptr_array_new(); + uint64_t free_base =3D start; + int i; + + g_ptr_array_sort(ranges, crs_range_compare); + for (i =3D 0; i < ranges->len; i++) { + CrsRangeEntry *used =3D g_ptr_array_index(ranges, i); + + if (free_base < used->base) { + crs_range_insert(free_ranges, free_base, used->base - 1); + } + + free_base =3D used->limit + 1; + } + + if (free_base < end) { + crs_range_insert(free_ranges, free_base, end); + } + + g_ptr_array_set_size(ranges, 0); + for (i =3D 0; i < free_ranges->len; i++) { + g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i)); + } + + g_ptr_array_free(free_ranges, true); +} + +static void crs_range_merge(GPtrArray *range) +{ + GPtrArray *tmp =3D g_ptr_array_new_with_free_func(crs_range_free); + CrsRangeEntry *entry; + uint64_t range_base, range_limit; + int i; + + if (!range->len) { + return; + } + + g_ptr_array_sort(range, crs_range_compare); + + entry =3D g_ptr_array_index(range, 0); + range_base =3D entry->base; + range_limit =3D entry->limit; + for (i =3D 1; i < range->len; i++) { + entry =3D g_ptr_array_index(range, i); + if (entry->base - 1 =3D=3D range_limit) { + range_limit =3D entry->limit; + } else { + crs_range_insert(tmp, range_base, range_limit); + range_base =3D entry->base; + range_limit =3D entry->limit; + } + } + crs_range_insert(tmp, range_base, range_limit); + + g_ptr_array_set_size(range, 0); + for (i =3D 0; i < tmp->len; i++) { + entry =3D g_ptr_array_index(tmp, i); + crs_range_insert(range, entry->base, entry->limit); + } + g_ptr_array_free(tmp, true); +} + + static void build_append_nameseg(GArray *array, const char *seg) { @@ -1875,6 +1997,159 @@ build_hdr: "FACP", tbl->len - fadt_start, f->rev, oem_id, oem_table_= id); } =20 +Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set) +{ + Aml *crs =3D aml_resource_template(); + CrsRangeSet temp_range_set; + CrsRangeEntry *entry; + uint8_t max_bus =3D pci_bus_num(host->bus); + uint8_t type; + int devfn; + int i; + + crs_range_set_init(&temp_range_set); + for (devfn =3D 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) { + uint64_t range_base, range_limit; + PCIDevice *dev =3D host->bus->devices[devfn]; + + if (!dev) { + continue; + } + + for (i =3D 0; i < PCI_NUM_REGIONS; i++) { + PCIIORegion *r =3D &dev->io_regions[i]; + + range_base =3D r->addr; + range_limit =3D r->addr + r->size - 1; + + /* + * Work-around for old bioses + * that do not support multiple root buses + */ + if (!range_base || range_base > range_limit) { + continue; + } + + if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { + crs_range_insert(temp_range_set.io_ranges, + range_base, range_limit); + } else { /* "memory" */ + crs_range_insert(temp_range_set.mem_ranges, + range_base, range_limit); + } + } + + type =3D dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUN= CTION; + if (type =3D=3D PCI_HEADER_TYPE_BRIDGE) { + uint8_t subordinate =3D dev->config[PCI_SUBORDINATE_BUS]; + if (subordinate > max_bus) { + max_bus =3D subordinate; + } + + range_base =3D pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE= _IO); + range_limit =3D pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPA= CE_IO); + /* + * Work-around for old bioses + * that do not support multiple root buses + */ + if (range_base && range_base <=3D range_limit) { + crs_range_insert(temp_range_set.io_ranges, + range_base, range_limit); + } + + range_base =3D + pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); + range_limit =3D + pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); + + /* + * Work-around for old bioses + * that do not support multiple root buses + */ + if (range_base && range_base <=3D range_limit) { + uint64_t length =3D range_limit - range_base + 1; + if (range_limit <=3D UINT32_MAX && length <=3D UINT32_MAX)= { + crs_range_insert(temp_range_set.mem_ranges, + range_base, range_limit); + } else { + crs_range_insert(temp_range_set.mem_64bit_ranges, + range_base, range_limit); + } + } + + range_base =3D + pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); + range_limit =3D + pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); + + /* + * Work-around for old bioses + * that do not support multiple root buses + */ + if (range_base && range_base <=3D range_limit) { + uint64_t length =3D range_limit - range_base + 1; + if (range_limit <=3D UINT32_MAX && length <=3D UINT32_MAX)= { + crs_range_insert(temp_range_set.mem_ranges, + range_base, range_limit); + } else { + crs_range_insert(temp_range_set.mem_64bit_ranges, + range_base, range_limit); + } + } + } + } + + crs_range_merge(temp_range_set.io_ranges); + for (i =3D 0; i < temp_range_set.io_ranges->len; i++) { + entry =3D g_ptr_array_index(temp_range_set.io_ranges, i); + aml_append(crs, + aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, + AML_POS_DECODE, AML_ENTIRE_RANGE, + 0, entry->base, entry->limit, 0, + entry->limit - entry->base + 1)); + crs_range_insert(range_set->io_ranges, entry->base, entry->limit); + } + + crs_range_merge(temp_range_set.mem_ranges); + for (i =3D 0; i < temp_range_set.mem_ranges->len; i++) { + entry =3D g_ptr_array_index(temp_range_set.mem_ranges, i); + aml_append(crs, + aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, + AML_MAX_FIXED, AML_NON_CACHEABLE, + AML_READ_WRITE, + 0, entry->base, entry->limit, 0, + entry->limit - entry->base + 1)); + crs_range_insert(range_set->mem_ranges, entry->base, entry->limit); + } + + crs_range_merge(temp_range_set.mem_64bit_ranges); + for (i =3D 0; i < temp_range_set.mem_64bit_ranges->len; i++) { + entry =3D g_ptr_array_index(temp_range_set.mem_64bit_ranges, i); + aml_append(crs, + aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, + AML_MAX_FIXED, AML_NON_CACHEABLE, + AML_READ_WRITE, + 0, entry->base, entry->limit, 0, + entry->limit - entry->base + 1)); + crs_range_insert(range_set->mem_64bit_ranges, + entry->base, entry->limit); + } + + crs_range_set_free(&temp_range_set); + + aml_append(crs, + aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, + 0, + pci_bus_num(host->bus), + max_bus, + 0, + max_bus - pci_bus_num(host->bus) + 1)); + + return crs; +} + + + /* ACPI 5.0: 6.4.3.8.2 Serial Bus Connection Descriptors */ static Aml *aml_serial_bus_device(uint8_t serial_bus_type, uint8_t flags, uint16_t type_flags, diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 2a7e55bae7..ba7750480f 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -715,291 +715,6 @@ static Aml *build_prt(bool is_pci0_prt) return method; } =20 -typedef struct CrsRangeEntry { - uint64_t base; - uint64_t limit; -} CrsRangeEntry; - -static void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t li= mit) -{ - CrsRangeEntry *entry; - - entry =3D g_malloc(sizeof(*entry)); - entry->base =3D base; - entry->limit =3D limit; - - g_ptr_array_add(ranges, entry); -} - -static void crs_range_free(gpointer data) -{ - CrsRangeEntry *entry =3D (CrsRangeEntry *)data; - g_free(entry); -} - -typedef struct CrsRangeSet { - GPtrArray *io_ranges; - GPtrArray *mem_ranges; - GPtrArray *mem_64bit_ranges; - } CrsRangeSet; - -static void crs_range_set_init(CrsRangeSet *range_set) -{ - range_set->io_ranges =3D g_ptr_array_new_with_free_func(crs_range_free= ); - range_set->mem_ranges =3D g_ptr_array_new_with_free_func(crs_range_fre= e); - range_set->mem_64bit_ranges =3D - g_ptr_array_new_with_free_func(crs_range_free); -} - -static void crs_range_set_free(CrsRangeSet *range_set) -{ - g_ptr_array_free(range_set->io_ranges, true); - g_ptr_array_free(range_set->mem_ranges, true); - g_ptr_array_free(range_set->mem_64bit_ranges, true); -} - -static gint crs_range_compare(gconstpointer a, gconstpointer b) -{ - CrsRangeEntry *entry_a =3D *(CrsRangeEntry **)a; - CrsRangeEntry *entry_b =3D *(CrsRangeEntry **)b; - - if (entry_a->base < entry_b->base) { - return -1; - } else if (entry_a->base > entry_b->base) { - return 1; - } else { - return 0; - } -} - -/* - * crs_replace_with_free_ranges - given the 'used' ranges within [start - = end] - * interval, computes the 'free' ranges from the same interval. - * Example: If the input array is { [a1 - a2],[b1 - b2] }, the function - * will return { [base - a1], [a2 - b1], [b2 - limit] }. - */ -static void crs_replace_with_free_ranges(GPtrArray *ranges, - uint64_t start, uint64_t end) -{ - GPtrArray *free_ranges =3D g_ptr_array_new(); - uint64_t free_base =3D start; - int i; - - g_ptr_array_sort(ranges, crs_range_compare); - for (i =3D 0; i < ranges->len; i++) { - CrsRangeEntry *used =3D g_ptr_array_index(ranges, i); - - if (free_base < used->base) { - crs_range_insert(free_ranges, free_base, used->base - 1); - } - - free_base =3D used->limit + 1; - } - - if (free_base < end) { - crs_range_insert(free_ranges, free_base, end); - } - - g_ptr_array_set_size(ranges, 0); - for (i =3D 0; i < free_ranges->len; i++) { - g_ptr_array_add(ranges, g_ptr_array_index(free_ranges, i)); - } - - g_ptr_array_free(free_ranges, true); -} - -/* - * crs_range_merge - merges adjacent ranges in the given array. - * Array elements are deleted and replaced with the merged ranges. - */ -static void crs_range_merge(GPtrArray *range) -{ - GPtrArray *tmp =3D g_ptr_array_new_with_free_func(crs_range_free); - CrsRangeEntry *entry; - uint64_t range_base, range_limit; - int i; - - if (!range->len) { - return; - } - - g_ptr_array_sort(range, crs_range_compare); - - entry =3D g_ptr_array_index(range, 0); - range_base =3D entry->base; - range_limit =3D entry->limit; - for (i =3D 1; i < range->len; i++) { - entry =3D g_ptr_array_index(range, i); - if (entry->base - 1 =3D=3D range_limit) { - range_limit =3D entry->limit; - } else { - crs_range_insert(tmp, range_base, range_limit); - range_base =3D entry->base; - range_limit =3D entry->limit; - } - } - crs_range_insert(tmp, range_base, range_limit); - - g_ptr_array_set_size(range, 0); - for (i =3D 0; i < tmp->len; i++) { - entry =3D g_ptr_array_index(tmp, i); - crs_range_insert(range, entry->base, entry->limit); - } - g_ptr_array_free(tmp, true); -} - -static Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set) -{ - Aml *crs =3D aml_resource_template(); - CrsRangeSet temp_range_set; - CrsRangeEntry *entry; - uint8_t max_bus =3D pci_bus_num(host->bus); - uint8_t type; - int devfn; - int i; - - crs_range_set_init(&temp_range_set); - for (devfn =3D 0; devfn < ARRAY_SIZE(host->bus->devices); devfn++) { - uint64_t range_base, range_limit; - PCIDevice *dev =3D host->bus->devices[devfn]; - - if (!dev) { - continue; - } - - for (i =3D 0; i < PCI_NUM_REGIONS; i++) { - PCIIORegion *r =3D &dev->io_regions[i]; - - range_base =3D r->addr; - range_limit =3D r->addr + r->size - 1; - - /* - * Work-around for old bioses - * that do not support multiple root buses - */ - if (!range_base || range_base > range_limit) { - continue; - } - - if (r->type & PCI_BASE_ADDRESS_SPACE_IO) { - crs_range_insert(temp_range_set.io_ranges, - range_base, range_limit); - } else { /* "memory" */ - crs_range_insert(temp_range_set.mem_ranges, - range_base, range_limit); - } - } - - type =3D dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUN= CTION; - if (type =3D=3D PCI_HEADER_TYPE_BRIDGE) { - uint8_t subordinate =3D dev->config[PCI_SUBORDINATE_BUS]; - if (subordinate > max_bus) { - max_bus =3D subordinate; - } - - range_base =3D pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE= _IO); - range_limit =3D pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPA= CE_IO); - - /* - * Work-around for old bioses - * that do not support multiple root buses - */ - if (range_base && range_base <=3D range_limit) { - crs_range_insert(temp_range_set.io_ranges, - range_base, range_limit); - } - - range_base =3D - pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); - range_limit =3D - pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY); - - /* - * Work-around for old bioses - * that do not support multiple root buses - */ - if (range_base && range_base <=3D range_limit) { - uint64_t length =3D range_limit - range_base + 1; - if (range_limit <=3D UINT32_MAX && length <=3D UINT32_MAX)= { - crs_range_insert(temp_range_set.mem_ranges, - range_base, range_limit); - } else { - crs_range_insert(temp_range_set.mem_64bit_ranges, - range_base, range_limit); - } - } - - range_base =3D - pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); - range_limit =3D - pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH); - - /* - * Work-around for old bioses - * that do not support multiple root buses - */ - if (range_base && range_base <=3D range_limit) { - uint64_t length =3D range_limit - range_base + 1; - if (range_limit <=3D UINT32_MAX && length <=3D UINT32_MAX)= { - crs_range_insert(temp_range_set.mem_ranges, - range_base, range_limit); - } else { - crs_range_insert(temp_range_set.mem_64bit_ranges, - range_base, range_limit); - } - } - } - } - - crs_range_merge(temp_range_set.io_ranges); - for (i =3D 0; i < temp_range_set.io_ranges->len; i++) { - entry =3D g_ptr_array_index(temp_range_set.io_ranges, i); - aml_append(crs, - aml_word_io(AML_MIN_FIXED, AML_MAX_FIXED, - AML_POS_DECODE, AML_ENTIRE_RANGE, - 0, entry->base, entry->limit, 0, - entry->limit - entry->base + 1)); - crs_range_insert(range_set->io_ranges, entry->base, entry->limit); - } - - crs_range_merge(temp_range_set.mem_ranges); - for (i =3D 0; i < temp_range_set.mem_ranges->len; i++) { - entry =3D g_ptr_array_index(temp_range_set.mem_ranges, i); - aml_append(crs, - aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, - AML_MAX_FIXED, AML_NON_CACHEABLE, - AML_READ_WRITE, - 0, entry->base, entry->limit, 0, - entry->limit - entry->base + 1)); - crs_range_insert(range_set->mem_ranges, entry->base, entry->limit); - } - - crs_range_merge(temp_range_set.mem_64bit_ranges); - for (i =3D 0; i < temp_range_set.mem_64bit_ranges->len; i++) { - entry =3D g_ptr_array_index(temp_range_set.mem_64bit_ranges, i); - aml_append(crs, - aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, - AML_MAX_FIXED, AML_NON_CACHEABLE, - AML_READ_WRITE, - 0, entry->base, entry->limit, 0, - entry->limit - entry->base + 1)); - crs_range_insert(range_set->mem_64bit_ranges, - entry->base, entry->limit); - } - - crs_range_set_free(&temp_range_set); - - aml_append(crs, - aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, - 0, - pci_bus_num(host->bus), - max_bus, - 0, - max_bus - pci_bus_num(host->bus) + 1)); - - return crs; -} - static void build_hpet_aml(Aml *table) { Aml *crs; diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index de4a406568..2894825ffb 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -223,6 +223,20 @@ struct AcpiBuildTables { BIOSLinker *linker; } AcpiBuildTables; =20 +typedef +struct CrsRangeEntry { + uint64_t base; + uint64_t limit; +} CrsRangeEntry; + +typedef +struct CrsRangeSet { + GPtrArray *io_ranges; + GPtrArray *mem_ranges; + GPtrArray *mem_64bit_ranges; +} CrsRangeSet; + + /* * ACPI 5.0: 6.4.3.8.2 Serial Bus Connection Descriptors * Serial Bus Type @@ -429,6 +443,17 @@ build_append_gas_from_struct(GArray *table, const stru= ct AcpiGenericAddress *s) s->access_width, s->address); } =20 +Aml *build_crs(PCIHostState *host, CrsRangeSet *range_set); + +void crs_range_insert(GPtrArray *ranges, uint64_t base, uint64_t limit); + +void crs_replace_with_free_ranges(GPtrArray *ranges, + uint64_t start, uint64_t end); + +void crs_range_set_init(CrsRangeSet *range_set); + +void crs_range_set_free(CrsRangeSet *range_set); + void build_srat_memory(AcpiSratMemoryAffinity *numamem, uint64_t base, uint64_t len, int node, MemoryAffinityFlags flags); =20 --=20 2.19.1 From nobody Fri May 10 08:50:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1586350954; cv=none; d=zohomail.com; s=zohoarc; b=fhpV2jfkaC2YsRaO/gCwZQ2XMli9jWxicG4en2oFlh1LQWYCrgx8lxe1p7LWM5mEd51R0IjEAMw/wxxq6QN8X4MmTpkuOI5jDD4BCgOghABLEqMrtKlpQPip8DHUEFxXZFpKHrWyboWnQ9/pYFq1EcNIwB1jNAwF+2o8KPp0+G8= ARC-Message-Signature: i=1; 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Wed, 08 Apr 2020 09:02:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39791) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jMAI7-0008VZ-HQ for qemu-devel@nongnu.org; Wed, 08 Apr 2020 08:58:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jMAI5-000581-FF for qemu-devel@nongnu.org; Wed, 08 Apr 2020 08:58:51 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:36628 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jMAI4-00056S-R1 for qemu-devel@nongnu.org; Wed, 08 Apr 2020 08:58:49 -0400 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id F2A2BC2A177341006499; Wed, 8 Apr 2020 20:58:44 +0800 (CST) Received: from DESKTOP-D7EVK5B.china.huawei.com (10.173.221.29) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.487.0; Wed, 8 Apr 2020 20:58:34 +0800 From: Yubo Miao To: , , Subject: [PATCH v6 4/8] acpi: Refactor the source of host bridge and build tables for pxb Date: Wed, 8 Apr 2020 20:58:12 +0800 Message-ID: <20200408125816.955-5-miaoyubo@huawei.com> X-Mailer: git-send-email 2.24.1.windows.2 In-Reply-To: <20200408125816.955-1-miaoyubo@huawei.com> References: <20200408125816.955-1-miaoyubo@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.173.221.29] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: berrange@redhat.com, mst@redhat.com, qemu-devel@nongnu.org, xiexiangyou@huawei.com, miaoyubo@huawei.com, imammedo@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: miaoyubo The resources of pxbs and obtained by crs_build and the resources used by pxbs would be moved form the resources defined for host-bridge. The resources for pxb are composed of the bar space of the pci-bridge/pcie-root-port behined it and the config space of devices behind it. Signed-off-by: miaoyubo --- hw/arm/virt-acpi-build.c | 131 +++++++++++++++++++++++++++++++++------ 1 file changed, 111 insertions(+), 20 deletions(-) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index e8ba09855c..7bcd04dfb7 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -49,6 +49,9 @@ #include "kvm_arm.h" #include "migration/vmstate.h" =20 +#include "hw/arm/virt.h" +#include "hw/pci/pci_bus.h" +#include "hw/pci/pci_bridge.h" #define ARM_SPI_BASE 32 =20 static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus) @@ -266,19 +269,81 @@ static void acpi_dsdt_add_pci_osc(Aml *dev, Aml *scop= e) } =20 static void acpi_dsdt_add_pci(Aml *scope, const MemMapEntry *memmap, - uint32_t irq, bool use_highmem, bool highmem= _ecam) + uint32_t irq, bool use_highmem, bool highmem= _ecam, + VirtMachineState *vms) { int ecam_id =3D VIRT_ECAM_ID(highmem_ecam); - Aml *method, *crs; + int i; + Aml *method, *crs, *dev; hwaddr base_mmio =3D memmap[VIRT_PCIE_MMIO].base; hwaddr size_mmio =3D memmap[VIRT_PCIE_MMIO].size; hwaddr base_pio =3D memmap[VIRT_PCIE_PIO].base; hwaddr size_pio =3D memmap[VIRT_PCIE_PIO].size; hwaddr base_ecam =3D memmap[ecam_id].base; hwaddr size_ecam =3D memmap[ecam_id].size; + CrsRangeEntry *entry; + CrsRangeSet crs_range_set; + + crs_range_set_init(&crs_range_set); int nr_pcie_buses =3D size_ecam / PCIE_MMCFG_SIZE_MIN; + PCIHostState *s =3D OBJECT_CHECK(PCIHostState, + object_resolve_path_type("", + "pcie-host-bridge", NULL), + TYPE_PCI_HOST_BRIDGE); + + PCIBus *bus =3D s->bus; + /* start to construct the tables for pxb*/ + if (bus) { + QLIST_FOREACH(bus, &bus->child, sibling) { + uint8_t bus_num =3D pci_bus_num(bus); + uint8_t numa_node =3D pci_bus_numa_node(bus); + + if (!pci_bus_is_root(bus)) { + continue; + } + /* + * Coded up the MIN of the busNr defined for pxb-pcie, + * the MIN - 1 would be the MAX bus number for the main + * host bridge. + */ + if (bus_num < nr_pcie_buses) { + nr_pcie_buses =3D bus_num; + } + + dev =3D aml_device("PC%.02X", bus_num); + aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); + aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); + aml_append(dev, aml_name_decl("_ADR", aml_int(0))); + aml_append(dev, aml_name_decl("_CCA", aml_int(1))); + aml_append(dev, aml_name_decl("_SEG", aml_int(0))); + aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); + aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); + aml_append(dev, aml_name_decl("_STR", aml_unicode("pxb Device"= ))); + if (numa_node !=3D NUMA_NODE_UNASSIGNED) { + method =3D aml_method("_PXM", 0, AML_NOTSERIALIZED); + aml_append(method, aml_return(aml_int(numa_node))); + aml_append(dev, method); + } + + acpi_dsdt_add_pci_route_table(dev, scope, irq); + + /* + * Resources deined for PXBs are composed by the folling parts: + * 1. The resources the pci-brige/pcie-root-port need. + * 2. The resources the devices behind pxb need. + */ + crs =3D build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_rang= e_set); + aml_append(dev, aml_name_decl("_CRS", crs)); + + acpi_dsdt_add_pci_osc(dev, scope); + + aml_append(scope, dev); + + } + } =20 - Aml *dev =3D aml_device("%s", "PCI0"); + /* start to construct the tables for main host bridge */ + dev =3D aml_device("%s", "PCI0"); aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); aml_append(dev, aml_name_decl("_SEG", aml_int(0))); @@ -299,25 +364,51 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMa= pEntry *memmap, aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, nr_pcie_buses)); - aml_append(rbuf, - aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, - AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, base_m= mio, - base_mmio + size_mmio - 1, 0x0000, size_mmio)); - aml_append(rbuf, - aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, - AML_ENTIRE_RANGE, 0x0000, 0x0000, size_pio - 1, base_= pio, - size_pio)); + + /* + * Remove the resources used by PXBs. + */ + crs_replace_with_free_ranges(crs_range_set.mem_ranges, + base_mmio, + base_mmio + size_mmio - 1); + for (i =3D 0; i < crs_range_set.mem_ranges->len; i++) { + entry =3D g_ptr_array_index(crs_range_set.mem_ranges, i); + aml_append(rbuf, + aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, + AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, + entry->base, entry->limit, + 0x0000, entry->limit - entry->base + 1)); + } + + crs_replace_with_free_ranges(crs_range_set.io_ranges, + 0x0000, + size_pio - 1); + for (i =3D 0; i < crs_range_set.io_ranges->len; i++) { + entry =3D g_ptr_array_index(crs_range_set.io_ranges, i); + aml_append(rbuf, + aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, + AML_ENTIRE_RANGE, 0x0000, entry->base, + entry->limit, base_pio, + entry->limit - entry->base + 1)); + } + =20 if (use_highmem) { hwaddr base_mmio_high =3D memmap[VIRT_HIGH_PCIE_MMIO].base; hwaddr size_mmio_high =3D memmap[VIRT_HIGH_PCIE_MMIO].size; =20 - aml_append(rbuf, - aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, - AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, - base_mmio_high, - base_mmio_high + size_mmio_high - 1, 0x0000, - size_mmio_high)); + crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, + base_mmio_high, + base_mmio_high + size_mmio_high - 1); + for (i =3D 0; i < crs_range_set.mem_64bit_ranges->len; i++) { + entry =3D g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); + aml_append(rbuf, + aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FI= XED, + AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, + entry->base, + entry->limit, 0x0000, + entry->limit - entry->base + 1)); + } } =20 aml_append(method, aml_return(rbuf)); @@ -335,6 +426,8 @@ static void acpi_dsdt_add_pci(Aml *scope, const MemMapE= ntry *memmap, aml_append(dev_res0, aml_name_decl("_CRS", crs)); aml_append(dev, dev_res0); aml_append(scope, dev); + + crs_range_set_free(&crs_range_set); } =20 static void acpi_dsdt_add_gpio(Aml *scope, const MemMapEntry *gpio_memmap, @@ -746,7 +839,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, Virt= MachineState *vms) acpi_dsdt_add_virtio(scope, &memmap[VIRT_MMIO], (irqmap[VIRT_MMIO] + ARM_SPI_BASE), NUM_VIRTIO_TRANSPO= RTS); acpi_dsdt_add_pci(scope, memmap, (irqmap[VIRT_PCIE] + ARM_SPI_BASE), - vms->highmem, vms->highmem_ecam); + vms->highmem, vms->highmem_ecam, vms); if (vms->acpi_dev) { build_ged_aml(scope, "\\_SB."GED_DEVICE, HOTPLUG_HANDLER(vms->acpi_dev), @@ -798,7 +891,6 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildTa= bles *tables) unsigned dsdt, xsdt; GArray *tables_blob =3D tables->table_data; MachineState *ms =3D MACHINE(vms); - table_offsets =3D g_array_new(false, true /* clear */, sizeof(uint32_t)); =20 @@ -952,7 +1044,6 @@ void virt_acpi_setup(VirtMachineState *vms) build_state->rsdp_mr =3D acpi_add_rom_blob(virt_acpi_build_update, build_state, tables.rsdp, ACPI_BUILD_RSDP_FILE, 0); - qemu_register_reset(virt_acpi_build_reset, build_state); virt_acpi_build_reset(build_state); vmstate_register(NULL, 0, &vmstate_virt_acpi_build, build_state); --=20 2.19.1 From nobody Fri May 10 08:50:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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charset="utf-8" From: miaoyubo If table size is changed between virt_acpi_build and virt_acpi_build_update, the table size would not be updated to UEFI, therefore, just align the size to 128kb, which is enough and same with x86. It would warn if 64k is not enough and the align size should be updated. Signed-off-by: miaoyubo --- hw/arm/virt-acpi-build.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 7bcd04dfb7..89bb768b0c 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -54,6 +54,8 @@ #include "hw/pci/pci_bridge.h" #define ARM_SPI_BASE 32 =20 +#define ACPI_BUILD_TABLE_SIZE 0x20000 + static void acpi_dsdt_add_cpus(Aml *scope, int smp_cpus) { uint16_t i; @@ -883,6 +885,15 @@ struct AcpiBuildState { bool patched; } AcpiBuildState; =20 +static void acpi_align_size(GArray *blob, unsigned align) +{ + /* + * Align size to multiple of given size. This reduces the chance + * we need to change size in the future (breaking cross version migrat= ion). + */ + g_array_set_size(blob, ROUND_UP(acpi_data_len(blob), align)); +} + static void virt_acpi_build(VirtMachineState *vms, AcpiBuildTables *tables) { @@ -953,6 +964,20 @@ void virt_acpi_build(VirtMachineState *vms, AcpiBuildT= ables *tables) build_rsdp(tables->rsdp, tables->linker, &rsdp_data); } =20 + /* + * The align size is 128, warn if 64k is not enough therefore + * the align size could be resized. + */ + if (tables_blob->len > ACPI_BUILD_TABLE_SIZE / 2) { + warn_report("ACPI table size %u exceeds %d bytes," + " migration may not work", + tables_blob->len, ACPI_BUILD_TABLE_SIZE / 2); + error_printf("Try removing CPUs, NUMA nodes, memory slots" + " or PCI bridges."); + } + acpi_align_size(tables_blob, ACPI_BUILD_TABLE_SIZE); + + /* Cleanup memory that's no longer used. */ g_array_free(table_offsets, true); } --=20 2.19.1 From nobody Fri May 10 08:50:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1586350798; cv=none; d=zohomail.com; s=zohoarc; b=nJE3ff/IiT7Q/5PQCCH8KSrRtGMWFj0OoD9j+At09mgbAuaxCIr8TUuEGwBNEDn0YSmmuzT/Md8cN1z0UW3hOz32xenkJ4c/yLBq+9H6I/PBqkzl4kq6WxPvIXBCNlCV7JZu9zWJHyP5UMsfYzv2GORgo7gPSU3uc5/hK/Amv7w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1586350798; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ZVjPjxKTY6hGkQrIUi4APIXWL9ziuOhWIKTeVxy5PyM=; b=kmc94Qz7N9XJOTcL1SHjwPktO+s62ojitUvX9OP8Tb6w+vhTompa5BLm9dcRWVko0EQRueDBWe1lqtX7WzFnw2q878za82Cf0fMcLHjyE9+JYuDlhKJD42/WY90okgzFk6CRhWvLo4FD/yLatXs4ZVuIUCfAU5pnnmwaj0rOe4s= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1586350798832876.4512459586743; Wed, 8 Apr 2020 05:59:58 -0700 (PDT) Received: from localhost ([::1]:35702 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jMAJB-0001gC-5F for importer@patchew.org; Wed, 08 Apr 2020 08:59:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39749) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jMAI6-0008VI-Mo for qemu-devel@nongnu.org; Wed, 08 Apr 2020 08:58:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jMAI5-00057n-5i for qemu-devel@nongnu.org; Wed, 08 Apr 2020 08:58:50 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:36626 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jMAI4-00056R-Ei for qemu-devel@nongnu.org; Wed, 08 Apr 2020 08:58:49 -0400 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id E71CBAE3E4A40088D63C; Wed, 8 Apr 2020 20:58:44 +0800 (CST) Received: from DESKTOP-D7EVK5B.china.huawei.com (10.173.221.29) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.487.0; Wed, 8 Apr 2020 20:58:35 +0800 From: Yubo Miao To: , , Subject: [PATCH v6 6/8] unit-test: The files changed. Date: Wed, 8 Apr 2020 20:58:14 +0800 Message-ID: <20200408125816.955-7-miaoyubo@huawei.com> X-Mailer: git-send-email 2.24.1.windows.2 In-Reply-To: <20200408125816.955-1-miaoyubo@huawei.com> References: <20200408125816.955-1-miaoyubo@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.173.221.29] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: berrange@redhat.com, mst@redhat.com, qemu-devel@nongnu.org, xiexiangyou@huawei.com, miaoyubo@huawei.com, imammedo@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: miaoyubo The unit-test is seperated into three patches: 1. The files changed and list in bios-tables-test-allowed-diff.h 2. The unit-test 3. The binary file and clear bios-tables-test-allowed-diff.h The ASL diff would also be listed. Sice there are 1000+lines diff, some changes would be omitted. * Original Table Header: * Signature "DSDT" - * Length 0x000014BB (5307) + * Length 0x00001E7A (7802) * Revision 0x02 - * Checksum 0xD1 + * Checksum 0x57 * OEM ID "BOCHS " * OEM Table ID "BXPCDSDT" * OEM Revision 0x00000001 (1) + Device (PC80) + { + Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardwar= e ID + Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID + Name (_ADR, Zero) // _ADR: Address + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_SEG, Zero) // _SEG: PCI Segment + Name (_BBN, 0x80) // _BBN: BIOS Bus Number + Name (_UID, 0x80) // _UID: Unique ID + Name (_STR, Unicode ("pxb Device")) // _STR: Description Stri= ng + Name (_PRT, Package (0x80) // _PRT: PCI Routing Table + { + Package (0x04) + { + 0xFFFF, + Zero, + GSI0, + Zero + }, + Packages are omitted. + Package (0x04) + { + 0x001FFFFF, + 0x03, + GSI2, + Zero + } + }) + Device (GSI0) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) //= _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resourc= e Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclus= ive, ,, ) + { + 0x00000023, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource= Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclus= ive, ,, ) + { + 0x00000023, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Set= tings + { + } + } GSI1,2,3 are omitted. + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Set= tings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDe= code, + 0x0000, // Granularity + 0x0080, // Range Minimum + 0x0080, // Range Maximum + 0x0000, // Translation Offset + 0x0001, // Length + ,, ) + }) + Name (SUPP, Zero) + Name (CTRL, Zero) + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Cap= abilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 =3D=3D ToUUID ("33db4d5b-1ff7-401c-9657-7441c03d= d766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + SUPP =3D CDW2 /* \_SB_.PC80._OSC.CDW2 */ + CTRL =3D CDW3 /* \_SB_.PC80._OSC.CDW3 */ + CTRL &=3D 0x1F + If ((Arg1 !=3D One)) + { + CDW1 |=3D 0x08 + } + + If ((CDW3 !=3D CTRL)) + { + CDW1 |=3D 0x10 + } + + CDW3 =3D CTRL /* \_SB_.PC80.CTRL */ + Return (Arg3) + } + Else + { + CDW1 |=3D 0x04 + Return (Arg3) + } + } DSM is are omitted Device (PCI0) { Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardwar= e ID WordBusNumber (ResourceProducer, MinFixed, MaxFixed, P= osDecode, 0x0000, // Granularity 0x0000, // Range Minimum - 0x00FF, // Range Maximum + 0x007F, // Range Maximum 0x0000, // Translation Offset - 0x0100, // Length + 0x0080, // Length Signed-off-by: miaoyubo --- tests/qtest/bios-tables-test-allowed-diff.h | 1 + 1 file changed, 1 insertion(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8b..90c53925fc 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,2 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/virt/DSDT.pxb", --=20 2.19.1 From nobody Fri May 10 08:50:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Wed, 08 Apr 2020 08:58:50 -0400 Received: from DGGEMS402-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id E17F99C76415CB7F967B; Wed, 8 Apr 2020 20:58:44 +0800 (CST) Received: from DESKTOP-D7EVK5B.china.huawei.com (10.173.221.29) by DGGEMS402-HUB.china.huawei.com (10.3.19.202) with Microsoft SMTP Server id 14.3.487.0; Wed, 8 Apr 2020 20:58:36 +0800 From: Yubo Miao To: , , Subject: [PATCH v6 7/8] unit-test: Add testcase for pxb Date: Wed, 8 Apr 2020 20:58:15 +0800 Message-ID: <20200408125816.955-8-miaoyubo@huawei.com> X-Mailer: git-send-email 2.24.1.windows.2 In-Reply-To: <20200408125816.955-1-miaoyubo@huawei.com> References: <20200408125816.955-1-miaoyubo@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.173.221.29] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: berrange@redhat.com, mst@redhat.com, qemu-devel@nongnu.org, xiexiangyou@huawei.com, miaoyubo@huawei.com, imammedo@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: miaoyubo Add testcase for pxb to make sure the ACPI table is correct for guest. Signed-off-by: miaoyubo --- tests/qtest/bios-tables-test.c | 58 ++++++++++++++++++++++++++++++---- 1 file changed, 52 insertions(+), 6 deletions(-) diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index 0a597bbacf..4bba680917 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -621,12 +621,21 @@ static void test_acpi_one(const char *params, test_da= ta *data) * TODO: convert '-drive if=3Dpflash' to new syntax (see e33763be7= cd3) * when arm/virt boad starts to support it. */ - args =3D g_strdup_printf("-machine %s %s -accel tcg -nodefaults -n= ographic " - "-drive if=3Dpflash,format=3Draw,file=3D%s,readonly " - "-drive if=3Dpflash,format=3Draw,file=3D%s,snapshot=3Don -cdro= m %s %s", - data->machine, data->tcg_only ? "" : "-accel kvm", - data->uefi_fl1, data->uefi_fl2, data->cd, params ? params : ""= ); - + if (data->cd) { + args =3D g_strdup_printf("-machine %s %s -accel tcg " + "-nodefaults -nographic " + "-drive if=3Dpflash,format=3Draw,file=3D%s,readonly " + "-drive if=3Dpflash,format=3Draw,file=3D%s,snapshot=3Don -= cdrom %s %s", + data->machine, data->tcg_only ? "" : "-accel kvm", + data->uefi_fl1, data->uefi_fl2, data->cd, params ? params = : ""); + } else { + args =3D g_strdup_printf("-machine %s %s -accel tcg " + "-nodefaults -nographic " + "-drive if=3Dpflash,format=3Draw,file=3D%s,readonly " + "-drive if=3Dpflash,format=3Draw,file=3D%s,snapshot=3Don %= s", + data->machine, data->tcg_only ? "" : "-accel kvm", + data->uefi_fl1, data->uefi_fl2, params ? params : ""); + } } else { /* Disable kernel irqchip to be able to override apic irq0. */ args =3D g_strdup_printf("-machine %s,kernel-irqchip=3Doff %s -acc= el tcg " @@ -961,6 +970,40 @@ static void test_acpi_virt_tcg_numamem(void) =20 } =20 +#ifdef CONFIG_PXB +static void test_acpi_virt_tcg_pxb(void) +{ + test_data data =3D { + .machine =3D "virt", + .tcg_only =3D true, + .uefi_fl1 =3D "pc-bios/edk2-aarch64-code.fd", + .uefi_fl2 =3D "pc-bios/edk2-arm-vars.fd", + .ram_start =3D 0x40000000ULL, + .scan_len =3D 128ULL * 1024 * 1024, + }; + /* + * While using -cdrom, the cdrom would auto plugged into pxb-pcie, + * the reason is the bus of pxb-pcie is also root bus, it would lead + * to the error only PCI/PCIE bridge could plug onto pxb. + * Therefore,thr cdrom is defined and plugged onto the scsi controller + * to solve the conflicts. + */ + data.variant =3D ".pxb"; + test_acpi_one(" -device pcie-root-port,chassis=3D1,id=3Dpci.1" + " -device virtio-scsi-pci,id=3Dscsi0,bus=3Dpci.1" + " -drive file=3D" + "tests/data/uefi-boot-images/bios-tables-test.aarch64.is= o.qcow2," + "if=3Dnone,media=3Dcdrom,id=3Ddrive-scsi0-0-0-1,readonly= =3Don" + " -device scsi-cd,bus=3Dscsi0.0,scsi-id=3D0," + "drive=3Ddrive-scsi0-0-0-1,id=3Dscsi0-0-0-1,bootindex=3D= 1" + " -cpu cortex-a57" + " -device pxb-pcie,bus_nr=3D128", + &data); + + free_test_data(&data); +} +#endif + static void test_acpi_tcg_acpi_hmat(const char *machine) { test_data data; @@ -1053,6 +1096,9 @@ int main(int argc, char *argv[]) qtest_add_func("acpi/virt", test_acpi_virt_tcg); qtest_add_func("acpi/virt/numamem", test_acpi_virt_tcg_numamem); qtest_add_func("acpi/virt/memhp", test_acpi_virt_tcg_memhp); +#ifdef CONFIG_PXB + qtest_add_func("acpi/virt/pxb", test_acpi_virt_tcg_pxb); +#endif } ret =3D g_test_run(); boot_sector_cleanup(disk); --=20 2.19.1 From nobody Fri May 10 08:50:23 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1586350952; 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Wed, 8 Apr 2020 20:58:36 +0800 From: Yubo Miao To: , , Subject: [PATCH v6 8/8] unit-test: Add the binary file and clear diff.h Date: Wed, 8 Apr 2020 20:58:16 +0800 Message-ID: <20200408125816.955-9-miaoyubo@huawei.com> X-Mailer: git-send-email 2.24.1.windows.2 In-Reply-To: <20200408125816.955-1-miaoyubo@huawei.com> References: <20200408125816.955-1-miaoyubo@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.173.221.29] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: berrange@redhat.com, mst@redhat.com, qemu-devel@nongnu.org, xiexiangyou@huawei.com, miaoyubo@huawei.com, imammedo@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: miaoyubo Add the binary file DSDT.pxb and clear bios-tables-test-allowed-diff.h Signed-off-by: miaoyubo --- tests/data/acpi/virt/DSDT.pxb | Bin 0 -> 7802 bytes tests/qtest/bios-tables-test-allowed-diff.h | 1 - 2 files changed, 1 deletion(-) create mode 100644 tests/data/acpi/virt/DSDT.pxb diff --git a/tests/data/acpi/virt/DSDT.pxb b/tests/data/acpi/virt/DSDT.pxb new file mode 100644 index 0000000000000000000000000000000000000000..d5f0533a02d62bc2ae2db9b9de9= 484e5c06652fe GIT binary patch literal 7802 zcmeI1%WoT16o;=3DLiS6+tw&OgUms2Pe&&rRcNlRN|kDbINPK+mQkW$GN2t>&y5*4DY z5GE1@x}%ZUunAHY{255B*s){5x*Prhb`0mvok@O&o()@MN3!S4-1E)-#wYff>!#D( zdAOidc(<`_Z#avMce{3z_Jx#EdRxC{zj_wB({~#Ey~7#1TrS7^8|`MgZg<-hEUS3` zR=3DcV84zJqVo#0rnvr#TrD*mx}-|jiN8EfisLTO+^WtIANRE0w4D0)D-m9e1W1K-`?I3=3D=3D%fJX5q(*jFqgf=3DxI;=3D+i!j2&*$h#YZ&sEUM@nAgr*&hytUE zjGD-ZNQ_Zn)R1vWWJD!K92l37u_Q7^B!&fyC1hL{8KV*-1&qtcSQZ&EiID-uGBQ>~ zMqFZKfw6*&DG%GO{fw77VxlVHu;{{;Uks;S< zUSgaFMgtjgosLV43&5~}QI+eoATeGBMiUuwolZ!MSAo$&hFqtU661AXtRX|L(Vw8cgfeg7$ixQ&>j5adlI-QXimw<5-8FHP@N{q|EcpDjVoz6*&6<};4 zL$1?#iE$Me9bnYtI$e+$*MPBw47pBA65|FiwtYtDhpxTi&!fB5E!WE{)VJ8wgqf&D zQN7vI`@BBFX|2AGs&X_uAR4$*c+C9j#H9`7}G}OzaP-oI?ys;54Gnhd{>C9kg#AMP?FOx!@Ni*^?sUtLF z{m6IphEmhyTLvL|jxf&=3D@0@|>h{+5lPa%4aGEZuLX$HYiYO>IiLiCI=3D&lvNJaZd`- zGtNBYUS@Dfs3}8F3ehvcJgIFrSI@g73GPWDdRolWVxH8*p(lmtnPi?x=3D9%Q46ryK} zd8U{rHGSwwA$q2nXPSAYxhI9_nPHw8=3D1EN=3DdQymU3el5po1kv9%#)f* z^rR3ybIdcxJagQWLiEft&ph*_CKNp>M9*>NInF%CxhI9_Szw+8=3D1EN}dQym<6U=3Djh zc}{Ro3ej_tc}_ARl0q^1}>DMZgA^DHvYBKM>a zJ!hEb4D+NW8a*jQ&spX<%RFbfCxz%a$2{klCpF#ZNg;a9GtYVEInO;QL{D1OFrQi8 zXZ!;5q$V9bDMZf_^DHsX68EIgcZYER-{LZqUNJz{O9IR6<1D|`%V{aWZ#O?fGWMl>9uyC1I^JJHH~_tpRAI8KF&Tp zx)=3DJKj#RwSmE*~$N5MF=3DJF5>K=3D)rpb$^MTSvtOU2a0Ek zp0J{OUnX^Ex184IVqw1Dy1kP)(81l~?9rpUmR_}c+}-Uptij%4QEy