From nobody Fri May 17 06:54:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (BodyHash is different from the expected one) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1586181433399590.8904253211807; Mon, 6 Apr 2020 06:57:13 -0700 (PDT) Received: from localhost ([::1]:60526 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jLSFT-0006nA-Tt for importer@patchew.org; Mon, 06 Apr 2020 09:57:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54151) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jLSBl-00041T-OO for qemu-devel@nongnu.org; Mon, 06 Apr 2020 09:53:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jLSBi-000288-EW for qemu-devel@nongnu.org; Mon, 06 Apr 2020 09:53:21 -0400 Received: from beetle.greensocs.com ([5.135.226.135]:56982) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jLSBd-00021e-RG; Mon, 06 Apr 2020 09:53:14 -0400 Received: from crumble.bar.greensocs.com (unknown [172.17.10.14]) by beetle.greensocs.com (Postfix) with ESMTPS id 64C9F96EF2; Mon, 6 Apr 2020 13:53:11 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1586181192; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6Z/Q4Pl53YiQHaCIjfeb844c6FsKQSf/RaoXBn6XrVg=; b=DqlnXVVU/8I6Fva0VIdqWa3koexmC09YYVlqqx1ls13ZlLoc5U74H7FRCMiTt36xgf2pXb MMqIjiJjTEmGi/TTjoZO0YpOm8Gutqd0wajquuH2osdBTbFPH1hym0saXyyeXxmg5h+Jxw GWmmULZ/DH2ZxIjCM/QyEttsmpHwrpU= From: Damien Hedde To: qemu-devel@nongnu.org Subject: [PATCH v9 1/9] hw/core/clock: introduce clock object Date: Mon, 6 Apr 2020 15:52:43 +0200 Message-Id: <20200406135251.157596-2-damien.hedde@greensocs.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200406135251.157596-1-damien.hedde@greensocs.com> References: <20200406135251.157596-1-damien.hedde@greensocs.com> MIME-Version: 1.0 ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1586181192; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=6Z/Q4Pl53YiQHaCIjfeb844c6FsKQSf/RaoXBn6XrVg=; b=qrNUQ4mImJqDJfnfV12aWqSGgJN0RSBkN+oARrjSCyj9NAGn40IIoEEfZHbAXZg0PnPxgG wamaFiDpV7TbgzfrycGxuyD092fuCV7j+HjOFeZ+Km264nPht1ozE7q1VSfXzCLnVgFal8 3HBk2NeqcJSIckMCQufpGj5SlW2dI2c= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1586181192; a=rsa-sha256; cv=none; b=QyYmsjwrryjuJ2owmWNiLamNYrbTbMWhVXPZckRKfFoSDO0N56FTyu4yNiuh50P1r616SC Ldufpb1Inac55+2J+JKLCIBFaCAjX1YfAbEmt1RmPwjwvqHahXs/mtB4D/RXW0WkqgM2we WZtA9o6HvKmhIKE0aun4YUeB/eWrhf8= ARC-Authentication-Results: i=1; beetle.greensocs.com; none X-Spam: Yes Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 5.135.226.135 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , peter.maydell@linaro.org, "Edgar E . Iglesias" , berrange@redhat.com, ehabkost@redhat.com, pbonzini@redhat.com, alistair@alistair23.me, mark.burton@greensocs.com, qemu-arm@nongnu.org, Alistair Francis , marcandre.lureau@redhat.com, edgar.iglesias@gmail.com, philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This object may be used to represent a clock inside a clock tree. A clock may be connected to another clock so that it receives update, through a callback, whenever the source/parent clock is updated. Although only the root clock of a clock tree controls the values (represented as periods) of all clocks in tree, each clock holds a local state containing the current value so that it can be fetched independently. It will allows us to fullfill migration requirements by migrating each clock independently of others. This is based on the original work of Frederic Konrad. Signed-off-by: Damien Hedde Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias -- v8: + fix hw/core/Makefiles.objs entry (Alistair) + no more field zeroing in finalizefn (Alistair) + typos (Alistair) v7: + merge ClockIn & ClockOut into a single type Clock + switch clock state to a period with 2^-32ns unit + add some Hz and ns helpers + propagate clock period when setting the source so that clocks with fixed period are easy to handle. --- include/hw/clock.h | 216 ++++++++++++++++++++++++++++++++++++++++++ hw/core/clock.c | 130 +++++++++++++++++++++++++ hw/core/Makefile.objs | 1 + hw/core/trace-events | 7 ++ 4 files changed, 354 insertions(+) create mode 100644 include/hw/clock.h create mode 100644 hw/core/clock.c diff --git a/include/hw/clock.h b/include/hw/clock.h new file mode 100644 index 0000000000..82a7f3c698 --- /dev/null +++ b/include/hw/clock.h @@ -0,0 +1,216 @@ +/* + * Hardware Clocks + * + * Copyright GreenSocs 2016-2020 + * + * Authors: + * Frederic Konrad + * Damien Hedde + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef QEMU_HW_CLOCK_H +#define QEMU_HW_CLOCK_H + +#include "qom/object.h" +#include "qemu/queue.h" + +#define TYPE_CLOCK "clock" +#define CLOCK(obj) OBJECT_CHECK(Clock, (obj), TYPE_CLOCK) + +typedef void ClockCallback(void *opaque); + +/* + * clock store a value representing the clock's period in 2^-32ns unit. + * It can represent: + * + periods from 2^-32ns up to 4seconds + * + frequency from ~0.25Hz 2e10Ghz + * Resolution of frequency representation decreases with frequency: + * + at 100MHz, resolution is ~2mHz + * + at 1Ghz, resolution is ~0.2Hz + * + at 10Ghz, resolution is ~20Hz + */ +#define CLOCK_SECOND (1000000000llu << 32) + +/* + * macro helpers to convert to hertz / nanosecond + */ +#define CLOCK_PERIOD_FROM_NS(ns) ((ns) * (CLOCK_SECOND / 1000000000llu)) +#define CLOCK_PERIOD_TO_NS(per) ((per) / (CLOCK_SECOND / 1000000000llu)) +#define CLOCK_PERIOD_FROM_HZ(hz) (((hz) !=3D 0) ? CLOCK_SECOND / (hz) : 0u) +#define CLOCK_PERIOD_TO_HZ(per) (((per) !=3D 0) ? CLOCK_SECOND / (per) : 0= u) + +/** + * Clock: + * @parent_obj: parent class + * @period: unsigned integer representing the period of the clock + * @canonical_path: clock path string cache (used for trace purpose) + * @callback: called when clock changes + * @callback_opaque: argument for @callback + * @source: source (or parent in clock tree) of the clock + * @children: list of clocks connected to this one (it is their source) + * @sibling: structure used to form a clock list + */ + +typedef struct Clock Clock; + +struct Clock { + /*< private >*/ + Object parent_obj; + + /* all fields are private and should not be modified directly */ + + /* fields */ + uint64_t period; + char *canonical_path; + ClockCallback *callback; + void *callback_opaque; + + /* Clocks are organized in a clock tree */ + Clock *source; + QLIST_HEAD(, Clock) children; + QLIST_ENTRY(Clock) sibling; +}; + +/** + * clock_setup_canonical_path: + * @clk: clock + * + * compute the canonical path of the clock (used by log messages) + */ +void clock_setup_canonical_path(Clock *clk); + +/** + * clock_set_callback: + * @clk: the clock to register the callback into + * @cb: the callback function + * @opaque: the argument to the callback + * + * Register a callback called on every clock update. + */ +void clock_set_callback(Clock *clk, ClockCallback *cb, void *opaque); + +/** + * clock_clear_callback: + * @clk: the clock to delete the callback from + * + * Unregister the callback registered with clock_set_callback. + */ +void clock_clear_callback(Clock *clk); + +/** + * clock_set_source: + * @clk: the clock. + * @src: the source clock + * + * Setup @src as the clock source of @clk. The current @src period + * value is also copied to @clk and its subtree but no callback is + * called. + * Further @src update will be propagated to @clk and its subtree. + */ +void clock_set_source(Clock *clk, Clock *src); + +/** + * clock_set: + * @clk: the clock to initialize. + * @value: the clock's value, 0 means unclocked + * + * Set the local cached period value of @clk to @value. + */ +void clock_set(Clock *clk, uint64_t value); + +static inline void clock_set_hz(Clock *clk, unsigned hz) +{ + clock_set(clk, CLOCK_PERIOD_FROM_HZ(hz)); +} + +static inline void clock_set_ns(Clock *clk, unsigned ns) +{ + clock_set(clk, CLOCK_PERIOD_FROM_NS(ns)); +} + +/** + * clock_propagate: + * @clk: the clock + * + * Propagate the clock period that has been previously configured using + * @clock_set(). This will update recursively all connected clocks. + * It is an error to call this function on a clock which has a source. + * Note: this function must not be called during device inititialization + * or migration. + */ +void clock_propagate(Clock *clk); + +/** + * clock_update: + * @clk: the clock to update. + * @value: the new clock's value, 0 means unclocked + * + * Update the @clk to the new @value. All connected clocks will be informed + * of this update. This is equivalent to call @clock_set() then + * @clock_propagate(). + */ +static inline void clock_update(Clock *clk, uint64_t value) +{ + clock_set(clk, value); + clock_propagate(clk); +} + +static inline void clock_update_hz(Clock *clk, unsigned hz) +{ + clock_update(clk, CLOCK_PERIOD_FROM_HZ(hz)); +} + +static inline void clock_update_ns(Clock *clk, unsigned ns) +{ + clock_update(clk, CLOCK_PERIOD_FROM_NS(ns)); +} + +/** + * clock_get: + * @clk: the clk to fetch the clock + * + * @return: the current period. + */ +static inline uint64_t clock_get(const Clock *clk) +{ + return clk->period; +} + +static inline unsigned clock_get_hz(Clock *clk) +{ + return CLOCK_PERIOD_TO_HZ(clock_get(clk)); +} + +static inline unsigned clock_get_ns(Clock *clk) +{ + return CLOCK_PERIOD_TO_NS(clock_get(clk)); +} + +/** + * clock_is_enabled: + * @clk: a clock + * + * @return: true if the clock is running. + */ +static inline bool clock_is_enabled(const Clock *clk) +{ + return clock_get(clk) !=3D 0; +} + +static inline void clock_init(Clock *clk, uint64_t value) +{ + clock_set(clk, value); +} +static inline void clock_init_hz(Clock *clk, uint64_t value) +{ + clock_set_hz(clk, value); +} +static inline void clock_init_ns(Clock *clk, uint64_t value) +{ + clock_set_ns(clk, value); +} + +#endif /* QEMU_HW_CLOCK_H */ diff --git a/hw/core/clock.c b/hw/core/clock.c new file mode 100644 index 0000000000..3c0daf7d4c --- /dev/null +++ b/hw/core/clock.c @@ -0,0 +1,130 @@ +/* + * Hardware Clocks + * + * Copyright GreenSocs 2016-2020 + * + * Authors: + * Frederic Konrad + * Damien Hedde + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "hw/clock.h" +#include "trace.h" + +#define CLOCK_PATH(_clk) (_clk->canonical_path) + +void clock_setup_canonical_path(Clock *clk) +{ + g_free(clk->canonical_path); + clk->canonical_path =3D object_get_canonical_path(OBJECT(clk)); +} + +void clock_set_callback(Clock *clk, ClockCallback *cb, void *opaque) +{ + clk->callback =3D cb; + clk->callback_opaque =3D opaque; +} + +void clock_clear_callback(Clock *clk) +{ + clock_set_callback(clk, NULL, NULL); +} + +void clock_set(Clock *clk, uint64_t period) +{ + trace_clock_set(CLOCK_PATH(clk), CLOCK_PERIOD_TO_NS(clk->period), + CLOCK_PERIOD_TO_NS(period)); + clk->period =3D period; +} + +static void clock_propagate_period(Clock *clk, bool call_callbacks) +{ + Clock *child; + + QLIST_FOREACH(child, &clk->children, sibling) { + if (child->period !=3D clk->period) { + child->period =3D clk->period; + trace_clock_update(CLOCK_PATH(child), CLOCK_PATH(clk), + CLOCK_PERIOD_TO_NS(clk->period), + call_callbacks); + if (call_callbacks && child->callback) { + child->callback(child->callback_opaque); + } + clock_propagate_period(child, call_callbacks); + } + } +} + +void clock_propagate(Clock *clk) +{ + assert(clk->source =3D=3D NULL); + trace_clock_propagate(CLOCK_PATH(clk)); + clock_propagate_period(clk, true); +} + +void clock_set_source(Clock *clk, Clock *src) +{ + /* changing clock source is not supported */ + assert(!clk->source); + + trace_clock_set_source(CLOCK_PATH(clk), CLOCK_PATH(src)); + + clk->period =3D src->period; + QLIST_INSERT_HEAD(&src->children, clk, sibling); + clk->source =3D src; + clock_propagate_period(clk, false); +} + +static void clock_disconnect(Clock *clk) +{ + if (clk->source =3D=3D NULL) { + return; + } + + trace_clock_disconnect(CLOCK_PATH(clk)); + + clk->source =3D NULL; + QLIST_REMOVE(clk, sibling); +} + +static void clock_initfn(Object *obj) +{ + Clock *clk =3D CLOCK(obj); + + QLIST_INIT(&clk->children); +} + +static void clock_finalizefn(Object *obj) +{ + Clock *clk =3D CLOCK(obj); + Clock *child, *next; + + /* clear our list of children */ + QLIST_FOREACH_SAFE(child, &clk->children, sibling, next) { + clock_disconnect(child); + } + + /* remove us from source's children list */ + clock_disconnect(clk); + + g_free(clk->canonical_path); +} + +static const TypeInfo clock_info =3D { + .name =3D TYPE_CLOCK, + .parent =3D TYPE_OBJECT, + .instance_size =3D sizeof(Clock), + .instance_init =3D clock_initfn, + .instance_finalize =3D clock_finalizefn, +}; + +static void clock_register_types(void) +{ + type_register_static(&clock_info); +} + +type_init(clock_register_types) diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs index 6215e7c208..1d9b0aa205 100644 --- a/hw/core/Makefile.objs +++ b/hw/core/Makefile.objs @@ -7,6 +7,7 @@ common-obj-y +=3D hotplug.o common-obj-y +=3D vmstate-if.o # irq.o needed for qdev GPIO handling: common-obj-y +=3D irq.o +common-obj-y +=3D clock.o =20 common-obj-$(CONFIG_SOFTMMU) +=3D reset.o common-obj-$(CONFIG_SOFTMMU) +=3D qdev-fw.o diff --git a/hw/core/trace-events b/hw/core/trace-events index aecd8e160e..39301621ce 100644 --- a/hw/core/trace-events +++ b/hw/core/trace-events @@ -27,3 +27,10 @@ resettable_phase_exit_begin(void *obj, const char *objty= pe, unsigned count, int resettable_phase_exit_exec(void *obj, const char *objtype, int has_method)= "obj=3D%p(%s) method=3D%d" resettable_phase_exit_end(void *obj, const char *objtype, unsigned count) = "obj=3D%p(%s) count=3D%d" resettable_transitional_function(void *obj, const char *objtype) "obj=3D%p= (%s)" + +# clock.c +clock_set_source(const char *clk, const char *src) "'%s', src=3D'%s'" +clock_disconnect(const char *clk) "'%s'" +clock_set(const char *clk, unsigned long long old, unsigned long long new)= "'%s', ns=3D%llu->%llu" +clock_propagate(const char *clk) "'%s'" +clock_update(const char *clk, const char *src, unsigned long long val, int= cb) "'%s', src=3D'%s', ns=3D%llu, cb=3D%d" --=20 2.26.0 From nobody Fri May 17 06:54:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Mon, 06 Apr 2020 09:53:18 -0400 Received: from beetle.greensocs.com ([5.135.226.135]:57006) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jLSBe-000222-8B; Mon, 06 Apr 2020 09:53:14 -0400 Received: from crumble.bar.greensocs.com (unknown [172.17.10.14]) by beetle.greensocs.com (Postfix) with ESMTPS id 2847296F50; Mon, 6 Apr 2020 13:53:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1586181192; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Rq6m+vucrgvZy/M+Gi95Dh58FmBHWgpH8MYOnBgpeVI=; b=CQ10Ml8NWy3V0EgwTkXH3jjbMqUYMy3E30/UByIRj8YmqQxQ2ll/exkNhLXy8vnDkmdzOa 40oCZIHTUbuNdILlXU1PXKjK3+JJblj1X+eiaVa+SyVwihI0hRowtHd9eVpsLMXVjRLJvd 5D0QSiTawrDC3LEUpMtI1Gud+f7FRu8= From: Damien Hedde To: qemu-devel@nongnu.org Subject: [PATCH v9 2/9] hw/core/clock-vmstate: define a vmstate entry for clock state Date: Mon, 6 Apr 2020 15:52:44 +0200 Message-Id: <20200406135251.157596-3-damien.hedde@greensocs.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200406135251.157596-1-damien.hedde@greensocs.com> References: <20200406135251.157596-1-damien.hedde@greensocs.com> MIME-Version: 1.0 ARC-Message-Signature: i=1; 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Iglesias" , berrange@redhat.com, ehabkost@redhat.com, pbonzini@redhat.com, alistair@alistair23.me, mark.burton@greensocs.com, qemu-arm@nongnu.org, Alistair Francis , marcandre.lureau@redhat.com, edgar.iglesias@gmail.com, philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Signed-off-by: Damien Hedde Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias -- v7: remove leading underscores in macro args --- include/hw/clock.h | 9 +++++++++ hw/core/clock-vmstate.c | 25 +++++++++++++++++++++++++ hw/core/Makefile.objs | 1 + 3 files changed, 35 insertions(+) create mode 100644 hw/core/clock-vmstate.c diff --git a/include/hw/clock.h b/include/hw/clock.h index 82a7f3c698..f3e44e9460 100644 --- a/include/hw/clock.h +++ b/include/hw/clock.h @@ -74,6 +74,15 @@ struct Clock { QLIST_ENTRY(Clock) sibling; }; =20 +/* + * vmstate description entry to be added in device vmsd. + */ +extern const VMStateDescription vmstate_clock; +#define VMSTATE_CLOCK(field, state) \ + VMSTATE_CLOCK_V(field, state, 0) +#define VMSTATE_CLOCK_V(field, state, version) \ + VMSTATE_STRUCT_POINTER_V(field, state, version, vmstate_clock, Clock) + /** * clock_setup_canonical_path: * @clk: clock diff --git a/hw/core/clock-vmstate.c b/hw/core/clock-vmstate.c new file mode 100644 index 0000000000..260b13fc2c --- /dev/null +++ b/hw/core/clock-vmstate.c @@ -0,0 +1,25 @@ +/* + * Clock migration structure + * + * Copyright GreenSocs 2019-2020 + * + * Authors: + * Damien Hedde + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "migration/vmstate.h" +#include "hw/clock.h" + +const VMStateDescription vmstate_clock =3D { + .name =3D "clock", + .version_id =3D 0, + .minimum_version_id =3D 0, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(period, Clock), + VMSTATE_END_OF_LIST() + } +}; diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs index 1d9b0aa205..115df55087 100644 --- a/hw/core/Makefile.objs +++ b/hw/core/Makefile.objs @@ -21,6 +21,7 @@ common-obj-$(CONFIG_SOFTMMU) +=3D null-machine.o common-obj-$(CONFIG_SOFTMMU) +=3D loader.o common-obj-$(CONFIG_SOFTMMU) +=3D machine-hmp-cmds.o common-obj-$(CONFIG_SOFTMMU) +=3D numa.o +common-obj-$(CONFIG_SOFTMMU) +=3D clock-vmstate.o obj-$(CONFIG_SOFTMMU) +=3D machine-qmp-cmds.o =20 common-obj-$(CONFIG_EMPTY_SLOT) +=3D empty_slot.o --=20 2.26.0 From nobody Fri May 17 06:54:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (BodyHash is different from the expected one) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1586181518147744.8075974514157; Mon, 6 Apr 2020 06:58:38 -0700 (PDT) Received: from localhost ([::1]:60532 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jLSGq-0007xx-NF for importer@patchew.org; Mon, 06 Apr 2020 09:58:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54137) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jLSBl-00040V-5a for qemu-devel@nongnu.org; Mon, 06 Apr 2020 09:53:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jLSBi-00028W-SH for qemu-devel@nongnu.org; Mon, 06 Apr 2020 09:53:21 -0400 Received: from beetle.greensocs.com ([5.135.226.135]:57034) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jLSBe-000228-FL; Mon, 06 Apr 2020 09:53:14 -0400 Received: from crumble.bar.greensocs.com (unknown [172.17.10.14]) by beetle.greensocs.com (Postfix) with ESMTPS id EA1D896F51; Mon, 6 Apr 2020 13:53:12 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1586181193; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=I40Ev6JDEVT3KkXhMiUkSXuMNflE19MYy5lSk1Ft8PA=; b=d/O8BvGoyljt0tlKeeBd1EiW6iZAzjT6BLNQzBhLv1L04eS9OOuG6azBpPf5jNP8O26U7P 4x+gpuoeWIfTWafABrK990/5r0iFrPjR8n4iwcXl3BFCOZCBKbUyABynbhQMYrG028TCW1 pop2e4ASumwgfWeSPXEV+9tNwOIMyoA= From: Damien Hedde To: qemu-devel@nongnu.org Subject: [PATCH v9 3/9] qdev: add clock input&output support to devices. Date: Mon, 6 Apr 2020 15:52:45 +0200 Message-Id: <20200406135251.157596-4-damien.hedde@greensocs.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200406135251.157596-1-damien.hedde@greensocs.com> References: <20200406135251.157596-1-damien.hedde@greensocs.com> MIME-Version: 1.0 ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1586181193; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=I40Ev6JDEVT3KkXhMiUkSXuMNflE19MYy5lSk1Ft8PA=; b=fOWpCIyN/s+IqqhzLBrW9FmQyFx2L+4BcW/kshkIIhHvcEdX/o2dj4gKj+BZmsJdD16tP0 WQUewHPpVMi2zswkuMmVwXXxRZZ9dNgPV8RBBuq/FLDWK84bBFmsM5svDxz3NjIpxAMHRS uoX7aevSxJlhzkYIaNkfUPp+rvHwZLI= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1586181193; a=rsa-sha256; cv=none; b=PFOFnYNDDmrT/KWfpYkCjgOIyCT//u4KH+347VDnX8M4mZ0TF2j7Y/+9wfgDj6ub6WQkMY 7ooW5Kz7FG/EufgXt0Ppn+k3cY34XRgqblAU4NEp4nHBau/oUgWgjwvjNY8kCe6hOFjiBS +YVcurVeIUTd3eKLzUg5LACRIuv/rWo= ARC-Authentication-Results: i=1; beetle.greensocs.com; none X-Spam: Yes Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 5.135.226.135 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , peter.maydell@linaro.org, "Edgar E . Iglesias" , berrange@redhat.com, ehabkost@redhat.com, pbonzini@redhat.com, alistair@alistair23.me, mark.burton@greensocs.com, qemu-arm@nongnu.org, Alistair Francis , marcandre.lureau@redhat.com, edgar.iglesias@gmail.com, philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add functions to easily handle clocks with devices. Clock inputs and outputs should be used to handle clock propagation between devices. The API is very similar the GPIO API. This is based on the original work of Frederic Konrad. Signed-off-by: Damien Hedde Reviewed-by: Edgar E. Iglesias Reviewed-by: Alistair Francis --- v8: + remove another useless assert (Alistair) + typos, comments (Alistair) v7: + update ClockIn/Out types + qdev_connect_clock_out function removed / qdev_connect_clock_in added instead + qdev_pass_clock renamed to qdev_alias_clock + various small fixes (typos, comment, asserts) (Peter) + move device's instance_finalize code related to clock in qdev-clock.c --- include/hw/qdev-clock.h | 104 +++++++++++++++++++++++++ include/hw/qdev-core.h | 12 +++ hw/core/qdev-clock.c | 168 ++++++++++++++++++++++++++++++++++++++++ hw/core/qdev.c | 12 +++ hw/core/Makefile.objs | 2 +- tests/Makefile.include | 1 + 6 files changed, 298 insertions(+), 1 deletion(-) create mode 100644 include/hw/qdev-clock.h create mode 100644 hw/core/qdev-clock.c diff --git a/include/hw/qdev-clock.h b/include/hw/qdev-clock.h new file mode 100644 index 0000000000..b3b3a3e021 --- /dev/null +++ b/include/hw/qdev-clock.h @@ -0,0 +1,104 @@ +/* + * Device's clock input and output + * + * Copyright GreenSocs 2016-2020 + * + * Authors: + * Frederic Konrad + * Damien Hedde + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#ifndef QDEV_CLOCK_H +#define QDEV_CLOCK_H + +#include "hw/clock.h" + +/** + * qdev_init_clock_in: + * @dev: the device to add an input clock to + * @name: the name of the clock (can't be NULL). + * @callback: optional callback to be called on update or NULL. + * @opaque: argument for the callback + * @returns: a pointer to the newly added clock + * + * Add an input clock to device @dev as a clock named @name. + * This adds a child<> property. + * The callback will be called with @opaque as opaque parameter. + */ +Clock *qdev_init_clock_in(DeviceState *dev, const char *name, + ClockCallback *callback, void *opaque); + +/** + * qdev_init_clock_out: + * @dev: the device to add an output clock to + * @name: the name of the clock (can't be NULL). + * @returns: a pointer to the newly added clock + * + * Add an output clock to device @dev as a clock named @name. + * This adds a child<> property. + */ +Clock *qdev_init_clock_out(DeviceState *dev, const char *name); + +/** + * qdev_get_clock_in: + * @dev: the device which has the clock + * @name: the name of the clock (can't be NULL). + * @returns: a pointer to the clock + * + * Get the input clock @name from @dev or NULL if does not exist. + */ +Clock *qdev_get_clock_in(DeviceState *dev, const char *name); + +/** + * qdev_get_clock_out: + * @dev: the device which has the clock + * @name: the name of the clock (can't be NULL). + * @returns: a pointer to the clock + * + * Get the output clock @name from @dev or NULL if does not exist. + */ +Clock *qdev_get_clock_out(DeviceState *dev, const char *name); + +/** + * qdev_connect_clock_in: + * @dev: a device + * @name: the name of an input clock in @dev + * @source: the source clock (an output clock of another device for exampl= e) + * + * Set the source clock of input clock @name of device @dev to @source. + * @source period update will be propagated to @name clock. + */ +static inline void qdev_connect_clock_in(DeviceState *dev, const char *nam= e, + Clock *source) +{ + clock_set_source(qdev_get_clock_in(dev, name), source); +} + +/** + * qdev_alias_clock: + * @dev: the device which has the clock + * @name: the name of the clock in @dev (can't be NULL) + * @alias_dev: the device to add the clock + * @alias_name: the name of the clock in @container + * @returns: a pointer to the clock + * + * Add a clock @alias_name in @alias_dev which is an alias of the clock @n= ame + * in @dev. The direction _in_ or _out_ will the same as the original. + * An alias clock must not be modified or used by @alias_dev and should + * typically be only only for device composition purpose. + */ +Clock *qdev_alias_clock(DeviceState *dev, const char *name, + DeviceState *alias_dev, const char *alias_name); + +/** + * qdev_finalize_clocklist: + * @dev: the device being finalized + * + * Clear the clocklist from @dev. Only used internally in qdev. + */ +void qdev_finalize_clocklist(DeviceState *dev); + +#endif /* QDEV_CLOCK_H */ diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index 1405b8a990..d87d989e72 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -149,6 +149,17 @@ struct NamedGPIOList { QLIST_ENTRY(NamedGPIOList) node; }; =20 +typedef struct Clock Clock; +typedef struct NamedClockList NamedClockList; + +struct NamedClockList { + char *name; + Clock *clock; + bool output; + bool alias; + QLIST_ENTRY(NamedClockList) node; +}; + /** * DeviceState: * @realized: Indicates whether the device has been fully constructed. @@ -171,6 +182,7 @@ struct DeviceState { bool allow_unplug_during_migration; BusState *parent_bus; QLIST_HEAD(, NamedGPIOList) gpios; + QLIST_HEAD(, NamedClockList) clocks; QLIST_HEAD(, BusState) child_bus; int num_child_bus; int instance_id_alias; diff --git a/hw/core/qdev-clock.c b/hw/core/qdev-clock.c new file mode 100644 index 0000000000..62035aef83 --- /dev/null +++ b/hw/core/qdev-clock.c @@ -0,0 +1,168 @@ +/* + * Device's clock input and output + * + * Copyright GreenSocs 2016-2020 + * + * Authors: + * Frederic Konrad + * Damien Hedde + * + * This work is licensed under the terms of the GNU GPL, version 2 or late= r. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include "hw/qdev-clock.h" +#include "hw/qdev-core.h" +#include "qapi/error.h" + +/* + * qdev_init_clocklist: + * Add a new clock in a device + */ +static NamedClockList *qdev_init_clocklist(DeviceState *dev, const char *n= ame, + bool output, Clock *clk) +{ + NamedClockList *ncl; + + /* + * Clock must be added before realize() so that we can compute the + * clock's canonical path during device_realize(). + */ + assert(!dev->realized); + + /* + * The ncl structure is freed by qdev_finalize_clocklist() which will + * be called during @dev's device_finalize(). + */ + ncl =3D g_new0(NamedClockList, 1); + ncl->name =3D g_strdup(name); + ncl->output =3D output; + ncl->alias =3D (clk !=3D NULL); + + /* + * Trying to create a clock whose name clashes with some other + * clock or property is a bug in the caller and we will abort(). + */ + if (clk =3D=3D NULL) { + clk =3D CLOCK(object_new(TYPE_CLOCK)); + object_property_add_child(OBJECT(dev), name, OBJECT(clk), &error_a= bort); + if (output) { + /* + * Remove object_new()'s initial reference. + * Note that for inputs, the reference created by object_new() + * will be deleted in qdev_finalize_clocklist(). + */ + object_unref(OBJECT(clk)); + } + } else { + object_property_add_link(OBJECT(dev), name, + object_get_typename(OBJECT(clk)), + (Object **) &ncl->clock, + NULL, OBJ_PROP_LINK_STRONG, &error_abort); + } + + ncl->clock =3D clk; + + QLIST_INSERT_HEAD(&dev->clocks, ncl, node); + return ncl; +} + +void qdev_finalize_clocklist(DeviceState *dev) +{ + /* called by @dev's device_finalize() */ + NamedClockList *ncl, *ncl_next; + + QLIST_FOREACH_SAFE(ncl, &dev->clocks, node, ncl_next) { + QLIST_REMOVE(ncl, node); + if (!ncl->output && !ncl->alias) { + /* + * We kept a reference on the input clock to ensure it lives u= p to + * this point so we can safely remove the callback. + * It avoids having a callback to a deleted object if ncl->clo= ck + * is still referenced somewhere else (eg: by a clock output). + */ + clock_clear_callback(ncl->clock); + object_unref(OBJECT(ncl->clock)); + } + g_free(ncl->name); + g_free(ncl); + } +} + +Clock *qdev_init_clock_out(DeviceState *dev, const char *name) +{ + NamedClockList *ncl; + + assert(name); + + ncl =3D qdev_init_clocklist(dev, name, true, NULL); + + return ncl->clock; +} + +Clock *qdev_init_clock_in(DeviceState *dev, const char *name, + ClockCallback *callback, void *opaque) +{ + NamedClockList *ncl; + + assert(name); + + ncl =3D qdev_init_clocklist(dev, name, false, NULL); + + if (callback) { + clock_set_callback(ncl->clock, callback, opaque); + } + return ncl->clock; +} + +static NamedClockList *qdev_get_clocklist(DeviceState *dev, const char *na= me) +{ + NamedClockList *ncl; + + QLIST_FOREACH(ncl, &dev->clocks, node) { + if (strcmp(name, ncl->name) =3D=3D 0) { + return ncl; + } + } + + return NULL; +} + +Clock *qdev_get_clock_in(DeviceState *dev, const char *name) +{ + NamedClockList *ncl; + + assert(name); + + ncl =3D qdev_get_clocklist(dev, name); + assert(!ncl->output); + + return ncl->clock; +} + +Clock *qdev_get_clock_out(DeviceState *dev, const char *name) +{ + NamedClockList *ncl; + + assert(name); + + ncl =3D qdev_get_clocklist(dev, name); + assert(ncl->output); + + return ncl->clock; +} + +Clock *qdev_alias_clock(DeviceState *dev, const char *name, + DeviceState *alias_dev, const char *alias_name) +{ + NamedClockList *ncl; + + assert(name && alias_name); + + ncl =3D qdev_get_clocklist(dev, name); + + qdev_init_clocklist(alias_dev, alias_name, ncl->output, ncl->clock); + + return ncl->clock; +} diff --git a/hw/core/qdev.c b/hw/core/qdev.c index 85f062def7..dd77a56067 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -37,6 +37,7 @@ #include "hw/qdev-properties.h" #include "hw/boards.h" #include "hw/sysbus.h" +#include "hw/qdev-clock.h" #include "migration/vmstate.h" #include "trace.h" =20 @@ -855,6 +856,7 @@ static void device_set_realized(Object *obj, bool value= , Error **errp) DeviceClass *dc =3D DEVICE_GET_CLASS(dev); HotplugHandler *hotplug_ctrl; BusState *bus; + NamedClockList *ncl; Error *local_err =3D NULL; bool unattached_parent =3D false; static int unattached_count; @@ -902,6 +904,13 @@ static void device_set_realized(Object *obj, bool valu= e, Error **errp) */ g_free(dev->canonical_path); dev->canonical_path =3D object_get_canonical_path(OBJECT(dev)); + QLIST_FOREACH(ncl, &dev->clocks, node) { + if (ncl->alias) { + continue; + } else { + clock_setup_canonical_path(ncl->clock); + } + } =20 if (qdev_get_vmsd(dev)) { if (vmstate_register_with_alias_id(VMSTATE_IF(dev), @@ -1025,6 +1034,7 @@ static void device_initfn(Object *obj) dev->allow_unplug_during_migration =3D false; =20 QLIST_INIT(&dev->gpios); + QLIST_INIT(&dev->clocks); } =20 static void device_post_init(Object *obj) @@ -1054,6 +1064,8 @@ static void device_finalize(Object *obj) */ } =20 + qdev_finalize_clocklist(dev); + /* Only send event if the device had been completely realized */ if (dev->pending_deleted_event) { g_assert(dev->canonical_path); diff --git a/hw/core/Makefile.objs b/hw/core/Makefile.objs index 115df55087..1d540ed6e7 100644 --- a/hw/core/Makefile.objs +++ b/hw/core/Makefile.objs @@ -7,7 +7,7 @@ common-obj-y +=3D hotplug.o common-obj-y +=3D vmstate-if.o # irq.o needed for qdev GPIO handling: common-obj-y +=3D irq.o -common-obj-y +=3D clock.o +common-obj-y +=3D clock.o qdev-clock.o =20 common-obj-$(CONFIG_SOFTMMU) +=3D reset.o common-obj-$(CONFIG_SOFTMMU) +=3D qdev-fw.o diff --git a/tests/Makefile.include b/tests/Makefile.include index 51de676298..03a74b60f6 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -439,6 +439,7 @@ tests/test-qdev-global-props$(EXESUF): tests/test-qdev-= global-props.o \ hw/core/fw-path-provider.o \ hw/core/reset.o \ hw/core/vmstate-if.o \ + hw/core/clock.o hw/core/qdev-clock.o \ $(test-qapi-obj-y) tests/test-vmstate$(EXESUF): tests/test-vmstate.o \ migration/vmstate.o migration/vmstate-types.o migration/qemu-file.o \ --=20 2.26.0 From nobody Fri May 17 06:54:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Mon, 06 Apr 2020 09:53:19 -0400 Received: from beetle.greensocs.com ([5.135.226.135]:57062) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jLSBf-00022j-85; Mon, 06 Apr 2020 09:53:15 -0400 Received: from crumble.bar.greensocs.com (unknown [172.17.10.14]) by beetle.greensocs.com (Postfix) with ESMTPS id A99C496F52; Mon, 6 Apr 2020 13:53:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1586181194; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xd+c6ZlUhTW+CjsmjUZ8LHr1moi5jsi8mp25Jv1cp0E=; b=BD9p98fd1uLwshkrS+2ytKIb6U6JIgu8x2WRqIprN9ukg121Wyfzez4RDbcfK+rjPHI+5f LrG8PHLS9TJhQRNBBI74AsOje3dN0zYSRhoyWwiBDX34AVBmsa3V2C71OWWulaoOWbvvFn iOeW1/Mj8uvykKq7X1Vb+60HzkK0xwg= From: Damien Hedde To: qemu-devel@nongnu.org Subject: [PATCH v9 4/9] qdev-clock: introduce an init array to ease the device construction Date: Mon, 6 Apr 2020 15:52:46 +0200 Message-Id: <20200406135251.157596-5-damien.hedde@greensocs.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200406135251.157596-1-damien.hedde@greensocs.com> References: <20200406135251.157596-1-damien.hedde@greensocs.com> MIME-Version: 1.0 ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1586181194; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xd+c6ZlUhTW+CjsmjUZ8LHr1moi5jsi8mp25Jv1cp0E=; b=5zBwib28TL6fKOOXLYfKYYp4lupRnqmXjGMJh8zuqjy9+5A8KhO+X/0Ln+P15SUqU09a00 B/NGM067GAHIvgCflk+ctBFSMbGTyHIpgS7dOwnyyNN+J8XdlEszFb3i++u2vhBuA5g+UN JOeuzTuOIlO4Z1AYqKfCgCtBEc0qTcc= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1586181194; a=rsa-sha256; cv=none; b=EWLc22ikmNNFa+wYONptfxXkE4jxOVfgLTVYmr9R8iQUFkCXUoNguDRWnpdGFAFJKrdvDh XlDslJ3XTjZshvCTU+Cl9vOpbcG6AWJ+kzfRSaCH81JOjUZAd5s9uAjc5riYcLuFVuVeR3 QqaqIP5NeFCVzkeIbO2uUgS7iTteSXs= ARC-Authentication-Results: i=1; beetle.greensocs.com; none Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 5.135.226.135 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , peter.maydell@linaro.org, "Edgar E . Iglesias" , berrange@redhat.com, ehabkost@redhat.com, pbonzini@redhat.com, alistair@alistair23.me, mark.burton@greensocs.com, qemu-arm@nongnu.org, Alistair Francis , marcandre.lureau@redhat.com, edgar.iglesias@gmail.com, philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Introduce a function and macro helpers to setup several clocks in a device from a static array description. An element of the array describes the clock (name and direction) as well as the related callback and an optional offset to store the created object pointer in the device state structure. The array must be terminated by a special element QDEV_CLOCK_END. This is based on the original work of Frederic Konrad. Signed-off-by: Damien Hedde Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias -- v7: + update ClockIn/Out types + remove the QDEV_CLOCK_IN_NOFIELD macro + remove leading underscores in macro arguments (Peter) + updated some comments (Peter) + removed trivial asserts (Peter) --- include/hw/qdev-clock.h | 55 +++++++++++++++++++++++++++++++++++++++++ hw/core/qdev-clock.c | 17 +++++++++++++ 2 files changed, 72 insertions(+) diff --git a/include/hw/qdev-clock.h b/include/hw/qdev-clock.h index b3b3a3e021..a340f65ff9 100644 --- a/include/hw/qdev-clock.h +++ b/include/hw/qdev-clock.h @@ -101,4 +101,59 @@ Clock *qdev_alias_clock(DeviceState *dev, const char *= name, */ void qdev_finalize_clocklist(DeviceState *dev); =20 +/** + * ClockPortInitElem: + * @name: name of the clock (can't be NULL) + * @output: indicates whether the clock is input or output + * @callback: for inputs, optional callback to be called on clock's update + * with device as opaque + * @offset: optional offset to store the ClockIn or ClockOut pointer in de= vice + * state structure (0 means unused) + */ +struct ClockPortInitElem { + const char *name; + bool is_output; + ClockCallback *callback; + size_t offset; +}; + +#define clock_offset_value(devstate, field) \ + (offsetof(devstate, field) + \ + type_check(Clock *, typeof_field(devstate, field))) + +#define QDEV_CLOCK(out_not_in, devstate, field, cb) { \ + .name =3D (stringify(field)), \ + .is_output =3D out_not_in, \ + .callback =3D cb, \ + .offset =3D clock_offset_value(devstate, field), \ +} + +/** + * QDEV_CLOCK_(IN|OUT): + * @devstate: structure type. @dev argument of qdev_init_clocks below must= be + * a pointer to that same type. + * @field: a field in @_devstate (must be Clock*) + * @callback: (for input only) callback (or NULL) to be called with the de= vice + * state as argument + * + * The name of the clock will be derived from @field + */ +#define QDEV_CLOCK_IN(devstate, field, callback) \ + QDEV_CLOCK(false, devstate, field, callback) + +#define QDEV_CLOCK_OUT(devstate, field) \ + QDEV_CLOCK(true, devstate, field, NULL) + +#define QDEV_CLOCK_END { .name =3D NULL } + +typedef struct ClockPortInitElem ClockPortInitArray[]; + +/** + * qdev_init_clocks: + * @dev: the device to add clocks to + * @clocks: a QDEV_CLOCK_END-terminated array which contains the + * clocks information. + */ +void qdev_init_clocks(DeviceState *dev, const ClockPortInitArray clocks); + #endif /* QDEV_CLOCK_H */ diff --git a/hw/core/qdev-clock.c b/hw/core/qdev-clock.c index 62035aef83..a94cc44437 100644 --- a/hw/core/qdev-clock.c +++ b/hw/core/qdev-clock.c @@ -116,6 +116,23 @@ Clock *qdev_init_clock_in(DeviceState *dev, const char= *name, return ncl->clock; } =20 +void qdev_init_clocks(DeviceState *dev, const ClockPortInitArray clocks) +{ + const struct ClockPortInitElem *elem; + + for (elem =3D &clocks[0]; elem->name !=3D NULL; elem++) { + Clock **clkp; + /* offset cannot be inside the DeviceState part */ + assert(elem->offset > sizeof(DeviceState)); + clkp =3D (Clock **)(((void *) dev) + elem->offset); + if (elem->is_output) { + *clkp =3D qdev_init_clock_out(dev, elem->name); + } else { + *clkp =3D qdev_init_clock_in(dev, elem->name, elem->callback, = dev); + } + } +} + static NamedClockList *qdev_get_clocklist(DeviceState *dev, const char *na= me) { NamedClockList *ncl; --=20 2.26.0 From nobody Fri May 17 06:54:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (BodyHash is different from the expected one) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1586182013683103.14956883747323; Mon, 6 Apr 2020 07:06:53 -0700 (PDT) Received: from localhost ([::1]:60680 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jLSOp-0007eY-TE for importer@patchew.org; Mon, 06 Apr 2020 10:06:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54204) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jLSBn-00043f-Ix for qemu-devel@nongnu.org; Mon, 06 Apr 2020 09:53:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jLSBl-0002CP-BW for qemu-devel@nongnu.org; Mon, 06 Apr 2020 09:53:23 -0400 Received: from beetle.greensocs.com ([5.135.226.135]:57074) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jLSBf-000231-UK; Mon, 06 Apr 2020 09:53:16 -0400 Received: from crumble.bar.greensocs.com (unknown [172.17.10.14]) by beetle.greensocs.com (Postfix) with ESMTPS id 6B2D596F53; Mon, 6 Apr 2020 13:53:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1586181195; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=YZuOI1lBiJmYkU6/t/C+JfVvwaYj3cFzVs/sOEQ4i3c=; b=sA9nfJQ9EfjZB/1UJvLwH/P+Q96CPcaGWAXDVS1YiNs/e6+xGm+cGR6rc3wjK0X4CvD2CF +RVlY9+Hhjacza1SW055mNOY6dlUp8aW1xo4l73ZOfubeeBRlumf5hjWVj82UhcSb/OPqz ASfFdTvMX+p2WHHovUsQsAhLsQBVeN4= From: Damien Hedde To: qemu-devel@nongnu.org Subject: [PATCH v9 5/9] docs/clocks: add device's clock documentation Date: Mon, 6 Apr 2020 15:52:47 +0200 Message-Id: <20200406135251.157596-6-damien.hedde@greensocs.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200406135251.157596-1-damien.hedde@greensocs.com> References: <20200406135251.157596-1-damien.hedde@greensocs.com> MIME-Version: 1.0 ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1586181195; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=YZuOI1lBiJmYkU6/t/C+JfVvwaYj3cFzVs/sOEQ4i3c=; b=TbUdOagqJwDoJQXkK8Ml56i8k+eAy86W2yXmsfHcegmXc7hfnSE0tPI9+wMZ4nW/Qsvecw OoZw6VAJfQ/gCMB6+N/OeQrhN2Z22RnS54ts8aYCzvGMsLOnMC9/hkSr/xO/hh1s87A3Rj yytU5zJcFR/lSVKNyA+NbjWp3DWvops= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1586181195; a=rsa-sha256; cv=none; b=jT+tDUB+XDVlk9GfvVzvIoX2EGOdE+GFDHo7oBeXvZgbg2XOd7KzNRIIVAGR+zKFu0ZihV P0Y+zhh1d6RxXUN61NOo0pA60Hz77wtkyE88ght1PojPj9/zx11Vn2ylrkk1X1g3U0Yfgc PtPS01FMci9uha2B9ZGplU+0Q6vGWLM= ARC-Authentication-Results: i=1; beetle.greensocs.com; none X-Spam: Yes Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 5.135.226.135 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , peter.maydell@linaro.org, "Edgar E . Iglesias" , berrange@redhat.com, ehabkost@redhat.com, pbonzini@redhat.com, alistair@alistair23.me, mark.burton@greensocs.com, qemu-arm@nongnu.org, Alistair Francis , marcandre.lureau@redhat.com, edgar.iglesias@gmail.com, philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add the documentation about the clock inputs and outputs in devices. This is based on the original work of Frederic Konrad. Signed-off-by: Damien Hedde Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias --- v9: + fix a few typos (Alistair) v8: + fix list indentation + reduce title size v7: + update ClockIn/Out types + switch to rst format --- docs/devel/clocks.rst | 360 ++++++++++++++++++++++++++++++++++++++++++ docs/devel/index.rst | 1 + 2 files changed, 361 insertions(+) create mode 100644 docs/devel/clocks.rst diff --git a/docs/devel/clocks.rst b/docs/devel/clocks.rst new file mode 100644 index 0000000000..ead9f55561 --- /dev/null +++ b/docs/devel/clocks.rst @@ -0,0 +1,360 @@ +Modeling a clock tree in QEMU +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D + +What are clocks +--------------- + +Clocks are QOM objects developed for the purpose of modeling the +distribution of clocks in QEMU. + +They allow us to model the clock distribution of a platform and detect +configuration errors in the clock tree such as badly configured PLL, clock +source selection or disabled clock. + +The object is *Clock* and its QOM name is ``CLOCK``. + +Clocks are typically used with devices where they are used to model inputs +and outputs. They are created in a similar way as gpios. Inputs and outputs +of different devices can be connect together. + +In these cases a Clock object is a child of a Device object but this is not +a requirement. Clocks can be independent of devices. For example it is pos= sible +to create a clock outside of any device to model the main clock source of a +machine. + +Here is an example of clocks:: + + +---------+ +----------------------+ +--------------+ + | Clock 1 | | Device B | | Device C | + | | | +-------+ +-------+ | | +-------+ | + | |>>-+-->>|Clock 2| |Clock 3|>>--->>|Clock 6| | + +---------+ | | | (in) | | (out) | | | | (in) | | + | | +-------+ +-------+ | | +-------+ | + | | +-------+ | +--------------+ + | | |Clock 4|>> + | | | (out) | | +--------------+ + | | +-------+ | | Device D | + | | +-------+ | | +-------+ | + | | |Clock 5|>>--->>|Clock 7| | + | | | (out) | | | | (in) | | + | | +-------+ | | +-------+ | + | +----------------------+ | | + | | +-------+ | + +----------------------------->>|Clock 8| | + | | (in) | | + | +-------+ | + +--------------+ + +Clocks are defined in include/hw/clock.h header and device related functio= ns +are defined in include/hw/qdev-clock.h header. + +The clock state +--------------- + +The state of a clock is its period; it is stored as an integer representing +it in 2^-32ns unit. The special value of 0 is used to represent the clock = being +inactive or gated. The clocks do not model the signal itself (pin toggling) +or other properties such as the duty cycle. + +All clocks contain this state: outputs as well as inputs. It allows to fet= ch +the current period of a clock at any time. When a clock is updated, the +value is immediately propagated to all connected clocks in the tree. + +To ease interaction with clocks. Helpers with a unit suffix are defined for +every clock state setter or getter. They are: + +- ``_ns`` for handling periods in nanosecond, +- ``_hz`` for handling frequencies in hertz. + +The 0 period value is converted to 0 in hertz and vice versa. 0 always mea= ns +that the clock is disabled. + +Adding a new a clock +-------------------- + +Adding clocks to a device must be done during the init method of the Device +instance. + +To add an input clock to a device, the function qdev_init_clock_in must be= used. +It takes the name, a callback and an opaque parameter for the callback (th= is will +be explained in a following section below). +Output is more simple, only the name is required. Typically:: + + qdev_init_clock_in(DEVICE(dev), "clk_in", clk_in_callback, dev); + qdev_init_clock_out(DEVICE(dev), "clk_out"); + +Both functions return the created Clock pointer, which should be saved in = the +device's state structure for further use. + +These objects will be automatically deleted by the QOM reference mechanism. + +Note that it is possible to create a static array describing clock inputs = and +outputs. The function ``qdev_init_clocks()`` must be called with the array= as +parameter to initialize the clocks: it has the same behaviour as calling t= he +``qdev_init_clock_in/out()`` for each clock in the array. To ease the array +construction, some macros are defined in include/hw/qdev-clock.h. +As an example, the following creates 2 clocks to a device: one input and o= ne +output. + +:: + + /* device structure containing pointer to the clock objects */ + typedef struct MyDeviceState { + DeviceState parent_obj; + Clock *clk_in; + Clock *clk_out; + } MyDeviceState; + + /* + * callback for the input clock (see "Callback on input clock + * change" section below for more information). + */ + static void clk_in_callback(void *opaque); + + /* + * static array describing clocks: + * + a clock input named "clk_in", whose pointer is stored in + * clk_in field of a MyDeviceState structure with callback + * clk_in_callback. + * + a clock output named "clk_out" whose pointer is stored in + * clk_out field of a MyDeviceState structure. + */ + static const ClockPortInitArray mydev_clocks =3D { + QDEV_CLOCK_IN(MyDeviceState, clk_in, clk_in_callback), + QDEV_CLOCK_OUT(MyDeviceState, clk_out), + QDEV_CLOCK_END + }; + + /* device initialization function */ + static void mydev_init(Object *obj) + { + /* cast to MyDeviceState */ + MyDeviceState *mydev =3D MYDEVICE(obj); + /* create and fill the pointer fields in the MyDeviceState */ + qdev_init_clocks(mydev, mydev_clocks); + [...] + } + +An alternative way to create a clock is to simply call +``object_new(TYPE_CLOCK)``. In that case the clock will neither be an inpu= t nor +an output of a device. After the whole QOM hieracrhy of the clock has been= set +``clock_setup_canonical_path()`` should be called. + +At creation, the period of the clock is 0: the clock is disabled. You can +change it using ``clock_set[_ns|_hz]()``. + +Note that if you are creating a clock with a fixed period which will never +change (for example the main clock source of a board), then you'll have +nothing else to do. This value will be propagated to other clocks when +connecting the clocks together and devices will fetch the right value duri= ng +the first reset. + +Retrieving clocks from a device +------------------------------- + +``qdev_get_clock_in()`` and ``dev_get_clock_out()`` are available to get t= he clock inputs or outputs of a device. For example:: + + Clock *clk =3D qdev_get_clock_in(DEVICE(mydev), "clk_in"); + +or:: + + Clock *clk =3D qdev_get_clock_out(DEVICE(mydev), "clk_out"); + +Connecting two clocks together +------------------------------ + +To connect two clocks together, use the ``clock_set_source()`` function. +Given two clocks ``clk1``, and ``clk2``, ``clock_set_source(clk2, clk1);`` +configure ``clk2`` to follow the ``clk1`` period changes. Every time ``clk= 1`` +is updated, ``clk2`` will be updated too. + +When connecting clock between devices, prefer using the +``qdev_connect_clock_in()`` function set the source of an input device clo= ck. +For example, to connect the input clock ``clk2`` of ``devB`` to the output +clock ``clk1`` of ``devA``, do:: + + qdev_connect_clock_in(devB, "clk2", qdev_get_clock_out(devA, "clk1")) + +We used ``qdev_get_clock_out()`` above, but any clock can drive an input c= lock, +even another input clock. The following diagram shows some +examples of connections. Note also that a clock can drive several other cl= ocks. + +:: + + +------------+ +--------------------------------------------------+ + | Device A | | Device B | + | | | +---------------------+ | + | | | | Device C | | + | +-------+ | | +-------+ | +-------+ +-------+ | +-------+ | + | |Clock 1|>>-->>|Clock 2|>>+-->>|Clock 3| |Clock 5|>>>>|Clock 6|>> + | | (out) | | | | (in) | | | | (in) | | (out) | | | (out) | | + | +-------+ | | +-------+ | | +-------+ +-------+ | +-------+ | + +------------+ | | +---------------------+ | + | | | + | | +--------------+ | + | | | Device D | | + | | | +-------+ | | + | +-->>|Clock 4| | | + | | | (in) | | | + | | +-------+ | | + | +--------------+ | + +--------------------------------------------------+ + +In the above example, when *Clock 1* is updated by *Device A*, three clock= s gets the new clock period value: *Clock 2*, Clock 3* and *Clock 4*. + +It is not possible to disconnect a clock or to change the clock connection +after it is done. + +Unconnected input clocks +------------------------ + +A newly created input clock is disabled (period of 0). It means the clock = will +be considered as disabled until the period is updated. If the clock remains +unconnected it will always keep its initial value of 0. If this is not the +wanted behaviour, ``clock_set()``, ``clock_set_ns()`` or ``clock_set_hz()`` +should be called on the Clock object during device instance init. For exam= ple:: + + clk =3D qdev_init_clock_in(DEVICE(dev), "clk-in", clk_in_callback, + dev); + /* set initial value to 10ns / 100MHz */ + clock_set_ns(clk, 10); + +Fetching clock frequency/period +------------------------------- + +To get the current state of a clock, the function ``clock_get()``, +``clock_get_ns()`` or ``clock_get_hz()`` must be used. + +It is also possible to register a callback on clock frequency changes. +Here is an example:: + + void clock_callback(void *opaque) { + MyDeviceState *s =3D (MyDeviceState *) opaque; + /* + * opaque may not be the device state pointer, but most + * probably it is. (It depends on what is given to the + * qdev_init_clock_in function) + */ + + /* do something with the new period */ + fprintf(stdout, "device new period is %" PRIu64 "ns\n", + clock_get_ns(dev->my_clk_input)); + } + +Changing a clock period +----------------------- + +A device can change its outputs using the ``clock_update()``, +``clock_update_ns()`` or ``clock_update_hz()`` function. It will trigger +updates on every connected input. + +For example, let's say that we have an output clock *clkout* and we have a +pointer to it in the device state because we did the following in init pha= se:: + + dev->clkout =3D qdev_init_clock_out(DEVICE(dev), "clkout"); + +Then at any time (apart from the cases listed below), it is possible to +change the clock value by doing:: + + clock_update_hz(dev->clkout, 1000 * 1000 * 1000); /* 1Ghz */ + +Because updating a clock may trigger any side effects through connected cl= ocks +and their callbacks, this operation must be done while holding the qemu io= lock. + +For the same reason, one can update clocks only when it is allowed to have +side effects on other objects. In consequence, it is forbidden: ++ during migration, ++ and in the enter phase of reset. + +Note that calling ``clock_update[_ns|_hz]()`` is equivalent to calling +``clock_set[_ns|_hz]()`` (with the same arguments) then ``clock_propagate(= )`` on +the clock. Thus, setting the clock value can be separated from triggering = the +side-effects. This is often required to factorize code to handle reset and +migration in devices. + +Aliasing clocks +--------------- + +Sometimes, one needs to forward, or inherit, a clock from another device. +Typically, when doing device composition, a device might expose a sub-devi= ce's +clock without interfering with it. +The function ``qdev_alias_clock()`` can be used to achieve this behaviour.= Note +that it is possible to expose the clock under a different name. This works= for +both inputs and outputs. + +For example, if device B is a child of device A, ``device_a_instance_init(= )`` +may do something like this:: + + void device_a_instance_init(Object *obj) + { + AState *A =3D DEVICE_A(obj); + BState *B; + /* create B object as child of A */ + [...] + qdev_alias_clock(B, "clk", A, "b_clk"); + /* + * Now A has a clock "b_clk" which is an alias to + * the clock "clk" of its child B. + */ + } + +This function does not return any clock object. The new clock has the same +direction (input or output) as the original one. This function only adds a= link +to the existing clock. In the above example, B object remains the only obj= ect +allowed to use the clock and device A must not try to change the clock per= iod +or set a callback to the clock. Here follows a diagram describing the exam= ple +with an input clock:: + + +--------------------------+ + | Device A | + | +--------------+ | + | | Device B | | + | | +-------+ | | + >>"b_clk">>>| "clk" | | | + | (in) | | (in) | | | + | | +-------+ | | + | +--------------+ | + +--------------------------+ + +Migration +--------- + +Clock state is not migrated automatically. Every device must handle its +clock migration. Alias clocks must not be migrated. + +To ensure clock states are restored correctly during migration, there is t= wo +solutions. + +Clocks states can be migrated by adding an entry into the device +vmstate description. To this purpose, the ``VMSTATE_CLOCK`` macro defines +such an entry and should be used. This is typically used to migrate an inp= ut +clock state. The following example describes it:: + + MyDeviceState { + DeviceState parent_obj; + [...] /* some fields */ + Clock *clk; + }; + + VMStateDescription my_device_vmstate =3D { + .name =3D "my_device", + .fields =3D (VMStateField[]) { + [...], /* other migrated fields */ + VMSTATE_CLOCK(clk, MyDeviceState), + VMSTATE_END_OF_LIST() + } + }; + +The second solution is to restore the clock state using information already +at our disposal. This can be used to restore output clocks states using the +device state. The functions ``clock_set[_ns|_hz]()`` can be used during the +``post_load()`` migration callback. + +When adding a clock support to an existing device, if you care about migra= tion +compatibility. To this end, you can use ``clock_set()`` in a ``pre_load()`` +function to setup a default value in case the source virtual machine does = not +send the clock state. You may also need to use a vmstate subsection. + +Care should be taken not to use ``clock_update[_ns|_hz]()`` or +``clock_propagate()`` during the whole migration procedure because it will +trigger side effects to other devices in an unknown state. diff --git a/docs/devel/index.rst b/docs/devel/index.rst index b734ba4655..35af5bf97d 100644 --- a/docs/devel/index.rst +++ b/docs/devel/index.rst @@ -26,3 +26,4 @@ Contents: bitops reset s390-dasd-ipl + clocks --=20 2.26.0 From nobody Fri May 17 06:54:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (BodyHash is different from the expected one) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1586181834737871.4282186026744; Mon, 6 Apr 2020 07:03:54 -0700 (PDT) Received: from localhost ([::1]:60618 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jLSLx-00058U-6R for importer@patchew.org; Mon, 06 Apr 2020 10:03:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54156) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jLSBl-00041b-UE for qemu-devel@nongnu.org; Mon, 06 Apr 2020 09:53:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jLSBk-0002An-Ay for qemu-devel@nongnu.org; Mon, 06 Apr 2020 09:53:21 -0400 Received: from beetle.greensocs.com ([5.135.226.135]:57096) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jLSBg-00024e-Kr; Mon, 06 Apr 2020 09:53:16 -0400 Received: from crumble.bar.greensocs.com (unknown [172.17.10.14]) by beetle.greensocs.com (Postfix) with ESMTPS id 2AC3E96F54; Mon, 6 Apr 2020 13:53:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1586181195; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=w2tbUoohONT12BkgoX/7zs5Zt2Dh5babDEcWSQSxGdE=; b=Ubvw8N/o7Mt4kGY93RfcxKslQaIKxTRintMeR/jEGCtyLsVW8WCBqQVjBLhdEx3S3pv1F0 L/OuJM1Vcb6aVd1vXYZc+++wuMWNhMhdfZJ6BJycU234amV7qK2tkBLjZ75JKDeRBApNdU HLySdIBVpeOky8haQFbN5xV7ZfREPao= From: Damien Hedde To: qemu-devel@nongnu.org Subject: [PATCH v9 6/9] hw/misc/zynq_slcr: add clock generation for uarts Date: Mon, 6 Apr 2020 15:52:48 +0200 Message-Id: <20200406135251.157596-7-damien.hedde@greensocs.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200406135251.157596-1-damien.hedde@greensocs.com> References: <20200406135251.157596-1-damien.hedde@greensocs.com> MIME-Version: 1.0 ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1586181195; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=w2tbUoohONT12BkgoX/7zs5Zt2Dh5babDEcWSQSxGdE=; b=JFlLXO7QR/k9v4ie/Ub5k4pE7kwa9Dr6vCtbOs7NSeqKvjWs7OpyPU3DLXfn+RQqkDxScY /BZPEUF7/gi3y4WmobhYrT1lXF/KBFVX67TU1ySHO69YsVGb0sg9raC2QwDCroL28yGxsK CY4lLSWM3x9XIAKk1bd60WQJHT40ynM= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1586181195; a=rsa-sha256; cv=none; b=3QUR/lmlL01rBEX0vY0mL8g7Xjt8m2ZNsj7kDBg5pf8x8HMrjQ/Q17ju6hxSXT3YtKS9c2 HFcG1M//jdS8vungfq0ShzQv97GLJDZt/fwtO1h1nLKevn0P9A1KepT1edwqfe0ONV8Xyn claJDc7rdTG9cOfLlad+w5eoAkb6cWk= ARC-Authentication-Results: i=1; beetle.greensocs.com; none X-Spam: Yes Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 5.135.226.135 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , peter.maydell@linaro.org, "Edgar E . Iglesias" , berrange@redhat.com, ehabkost@redhat.com, pbonzini@redhat.com, alistair@alistair23.me, mark.burton@greensocs.com, qemu-arm@nongnu.org, Alistair Francis , marcandre.lureau@redhat.com, edgar.iglesias@gmail.com, philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add some clocks to zynq_slcr + the main input clock (ps_clk) + the reference clock outputs for each uart (uart0 & 1) This commit also transitional the slcr to multi-phase reset as it is required to initialize the clocks correctly. The clock frequencies are computed using the internal pll & uart configurat= ion registers and the input ps_clk frequency. Signed-off-by: Damien Hedde Reviewed-by: Edgar E. Iglesias Acked-by: Alistair Francis --- v7: + handle migration of input clock + update ClockIn/ClockOut types + comments correction/precision (Peter) --- hw/misc/zynq_slcr.c | 172 ++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 168 insertions(+), 4 deletions(-) diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index b9a38272d9..f7472d1f3c 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -22,6 +22,7 @@ #include "qemu/log.h" #include "qemu/module.h" #include "hw/registerfields.h" +#include "hw/qdev-clock.h" =20 #ifndef ZYNQ_SLCR_ERR_DEBUG #define ZYNQ_SLCR_ERR_DEBUG 0 @@ -45,6 +46,12 @@ REG32(LOCKSTA, 0x00c) REG32(ARM_PLL_CTRL, 0x100) REG32(DDR_PLL_CTRL, 0x104) REG32(IO_PLL_CTRL, 0x108) +/* fields for [ARM|DDR|IO]_PLL_CTRL registers */ + FIELD(xxx_PLL_CTRL, PLL_RESET, 0, 1) + FIELD(xxx_PLL_CTRL, PLL_PWRDWN, 1, 1) + FIELD(xxx_PLL_CTRL, PLL_BYPASS_QUAL, 3, 1) + FIELD(xxx_PLL_CTRL, PLL_BYPASS_FORCE, 4, 1) + FIELD(xxx_PLL_CTRL, PLL_FPDIV, 12, 7) REG32(PLL_STATUS, 0x10c) REG32(ARM_PLL_CFG, 0x110) REG32(DDR_PLL_CFG, 0x114) @@ -64,6 +71,10 @@ REG32(SMC_CLK_CTRL, 0x148) REG32(LQSPI_CLK_CTRL, 0x14c) REG32(SDIO_CLK_CTRL, 0x150) REG32(UART_CLK_CTRL, 0x154) + FIELD(UART_CLK_CTRL, CLKACT0, 0, 1) + FIELD(UART_CLK_CTRL, CLKACT1, 1, 1) + FIELD(UART_CLK_CTRL, SRCSEL, 4, 2) + FIELD(UART_CLK_CTRL, DIVISOR, 8, 6) REG32(SPI_CLK_CTRL, 0x158) REG32(CAN_CLK_CTRL, 0x15c) REG32(CAN_MIOCLK_CTRL, 0x160) @@ -179,11 +190,127 @@ typedef struct ZynqSLCRState { MemoryRegion iomem; =20 uint32_t regs[ZYNQ_SLCR_NUM_REGS]; + + Clock *ps_clk; + Clock *uart0_ref_clk; + Clock *uart1_ref_clk; } ZynqSLCRState; =20 -static void zynq_slcr_reset(DeviceState *d) +/* + * return the output frequency of ARM/DDR/IO pll + * using input frequency and PLL_CTRL register + */ +static uint64_t zynq_slcr_compute_pll(uint64_t input, uint32_t ctrl_reg) { - ZynqSLCRState *s =3D ZYNQ_SLCR(d); + uint32_t mult =3D ((ctrl_reg & R_xxx_PLL_CTRL_PLL_FPDIV_MASK) >> + R_xxx_PLL_CTRL_PLL_FPDIV_SHIFT); + + /* first, check if pll is bypassed */ + if (ctrl_reg & R_xxx_PLL_CTRL_PLL_BYPASS_FORCE_MASK) { + return input; + } + + /* is pll disabled ? */ + if (ctrl_reg & (R_xxx_PLL_CTRL_PLL_RESET_MASK | + R_xxx_PLL_CTRL_PLL_PWRDWN_MASK)) { + return 0; + } + + /* frequency multiplier -> period division */ + return input / mult; +} + +/* + * return the output period of a clock given: + * + the periods in an array corresponding to input mux selector + * + the register xxx_CLK_CTRL value + * + enable bit index in ctrl register + * + * This function makes the assumption that the ctrl_reg value is organized= as + * follows: + * + bits[13:8] clock frequency divisor + * + bits[5:4] clock mux selector (index in array) + * + bits[index] clock enable + */ +static uint64_t zynq_slcr_compute_clock(const uint64_t periods[], + uint32_t ctrl_reg, + unsigned index) +{ + uint32_t srcsel =3D extract32(ctrl_reg, 4, 2); /* bits [5:4] */ + uint32_t divisor =3D extract32(ctrl_reg, 8, 6); /* bits [13:8] */ + + /* first, check if clock is disabled */ + if (((ctrl_reg >> index) & 1u) =3D=3D 0) { + return 0; + } + + /* + * according to the Zynq technical ref. manual UG585 v1.12.2 in + * Clocks chapter, section 25.10.1 page 705: + * "The 6-bit divider provides a divide range of 1 to 63" + * We follow here what is implemented in linux kernel and consider + * the 0 value as a bypass (no division). + */ + /* frequency divisor -> period multiplication */ + return periods[srcsel] * (divisor ? divisor : 1u); +} + +/* + * macro helper around zynq_slcr_compute_clock to avoid repeating + * the register name. + */ +#define ZYNQ_COMPUTE_CLK(state, plls, reg, enable_field) \ + zynq_slcr_compute_clock((plls), (state)->regs[reg], \ + reg ## _ ## enable_field ## _SHIFT) + +/** + * Compute and set the ouputs clocks periods. + * But do not propagate them further. Connected clocks + * will not receive any updates (See zynq_slcr_compute_clocks()) + */ +static void zynq_slcr_compute_clocks(ZynqSLCRState *s) +{ + uint64_t ps_clk =3D clock_get(s->ps_clk); + + /* consider outputs clocks are disabled while in reset */ + if (device_is_in_reset(DEVICE(s))) { + ps_clk =3D 0; + } + + uint64_t io_pll =3D zynq_slcr_compute_pll(ps_clk, s->regs[R_IO_PLL_CTR= L]); + uint64_t arm_pll =3D zynq_slcr_compute_pll(ps_clk, s->regs[R_ARM_PLL_C= TRL]); + uint64_t ddr_pll =3D zynq_slcr_compute_pll(ps_clk, s->regs[R_DDR_PLL_C= TRL]); + + uint64_t uart_mux[4] =3D {io_pll, io_pll, arm_pll, ddr_pll}; + + /* compute uartX reference clocks */ + clock_set(s->uart0_ref_clk, + ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT0)); + clock_set(s->uart1_ref_clk, + ZYNQ_COMPUTE_CLK(s, uart_mux, R_UART_CLK_CTRL, CLKACT1)); +} + +/** + * Propagate the outputs clocks. + * zynq_slcr_compute_clocks() should have been called before + * to configure them. + */ +static void zynq_slcr_propagate_clocks(ZynqSLCRState *s) +{ + clock_propagate(s->uart0_ref_clk); + clock_propagate(s->uart1_ref_clk); +} + +static void zynq_slcr_ps_clk_callback(void *opaque) +{ + ZynqSLCRState *s =3D (ZynqSLCRState *) opaque; + zynq_slcr_compute_clocks(s); + zynq_slcr_propagate_clocks(s); +} + +static void zynq_slcr_reset_init(Object *obj, ResetType type) +{ + ZynqSLCRState *s =3D ZYNQ_SLCR(obj); int i; =20 DB_PRINT("RESET\n"); @@ -277,6 +404,23 @@ static void zynq_slcr_reset(DeviceState *d) s->regs[R_DDRIOB + 12] =3D 0x00000021; } =20 +static void zynq_slcr_reset_hold(Object *obj) +{ + ZynqSLCRState *s =3D ZYNQ_SLCR(obj); + + /* will disable all output clocks */ + zynq_slcr_compute_clocks(s); + zynq_slcr_propagate_clocks(s); +} + +static void zynq_slcr_reset_exit(Object *obj) +{ + ZynqSLCRState *s =3D ZYNQ_SLCR(obj); + + /* will compute output clocks according to ps_clk and registers */ + zynq_slcr_compute_clocks(s); + zynq_slcr_propagate_clocks(s); +} =20 static bool zynq_slcr_check_offset(hwaddr offset, bool rnw) { @@ -409,6 +553,13 @@ static void zynq_slcr_write(void *opaque, hwaddr offse= t, qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); } break; + case R_IO_PLL_CTRL: + case R_ARM_PLL_CTRL: + case R_DDR_PLL_CTRL: + case R_UART_CLK_CTRL: + zynq_slcr_compute_clocks(s); + zynq_slcr_propagate_clocks(s); + break; } } =20 @@ -418,6 +569,13 @@ static const MemoryRegionOps slcr_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 +static const ClockPortInitArray zynq_slcr_clocks =3D { + QDEV_CLOCK_IN(ZynqSLCRState, ps_clk, zynq_slcr_ps_clk_callback), + QDEV_CLOCK_OUT(ZynqSLCRState, uart0_ref_clk), + QDEV_CLOCK_OUT(ZynqSLCRState, uart1_ref_clk), + QDEV_CLOCK_END +}; + static void zynq_slcr_init(Object *obj) { ZynqSLCRState *s =3D ZYNQ_SLCR(obj); @@ -425,14 +583,17 @@ static void zynq_slcr_init(Object *obj) memory_region_init_io(&s->iomem, obj, &slcr_ops, s, "slcr", ZYNQ_SLCR_MMIO_SIZE); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->iomem); + + qdev_init_clocks(DEVICE(obj), zynq_slcr_clocks); } =20 static const VMStateDescription vmstate_zynq_slcr =3D { .name =3D "zynq_slcr", - .version_id =3D 2, + .version_id =3D 3, .minimum_version_id =3D 2, .fields =3D (VMStateField[]) { VMSTATE_UINT32_ARRAY(regs, ZynqSLCRState, ZYNQ_SLCR_NUM_REGS), + VMSTATE_CLOCK_V(ps_clk, ZynqSLCRState, 3), VMSTATE_END_OF_LIST() } }; @@ -440,9 +601,12 @@ static const VMStateDescription vmstate_zynq_slcr =3D { static void zynq_slcr_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 dc->vmsd =3D &vmstate_zynq_slcr; - dc->reset =3D zynq_slcr_reset; + rc->phases.enter =3D zynq_slcr_reset_init; + rc->phases.hold =3D zynq_slcr_reset_hold; + rc->phases.exit =3D zynq_slcr_reset_exit; } =20 static const TypeInfo zynq_slcr_info =3D { --=20 2.26.0 From nobody Fri May 17 06:54:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (BodyHash is different from the expected one) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1586182284581328.4863619733426; Mon, 6 Apr 2020 07:11:24 -0700 (PDT) Received: from localhost ([::1]:60754 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jLSTD-0003bk-1Y for importer@patchew.org; Mon, 06 Apr 2020 10:11:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54209) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jLSBn-00044H-SV for qemu-devel@nongnu.org; Mon, 06 Apr 2020 09:53:25 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jLSBm-0002DC-4W for qemu-devel@nongnu.org; Mon, 06 Apr 2020 09:53:23 -0400 Received: from beetle.greensocs.com ([5.135.226.135]:57118) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jLSBh-00025U-AU; Mon, 06 Apr 2020 09:53:17 -0400 Received: from crumble.bar.greensocs.com (unknown [172.17.10.14]) by beetle.greensocs.com (Postfix) with ESMTPS id DDCA896F56; Mon, 6 Apr 2020 13:53:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1586181196; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+u4DTtVtAfEAsYJ95xI5vzqpIQ4B1AsHwuQZ1++Yn54=; b=1DFbSempHL2bfzGwryC8uABTS8jIvduusFOh9Vox1FiBqXpl+BB266tyPV+ZbgR82UCrIi fHOM+hVWNi/QfFGmPIVcOrGCDvHbpLH/PzPl4x1wju3HBYdvt4owKJKWPrN1nMI+Eah02c zkzd5tJ2lGgPUAGKCClkr0t9oquiESU= From: Damien Hedde To: qemu-devel@nongnu.org Subject: [PATCH v9 7/9] hw/char/cadence_uart: add clock support Date: Mon, 6 Apr 2020 15:52:49 +0200 Message-Id: <20200406135251.157596-8-damien.hedde@greensocs.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200406135251.157596-1-damien.hedde@greensocs.com> References: <20200406135251.157596-1-damien.hedde@greensocs.com> MIME-Version: 1.0 ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1586181196; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+u4DTtVtAfEAsYJ95xI5vzqpIQ4B1AsHwuQZ1++Yn54=; b=6uwgapCCOGqkIN8CAJ9GD2AOasFJ+pZG6oZgqajg2+Fzq1R44m1WMTO2cOWOAwF3CepjXp +kzqQ6kdYvq2755tPa/2gkDpnwoORIrzOOjYTzWnn0s3DbZFbrbAvkJz0sJvO7ELCvzw2s /ekzqt16fXxayEHbcPWz2AmtvQdBH8o= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1586181196; a=rsa-sha256; cv=none; b=BL9y72wvgHUUlk8f3DKR69xYjiVNCF3O8FVnE655fRbKa8+hA61FExgAQmuipo9OibcLY/ 7joxks3J7/m0LNUoCFHEOBRHMzQ+rZ7VByKaZcSYQSjCP3yM5oCixQAi9J0ejDFKsk0iGa CG0Acv1SrWVNuFS8gfrhu2/my4dzDHE= ARC-Authentication-Results: i=1; beetle.greensocs.com; none X-Spam: Yes Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 5.135.226.135 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , peter.maydell@linaro.org, "Edgar E . Iglesias" , berrange@redhat.com, ehabkost@redhat.com, pbonzini@redhat.com, alistair@alistair23.me, mark.burton@greensocs.com, qemu-arm@nongnu.org, Alistair Francis , marcandre.lureau@redhat.com, edgar.iglesias@gmail.com, philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Switch the cadence uart to multi-phase reset and add the reference clock input. The input clock frequency is added to the migration structure. The reference clock controls the baudrate generation. If it disabled, any input characters and events are ignored. If this clock remains unconnected, the uart behaves as before (it default to a 50MHz ref clock). Signed-off-by: Damien Hedde Reviewed-by: Edgar E. Iglesias Reviewed-by: Alistair Francis --- v7: + update ClockIn/ClockOut types + update due to resettable changes + use a versioned field instead subsection in vmstate --- include/hw/char/cadence_uart.h | 1 + hw/char/cadence_uart.c | 73 +++++++++++++++++++++++++++++----- hw/char/trace-events | 3 ++ 3 files changed, 67 insertions(+), 10 deletions(-) diff --git a/include/hw/char/cadence_uart.h b/include/hw/char/cadence_uart.h index 47cec956c4..2a179a572f 100644 --- a/include/hw/char/cadence_uart.h +++ b/include/hw/char/cadence_uart.h @@ -49,6 +49,7 @@ typedef struct { CharBackend chr; qemu_irq irq; QEMUTimer *fifo_trigger_handle; + Clock *refclk; } CadenceUARTState; =20 static inline DeviceState *cadence_uart_create(hwaddr addr, diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index 22e47972f1..e196906c92 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -31,6 +31,8 @@ #include "qemu/module.h" #include "hw/char/cadence_uart.h" #include "hw/irq.h" +#include "hw/qdev-clock.h" +#include "trace.h" =20 #ifdef CADENCE_UART_ERR_DEBUG #define DB_PRINT(...) do { \ @@ -97,7 +99,7 @@ #define LOCAL_LOOPBACK (0x2 << UART_MR_CHMODE_SH) #define REMOTE_LOOPBACK (0x3 << UART_MR_CHMODE_SH) =20 -#define UART_INPUT_CLK 50000000 +#define UART_DEFAULT_REF_CLK (50 * 1000 * 1000) =20 #define R_CR (0x00/4) #define R_MR (0x04/4) @@ -171,12 +173,15 @@ static void uart_send_breaks(CadenceUARTState *s) static void uart_parameters_setup(CadenceUARTState *s) { QEMUSerialSetParams ssp; - unsigned int baud_rate, packet_size; + unsigned int baud_rate, packet_size, input_clk; + input_clk =3D clock_get_hz(s->refclk); =20 - baud_rate =3D (s->r[R_MR] & UART_MR_CLKS) ? - UART_INPUT_CLK / 8 : UART_INPUT_CLK; + baud_rate =3D (s->r[R_MR] & UART_MR_CLKS) ? input_clk / 8 : input_clk; + baud_rate /=3D (s->r[R_BRGR] * (s->r[R_BDIV] + 1)); + trace_cadence_uart_baudrate(baud_rate); + + ssp.speed =3D baud_rate; =20 - ssp.speed =3D baud_rate / (s->r[R_BRGR] * (s->r[R_BDIV] + 1)); packet_size =3D 1; =20 switch (s->r[R_MR] & UART_MR_PAR) { @@ -215,6 +220,13 @@ static void uart_parameters_setup(CadenceUARTState *s) } =20 packet_size +=3D ssp.data_bits + ssp.stop_bits; + if (ssp.speed =3D=3D 0) { + /* + * Avoid division-by-zero below. + * TODO: find something better + */ + ssp.speed =3D 1; + } s->char_tx_time =3D (NANOSECONDS_PER_SECOND / ssp.speed) * packet_size; qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_PARAMS, &ssp); } @@ -340,6 +352,11 @@ static void uart_receive(void *opaque, const uint8_t *= buf, int size) CadenceUARTState *s =3D opaque; uint32_t ch_mode =3D s->r[R_MR] & UART_MR_CHMODE; =20 + /* ignore characters when unclocked or in reset */ + if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) { + return; + } + if (ch_mode =3D=3D NORMAL_MODE || ch_mode =3D=3D ECHO_MODE) { uart_write_rx_fifo(opaque, buf, size); } @@ -353,6 +370,11 @@ static void uart_event(void *opaque, QEMUChrEvent even= t) CadenceUARTState *s =3D opaque; uint8_t buf =3D '\0'; =20 + /* ignore characters when unclocked or in reset */ + if (!clock_is_enabled(s->refclk) || device_is_in_reset(DEVICE(s))) { + return; + } + if (event =3D=3D CHR_EVENT_BREAK) { uart_write_rx_fifo(opaque, &buf, 1); } @@ -462,9 +484,9 @@ static const MemoryRegionOps uart_ops =3D { .endianness =3D DEVICE_NATIVE_ENDIAN, }; =20 -static void cadence_uart_reset(DeviceState *dev) +static void cadence_uart_reset_init(Object *obj, ResetType type) { - CadenceUARTState *s =3D CADENCE_UART(dev); + CadenceUARTState *s =3D CADENCE_UART(obj); =20 s->r[R_CR] =3D 0x00000128; s->r[R_IMR] =3D 0; @@ -473,6 +495,11 @@ static void cadence_uart_reset(DeviceState *dev) s->r[R_BRGR] =3D 0x0000028B; s->r[R_BDIV] =3D 0x0000000F; s->r[R_TTRIG] =3D 0x00000020; +} + +static void cadence_uart_reset_hold(Object *obj) +{ + CadenceUARTState *s =3D CADENCE_UART(obj); =20 uart_rx_reset(s); uart_tx_reset(s); @@ -491,6 +518,14 @@ static void cadence_uart_realize(DeviceState *dev, Err= or **errp) uart_event, NULL, s, NULL, true); } =20 +static void cadence_uart_refclk_update(void *opaque) +{ + CadenceUARTState *s =3D opaque; + + /* recompute uart's speed on clock change */ + uart_parameters_setup(s); +} + static void cadence_uart_init(Object *obj) { SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); @@ -500,9 +535,23 @@ static void cadence_uart_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem); sysbus_init_irq(sbd, &s->irq); =20 + s->refclk =3D qdev_init_clock_in(DEVICE(obj), "refclk", + cadence_uart_refclk_update, s); + /* initialize the frequency in case the clock remains unconnected */ + clock_set_hz(s->refclk, UART_DEFAULT_REF_CLK); + s->char_tx_time =3D (NANOSECONDS_PER_SECOND / 9600) * 10; } =20 +static int cadence_uart_pre_load(void *opaque) +{ + CadenceUARTState *s =3D opaque; + + /* the frequency will be overriden if the refclk field is present */ + clock_set_hz(s->refclk, UART_DEFAULT_REF_CLK); + return 0; +} + static int cadence_uart_post_load(void *opaque, int version_id) { CadenceUARTState *s =3D opaque; @@ -521,8 +570,9 @@ static int cadence_uart_post_load(void *opaque, int ver= sion_id) =20 static const VMStateDescription vmstate_cadence_uart =3D { .name =3D "cadence_uart", - .version_id =3D 2, + .version_id =3D 3, .minimum_version_id =3D 2, + .pre_load =3D cadence_uart_pre_load, .post_load =3D cadence_uart_post_load, .fields =3D (VMStateField[]) { VMSTATE_UINT32_ARRAY(r, CadenceUARTState, CADENCE_UART_R_MAX), @@ -534,8 +584,9 @@ static const VMStateDescription vmstate_cadence_uart = =3D { VMSTATE_UINT32(tx_count, CadenceUARTState), VMSTATE_UINT32(rx_wpos, CadenceUARTState), VMSTATE_TIMER_PTR(fifo_trigger_handle, CadenceUARTState), + VMSTATE_CLOCK_V(refclk, CadenceUARTState, 3), VMSTATE_END_OF_LIST() - } + }, }; =20 static Property cadence_uart_properties[] =3D { @@ -546,10 +597,12 @@ static Property cadence_uart_properties[] =3D { static void cadence_uart_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 dc->realize =3D cadence_uart_realize; dc->vmsd =3D &vmstate_cadence_uart; - dc->reset =3D cadence_uart_reset; + rc->phases.enter =3D cadence_uart_reset_init; + rc->phases.hold =3D cadence_uart_reset_hold; device_class_set_props(dc, cadence_uart_properties); } =20 diff --git a/hw/char/trace-events b/hw/char/trace-events index 6f938301d9..d20eafd56f 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -97,3 +97,6 @@ exynos_uart_wo_read(uint32_t channel, const char *name, u= int32_t reg) "UART%d: T exynos_uart_rxsize(uint32_t channel, uint32_t size) "UART%d: Rx FIFO size:= %d" exynos_uart_channel_error(uint32_t channel) "Wrong UART channel number: %d" exynos_uart_rx_timeout(uint32_t channel, uint32_t stat, uint32_t intsp) "U= ART%d: Rx timeout stat=3D0x%x intsp=3D0x%x" + +# hw/char/cadence_uart.c +cadence_uart_baudrate(unsigned baudrate) "baudrate %u" --=20 2.26.0 From nobody Fri May 17 06:54:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; arc=fail (BodyHash is different from the expected one) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1586182044227523.6267095483307; Mon, 6 Apr 2020 07:07:24 -0700 (PDT) Received: from localhost ([::1]:60686 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jLSPK-00086P-P2 for importer@patchew.org; Mon, 06 Apr 2020 10:07:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54173) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jLSBm-00042R-LI for qemu-devel@nongnu.org; Mon, 06 Apr 2020 09:53:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jLSBl-0002CU-Cs for qemu-devel@nongnu.org; Mon, 06 Apr 2020 09:53:22 -0400 Received: from beetle.greensocs.com ([5.135.226.135]:57132) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jLSBi-00026N-2I; Mon, 06 Apr 2020 09:53:18 -0400 Received: from crumble.bar.greensocs.com (unknown [172.17.10.14]) by beetle.greensocs.com (Postfix) with ESMTPS id 9685F96F57; Mon, 6 Apr 2020 13:53:16 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1586181197; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=C0ooB5GiyOIOs5QGTuAebY7o8e/UFndNW9ySnoGuca8=; b=pzjC2Ao2TtO9oFrX2Jaqk41ct0/16yJQC73hbomoaNLFtpuaQKzCAyG4qy4OA1wRduP0AY TLm61tkCK/vFxl1cQhfYq9jZxhV7sodD9waBce/nCiiE0E1Vp1Ne4PYz3BJ4a61HIZVtTY 4i+owzfub2Gy2EC/ucNIL0upOSfaiZo= From: Damien Hedde To: qemu-devel@nongnu.org Subject: [PATCH v9 8/9] hw/arm/xilinx_zynq: connect uart clocks to slcr Date: Mon, 6 Apr 2020 15:52:50 +0200 Message-Id: <20200406135251.157596-9-damien.hedde@greensocs.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200406135251.157596-1-damien.hedde@greensocs.com> References: <20200406135251.157596-1-damien.hedde@greensocs.com> MIME-Version: 1.0 ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1586181197; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=C0ooB5GiyOIOs5QGTuAebY7o8e/UFndNW9ySnoGuca8=; b=ycVgJmGhj++DN1PghVrE7qDH01rQbGiTTjIjJCFbsQLHOociZtxHjqfU4Zr+VcLDRaFy0X 45YlvhakHc7eh1drSiYucuH1qtsYDkT/z1OzNhvJlbJmnL6cX4LW4CTMtXe6rNjirhUuvM 3svI8Qci/XYyHkSzQp3m9SCr2dDQtFo= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1586181197; a=rsa-sha256; cv=none; b=ANq1FAeiCoUmdsiOapjX3qwSZyAeQHuCf2AG0NdLbdEGLyJT3KZ/hPdL+rOuqAqn7lBhvw fG61vxQihx1nusLLq36wOPqpsAgh3DCuqFE/PqoIM0t7AYyh4El31zRgpMT4F5UpsTvVsj ineKfij4IOLsO6K+tlgCLynCqaAbhwM= ARC-Authentication-Results: i=1; beetle.greensocs.com; none X-Spam: Yes Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 5.135.226.135 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , peter.maydell@linaro.org, "Edgar E . Iglesias" , berrange@redhat.com, ehabkost@redhat.com, pbonzini@redhat.com, alistair@alistair23.me, mark.burton@greensocs.com, qemu-arm@nongnu.org, Alistair Francis , marcandre.lureau@redhat.com, edgar.iglesias@gmail.com, philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Add the connection between the slcr's output clocks and the uarts inputs. Also add the main board clock 'ps_clk', which is hard-coded to 33.33MHz (the default frequency). This clock is used to feed the slcr's input clock. Signed-off-by: Damien Hedde Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias --- v7 + update ClockIn/ClockOut types + simplify the ps_clk frequency init --- hw/arm/xilinx_zynq.c | 57 +++++++++++++++++++++++++++++++++++++------- 1 file changed, 49 insertions(+), 8 deletions(-) diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 571cdcd599..91b498dd5d 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -35,6 +35,15 @@ #include "hw/char/cadence_uart.h" #include "hw/net/cadence_gem.h" #include "hw/cpu/a9mpcore.h" +#include "hw/qdev-clock.h" +#include "sysemu/reset.h" + +#define TYPE_ZYNQ_MACHINE MACHINE_TYPE_NAME("xilinx-zynq-a9") +#define ZYNQ_MACHINE(obj) \ + OBJECT_CHECK(ZynqMachineState, (obj), TYPE_ZYNQ_MACHINE) + +/* board base frequency: 33.333333 MHz */ +#define PS_CLK_FREQUENCY (100 * 1000 * 1000 / 3) =20 #define NUM_SPI_FLASHES 4 #define NUM_QSPI_FLASHES 2 @@ -75,6 +84,11 @@ static const int dma_irqs[8] =3D { 0xe3401000 + ARMV7_IMM16(extract32((val), 16, 16)), /* movt r1 ... */ \ 0xe5801000 + (addr) =20 +typedef struct ZynqMachineState { + MachineState parent; + Clock *ps_clk; +} ZynqMachineState; + static void zynq_write_board_setup(ARMCPU *cpu, const struct arm_boot_info *info) { @@ -159,10 +173,11 @@ static inline void zynq_init_spi_flashes(uint32_t bas= e_addr, qemu_irq irq, =20 static void zynq_init(MachineState *machine) { + ZynqMachineState *zynq_machine =3D ZYNQ_MACHINE(machine); ARMCPU *cpu; MemoryRegion *address_space_mem =3D get_system_memory(); MemoryRegion *ocm_ram =3D g_new(MemoryRegion, 1); - DeviceState *dev; + DeviceState *dev, *slcr; SysBusDevice *busdev; qemu_irq pic[64]; int n; @@ -206,9 +221,18 @@ static void zynq_init(MachineState *machine) 1, 0x0066, 0x0022, 0x0000, 0x0000, 0x0555, 0x2aa, 0); =20 - dev =3D qdev_create(NULL, "xilinx,zynq_slcr"); - qdev_init_nofail(dev); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xF8000000); + /* Create slcr, keep a pointer to connect clocks */ + slcr =3D qdev_create(NULL, "xilinx,zynq_slcr"); + qdev_init_nofail(slcr); + sysbus_mmio_map(SYS_BUS_DEVICE(slcr), 0, 0xF8000000); + + /* Create the main clock source, and feed slcr with it */ + zynq_machine->ps_clk =3D CLOCK(object_new(TYPE_CLOCK)); + object_property_add_child(OBJECT(zynq_machine), "ps_clk", + OBJECT(zynq_machine->ps_clk), &error_abort); + object_unref(OBJECT(zynq_machine->ps_clk)); + clock_set_hz(zynq_machine->ps_clk, PS_CLK_FREQUENCY); + qdev_connect_clock_in(slcr, "ps_clk", zynq_machine->ps_clk); =20 dev =3D qdev_create(NULL, TYPE_A9MPCORE_PRIV); qdev_prop_set_uint32(dev, "num-cpu", 1); @@ -229,8 +253,12 @@ static void zynq_init(MachineState *machine) sysbus_create_simple(TYPE_CHIPIDEA, 0xE0002000, pic[53 - IRQ_OFFSET]); sysbus_create_simple(TYPE_CHIPIDEA, 0xE0003000, pic[76 - IRQ_OFFSET]); =20 - cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_hd(0)); - cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_hd(1)); + dev =3D cadence_uart_create(0xE0000000, pic[59 - IRQ_OFFSET], serial_h= d(0)); + qdev_connect_clock_in(dev, "refclk", + qdev_get_clock_out(slcr, "uart0_ref_clk")); + dev =3D cadence_uart_create(0xE0001000, pic[82 - IRQ_OFFSET], serial_h= d(1)); + qdev_connect_clock_in(dev, "refclk", + qdev_get_clock_out(slcr, "uart1_ref_clk")); =20 sysbus_create_varargs("cadence_ttc", 0xF8001000, pic[42-IRQ_OFFSET], pic[43-IRQ_OFFSET], pic[44-IRQ_OFFSET], NU= LL); @@ -308,8 +336,9 @@ static void zynq_init(MachineState *machine) arm_load_kernel(ARM_CPU(first_cpu), machine, &zynq_binfo); } =20 -static void zynq_machine_init(MachineClass *mc) +static void zynq_machine_class_init(ObjectClass *oc, void *data) { + MachineClass *mc =3D MACHINE_CLASS(oc); mc->desc =3D "Xilinx Zynq Platform Baseboard for Cortex-A9"; mc->init =3D zynq_init; mc->max_cpus =3D 1; @@ -319,4 +348,16 @@ static void zynq_machine_init(MachineClass *mc) mc->default_ram_id =3D "zynq.ext_ram"; } =20 -DEFINE_MACHINE("xilinx-zynq-a9", zynq_machine_init) +static const TypeInfo zynq_machine_type =3D { + .name =3D TYPE_ZYNQ_MACHINE, + .parent =3D TYPE_MACHINE, + .class_init =3D zynq_machine_class_init, + .instance_size =3D sizeof(ZynqMachineState), +}; + +static void zynq_machine_register_types(void) +{ + type_register_static(&zynq_machine_type); +} + +type_init(zynq_machine_register_types) --=20 2.26.0 From nobody Fri May 17 06:54:13 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Mon, 06 Apr 2020 09:53:22 -0400 Received: from beetle.greensocs.com ([5.135.226.135]:57150) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jLSBi-00027G-Qq; Mon, 06 Apr 2020 09:53:19 -0400 Received: from crumble.bar.greensocs.com (unknown [172.17.10.14]) by beetle.greensocs.com (Postfix) with ESMTPS id 4F68896F58; Mon, 6 Apr 2020 13:53:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1586181197; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=LSG/QpD1xqo/C6MQOGaRFTgH86+yW5uNIUzQ2andGQk=; b=DpAvFuYyp6/Zj8DXDaj0LWWey/wKffnlF15Do7BcjiHjnRPrPPkyCX9rSnFcrlC6tLLI1e a72PY47RxCRhMk72o+Nx//DWAdmQNa+dwQiVJ1LKD7xx7Ix21nQHglJKQSRM5od4s1c8KZ WaDbTQliYZhb4imHLe7AzW+6ND1VLOU= From: Damien Hedde To: qemu-devel@nongnu.org Subject: [PATCH v9 9/9] qdev-monitor: print the device's clock with info qtree Date: Mon, 6 Apr 2020 15:52:51 +0200 Message-Id: <20200406135251.157596-10-damien.hedde@greensocs.com> X-Mailer: git-send-email 2.26.0 In-Reply-To: <20200406135251.157596-1-damien.hedde@greensocs.com> References: <20200406135251.157596-1-damien.hedde@greensocs.com> MIME-Version: 1.0 ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1586181197; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=LSG/QpD1xqo/C6MQOGaRFTgH86+yW5uNIUzQ2andGQk=; b=TNiQbGa8DyiWfoxtZ+Y7ALFB2zUkwmiuEgiBH/9nRIH3u014NTlJST9/2yt06DRfSUcCP6 K7hGbMcwMEHCTskNq3W+3r1B6hvLBv5ruFubFi1wadJlUh0jZKamKv2Re0N312RtPhnJf5 xvh98UcFLi4wcJTJ2EqyPHPCaFF+9L4= ARC-Seal: i=1; s=mail; d=greensocs.com; t=1586181197; a=rsa-sha256; cv=none; b=rsoI97DSIWFUXxIgIO+apK3O1wMsvmJXjMh/wK62zdHy7JQc8371cFaCBjoBNjv16M/3T3 k7JY/U5+SXKpfXtgAljTdvLZC7S8LxXjqj2rCobsPh2HyFOToAMcs+ujyU3i+foxnIT219 L30zOxWP/rPwhE3Yn5n4NgZHkV774sI= ARC-Authentication-Results: i=1; beetle.greensocs.com; none Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 5.135.226.135 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , peter.maydell@linaro.org, "Edgar E . Iglesias" , berrange@redhat.com, ehabkost@redhat.com, pbonzini@redhat.com, alistair@alistair23.me, mark.burton@greensocs.com, qemu-arm@nongnu.org, Alistair Francis , marcandre.lureau@redhat.com, edgar.iglesias@gmail.com, philmd@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" This prints the clocks attached to a DeviceState when using "info qtree" monitor command. For every clock, it displays the direction, the name and if the clock is forwarded. For input clock, it displays also the frequency. This is based on the original work of Frederic Konrad. Here follows a sample of `info qtree` output on xilinx_zynq machine after linux boot with only one uart clocked: > bus: main-system-bus > type System > [...] > dev: cadence_uart, id "" > gpio-out "sysbus-irq" 1 > clock-in "refclk" freq_hz=3D0.000000e+00 > chardev =3D "" > mmio 00000000e0001000/0000000000001000 > dev: cadence_uart, id "" > gpio-out "sysbus-irq" 1 > clock-in "refclk" freq_hz=3D1.375661e+07 > chardev =3D "serial0" > mmio 00000000e0000000/0000000000001000 > [...] > dev: xilinx,zynq_slcr, id "" > clock-out "uart1_ref_clk" freq_hz=3D0.000000e+00 > clock-out "uart0_ref_clk" freq_hz=3D1.375661e+07 > clock-in "ps_clk" freq_hz=3D3.333333e+07 > mmio 00000000f8000000/0000000000001000 Signed-off-by: Damien Hedde Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Peter Maydell Reviewed-by: Alistair Francis Reviewed-by: Edgar E. Iglesias --- v7: + print output clocks frequencies too + add sample of qtree message above + display frequencies in floating-point --- qdev-monitor.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/qdev-monitor.c b/qdev-monitor.c index 9833b33549..56cee1483f 100644 --- a/qdev-monitor.c +++ b/qdev-monitor.c @@ -38,6 +38,7 @@ #include "migration/misc.h" #include "migration/migration.h" #include "qemu/cutils.h" +#include "hw/clock.h" =20 /* * Aliases were a bad idea from the start. Let's keep them @@ -737,6 +738,7 @@ static void qdev_print(Monitor *mon, DeviceState *dev, = int indent) ObjectClass *class; BusState *child; NamedGPIOList *ngl; + NamedClockList *ncl; =20 qdev_printf("dev: %s, id \"%s\"\n", object_get_typename(OBJECT(dev)), dev->id ? dev->id : ""); @@ -751,6 +753,13 @@ static void qdev_print(Monitor *mon, DeviceState *dev,= int indent) ngl->num_out); } } + QLIST_FOREACH(ncl, &dev->clocks, node) { + qdev_printf("clock-%s%s \"%s\" freq_hz=3D%e\n", + ncl->output ? "out" : "in", + ncl->alias ? " (alias)" : "", + ncl->name, + CLOCK_PERIOD_TO_HZ(1.0 * clock_get(ncl->clock))); + } class =3D object_get_class(OBJECT(dev)); do { qdev_print_props(mon, dev, DEVICE_CLASS(class)->props_, indent); --=20 2.26.0