From nobody Fri Nov 14 06:41:31 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1585866224; cv=none; d=zohomail.com; s=zohoarc; b=kBN0VyyKGAfAgn/E9UnTh5WExTYxSue1RVxIXO0TloDmhOaeeN0t5X1vnkokpD0rLsP3mddL0jsO+BVirFMInuC3TB7N5YwZ4l2Lnr4mXb7YWtJb1NcxWcdQIqv6V8IaqOb8rai/VrNRQlY5iHjL7Smc+ATIw+BYPpaR2XmyYWE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1585866224; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rco8irUg11D2TArNYy9HRBuK5ph6X4DulIi8XnlO8KE=; b=EnqZvRoFqeD3JNCmMxOc33VQPZ/on9ZDt1lZ3W62wvl+M4Um1nBvYUCVT7Qf/np59H8es0KE8N/pvE/PqFrLJ4k7QhvWGDHXzsE0e5XBPJ1BfPQ87HhVJaxHhUpZOaIp1F2TLe6taOI3KQd2ecxIFhOvR/WFgcfSFpfnzB5OcxI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1585866224117354.6437153214006; Thu, 2 Apr 2020 15:23:44 -0700 (PDT) Received: from localhost ([::1]:47894 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jK8FS-00064R-QZ for importer@patchew.org; Thu, 02 Apr 2020 18:23:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:34494) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jK8D6-0001bx-Nj for qemu-devel@nongnu.org; Thu, 02 Apr 2020 18:21:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jK8D3-0007R0-5X for qemu-devel@nongnu.org; Thu, 02 Apr 2020 18:21:15 -0400 Received: from us-smtp-1.mimecast.com ([205.139.110.61]:29082 helo=us-smtp-delivery-1.mimecast.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jK8D2-0007Qf-NW for qemu-devel@nongnu.org; Thu, 02 Apr 2020 18:21:12 -0400 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-166-GRBwH2TuN02kXvxX5AF-2w-1; Thu, 02 Apr 2020 18:21:04 -0400 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 635A718A6EC0; Thu, 2 Apr 2020 22:21:03 +0000 (UTC) Received: from localhost (ovpn-116-71.gru2.redhat.com [10.97.116.71]) by smtp.corp.redhat.com (Postfix) with ESMTP id C0A1199E1A; Thu, 2 Apr 2020 22:20:59 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1585866072; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=rco8irUg11D2TArNYy9HRBuK5ph6X4DulIi8XnlO8KE=; b=jJXjiHzfFloirXxeYaWoc1hjIG3njZPoS7gecY17ljNAV+psRvs/bqc08Jhu9G90FjZsVm wxUUlu5KZ1zDtIphoWmZDc1dc8Bv1Qo7x63YWl38C/IC1Dba8p+Fn9Ew/2m1LshWOsjonf mJ2aL4cHCnH24bAq5RXacWMsIQZvbQE= X-MC-Unique: GRBwH2TuN02kXvxX5AF-2w-1 From: Eduardo Habkost To: Peter Maydell , qemu-devel@nongnu.org Subject: [PULL 1/9] hw/386: Add EPYC mode topology decoding functions Date: Thu, 2 Apr 2020 19:20:43 -0300 Message-Id: <20200402222051.523093-2-ehabkost@redhat.com> In-Reply-To: <20200402222051.523093-1-ehabkost@redhat.com> References: <20200402222051.523093-1-ehabkost@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 205.139.110.61 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Igor Mammedov , "Michael S . Tsirkin" , Babu Moger , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Babu Moger These functions add support for building EPYC mode topology given the smp details like numa nodes, cores, threads and sockets. The new apic id decoding is mostly similar to current apic id decoding except that it adds a new field node_id when numa configured. Removes all the hardcoded values. Subsequent patches will use these functions to build the topology. Following functions are added. apicid_llc_width_epyc apicid_llc_offset_epyc apicid_pkg_offset_epyc apicid_from_topo_ids_epyc x86_topo_ids_from_idx_epyc x86_topo_ids_from_apicid_epyc x86_apicid_from_cpu_idx_epyc The topology details are available in Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors. The revision guides a= re available from the bugzilla Link below. Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 Signed-off-by: Babu Moger Acked-by: Igor Mammedov Acked-by: Michael S. Tsirkin Message-Id: <158396721426.58170.2930696192478912976.stgit@naples-babu.amd.c= om> Signed-off-by: Eduardo Habkost --- include/hw/i386/topology.h | 100 +++++++++++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/include/hw/i386/topology.h b/include/hw/i386/topology.h index b9593b9905..07239f95f4 100644 --- a/include/hw/i386/topology.h +++ b/include/hw/i386/topology.h @@ -47,6 +47,7 @@ typedef uint32_t apic_id_t; =20 typedef struct X86CPUTopoIDs { unsigned pkg_id; + unsigned node_id; unsigned die_id; unsigned core_id; unsigned smt_id; @@ -88,6 +89,11 @@ static inline unsigned apicid_die_width(X86CPUTopoInfo *= topo_info) return apicid_bitwidth_for_count(topo_info->dies_per_pkg); } =20 +/* Bit width of the node_id field per socket */ +static inline unsigned apicid_node_width_epyc(X86CPUTopoInfo *topo_info) +{ + return apicid_bitwidth_for_count(MAX(topo_info->nodes_per_pkg, 1)); +} /* Bit offset of the Core_ID field */ static inline unsigned apicid_core_offset(X86CPUTopoInfo *topo_info) @@ -108,6 +114,100 @@ static inline unsigned apicid_pkg_offset(X86CPUTopoIn= fo *topo_info) return apicid_die_offset(topo_info) + apicid_die_width(topo_info); } =20 +#define NODE_ID_OFFSET 3 /* Minimum node_id offset if numa configured */ + +/* + * Bit offset of the node_id field + * + * Make sure nodes_per_pkg > 0 if numa configured else zero. + */ +static inline unsigned apicid_node_offset_epyc(X86CPUTopoInfo *topo_info) +{ + unsigned offset =3D apicid_die_offset(topo_info) + + apicid_die_width(topo_info); + + if (topo_info->nodes_per_pkg) { + return MAX(NODE_ID_OFFSET, offset); + } else { + return offset; + } +} + +/* Bit offset of the Pkg_ID (socket ID) field */ +static inline unsigned apicid_pkg_offset_epyc(X86CPUTopoInfo *topo_info) +{ + return apicid_node_offset_epyc(topo_info) + + apicid_node_width_epyc(topo_info); +} + +/* + * Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID + * + * The caller must make sure core_id < nr_cores and smt_id < nr_threads. + */ +static inline apic_id_t +x86_apicid_from_topo_ids_epyc(X86CPUTopoInfo *topo_info, + const X86CPUTopoIDs *topo_ids) +{ + return (topo_ids->pkg_id << apicid_pkg_offset_epyc(topo_info)) | + (topo_ids->node_id << apicid_node_offset_epyc(topo_info)) | + (topo_ids->die_id << apicid_die_offset(topo_info)) | + (topo_ids->core_id << apicid_core_offset(topo_info)) | + topo_ids->smt_id; +} + +static inline void x86_topo_ids_from_idx_epyc(X86CPUTopoInfo *topo_info, + unsigned cpu_index, + X86CPUTopoIDs *topo_ids) +{ + unsigned nr_nodes =3D MAX(topo_info->nodes_per_pkg, 1); + unsigned nr_dies =3D topo_info->dies_per_pkg; + unsigned nr_cores =3D topo_info->cores_per_die; + unsigned nr_threads =3D topo_info->threads_per_core; + unsigned cores_per_node =3D DIV_ROUND_UP((nr_dies * nr_cores * nr_thre= ads), + nr_nodes); + + topo_ids->pkg_id =3D cpu_index / (nr_dies * nr_cores * nr_threads); + topo_ids->node_id =3D (cpu_index / cores_per_node) % nr_nodes; + topo_ids->die_id =3D cpu_index / (nr_cores * nr_threads) % nr_dies; + topo_ids->core_id =3D cpu_index / nr_threads % nr_cores; + topo_ids->smt_id =3D cpu_index % nr_threads; +} + +/* + * Calculate thread/core/package IDs for a specific topology, + * based on APIC ID + */ +static inline void x86_topo_ids_from_apicid_epyc(apic_id_t apicid, + X86CPUTopoInfo *topo_info, + X86CPUTopoIDs *topo_ids) +{ + topo_ids->smt_id =3D apicid & + ~(0xFFFFFFFFUL << apicid_smt_width(topo_info)); + topo_ids->core_id =3D + (apicid >> apicid_core_offset(topo_info)) & + ~(0xFFFFFFFFUL << apicid_core_width(topo_info)); + topo_ids->die_id =3D + (apicid >> apicid_die_offset(topo_info)) & + ~(0xFFFFFFFFUL << apicid_die_width(topo_info)); + topo_ids->node_id =3D + (apicid >> apicid_node_offset_epyc(topo_info)) & + ~(0xFFFFFFFFUL << apicid_node_width_epyc(topo_info)); + topo_ids->pkg_id =3D apicid >> apicid_pkg_offset_epyc(topo_info); +} + +/* + * Make APIC ID for the CPU 'cpu_index' + * + * 'cpu_index' is a sequential, contiguous ID for the CPU. + */ +static inline apic_id_t x86_apicid_from_cpu_idx_epyc(X86CPUTopoInfo *topo_= info, + unsigned cpu_index) +{ + X86CPUTopoIDs topo_ids; + x86_topo_ids_from_idx_epyc(topo_info, cpu_index, &topo_ids); + return x86_apicid_from_topo_ids_epyc(topo_info, &topo_ids); +} /* Make APIC ID for the CPU based on Pkg_ID, Core_ID, SMT_ID * * The caller must make sure core_id < nr_cores and smt_id < nr_threads. --=20 2.24.1 From nobody Fri Nov 14 06:41:31 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Thu, 02 Apr 2020 18:21:11 -0400 Received: from mimecast-mx01.redhat.com (mimecast-mx01.redhat.com [209.132.183.4]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-286-3JeThMbSP_O9lJF1nub9ZA-1; Thu, 02 Apr 2020 18:21:08 -0400 Received: from smtp.corp.redhat.com (int-mx03.intmail.prod.int.phx2.redhat.com [10.5.11.13]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx01.redhat.com (Postfix) with ESMTPS id 7BDF113F8; Thu, 2 Apr 2020 22:21:07 +0000 (UTC) Received: from localhost (ovpn-116-71.gru2.redhat.com [10.97.116.71]) by smtp.corp.redhat.com (Postfix) with ESMTP id 7B5AD99E1A; Thu, 2 Apr 2020 22:21:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1585866070; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AoLVTpcT1tQukmDUYVw1Y6+g1h7iXgskFrd//vCLyJY=; b=Qt+d5TtKeZ+yIPBfJ/MYTUcEIYOqhR2IJHaalDnNChdzkgkhYbqK9C3ptLKmcd2WOLpykx cN0YaiHNQge0OIj//0Z18CR5ESDSkRh3uA0ZHrI6svZ+GXBDUmdcaGAuWJLMPGFW+RIm4X onj/1hpZ74aRRNzdmrjWQE5fxD5k5DA= X-MC-Unique: 3JeThMbSP_O9lJF1nub9ZA-1 From: Eduardo Habkost To: Peter Maydell , qemu-devel@nongnu.org Subject: [PULL 2/9] target/i386: Cleanup and use the EPYC mode topology functions Date: Thu, 2 Apr 2020 19:20:44 -0300 Message-Id: <20200402222051.523093-3-ehabkost@redhat.com> In-Reply-To: <20200402222051.523093-1-ehabkost@redhat.com> References: <20200402222051.523093-1-ehabkost@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 205.139.110.61 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Igor Mammedov , "Michael S . Tsirkin" , Babu Moger , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Babu Moger Use the new functions from topology.h and delete the unused code. Given the sockets, nodes, cores and threads, the new functions generate apic id for E= PYC mode. Removes all the hardcoded values. Signed-off-by: Babu Moger Acked-by: Michael S. Tsirkin Acked-by: Igor Mammedov Message-Id: <158396722151.58170.8031705769621392927.stgit@naples-babu.amd.c= om> Signed-off-by: Eduardo Habkost --- target/i386/cpu.c | 161 ++++++++++------------------------------------ 1 file changed, 34 insertions(+), 127 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 34b511f078..c3eba567ea 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -338,68 +338,15 @@ static void encode_cache_cpuid80000006(CPUCacheInfo *= l2, } } =20 -/* - * Definitions used for building CPUID Leaf 0x8000001D and 0x8000001E - * Please refer to the AMD64 Architecture Programmer=E2=80=99s Manual Volu= me 3. - * Define the constants to build the cpu topology. Right now, TOPOEXT - * feature is enabled only on EPYC. So, these constants are based on - * EPYC supported configurations. We may need to handle the cases if - * these values change in future. - */ -/* Maximum core complexes in a node */ -#define MAX_CCX 2 -/* Maximum cores in a core complex */ -#define MAX_CORES_IN_CCX 4 -/* Maximum cores in a node */ -#define MAX_CORES_IN_NODE 8 -/* Maximum nodes in a socket */ -#define MAX_NODES_PER_SOCKET 4 - -/* - * Figure out the number of nodes required to build this config. - * Max cores in a node is 8 - */ -static int nodes_in_socket(int nr_cores) -{ - int nodes; - - nodes =3D DIV_ROUND_UP(nr_cores, MAX_CORES_IN_NODE); - - /* Hardware does not support config with 3 nodes, return 4 in that case= */ - return (nodes =3D=3D 3) ? 4 : nodes; -} - -/* - * Decide the number of cores in a core complex with the given nr_cores us= ing - * following set constants MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_NODE and - * MAX_NODES_PER_SOCKET. Maintain symmetry as much as possible - * L3 cache is shared across all cores in a core complex. So, this will al= so - * tell us how many cores are sharing the L3 cache. - */ -static int cores_in_core_complex(int nr_cores) -{ - int nodes; - - /* Check if we can fit all the cores in one core complex */ - if (nr_cores <=3D MAX_CORES_IN_CCX) { - return nr_cores; - } - /* Get the number of nodes required to build this config */ - nodes =3D nodes_in_socket(nr_cores); - - /* - * Divide the cores accros all the core complexes - * Return rounded up value - */ - return DIV_ROUND_UP(nr_cores, nodes * MAX_CCX); -} - /* Encode cache info for CPUID[8000001D] */ -static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, CPUState *cs, - uint32_t *eax, uint32_t *ebx, - uint32_t *ecx, uint32_t *edx) +static void encode_cache_cpuid8000001d(CPUCacheInfo *cache, + X86CPUTopoInfo *topo_info, + uint32_t *eax, uint32_t *ebx, + uint32_t *ecx, uint32_t *edx) { uint32_t l3_cores; + unsigned nodes =3D MAX(topo_info->nodes_per_pkg, 1); + assert(cache->size =3D=3D cache->line_size * cache->associativity * cache->partitions * cache->sets); =20 @@ -408,10 +355,13 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *= cache, CPUState *cs, =20 /* L3 is shared among multiple cores */ if (cache->level =3D=3D 3) { - l3_cores =3D cores_in_core_complex(cs->nr_cores); - *eax |=3D ((l3_cores * cs->nr_threads) - 1) << 14; + l3_cores =3D DIV_ROUND_UP((topo_info->dies_per_pkg * + topo_info->cores_per_die * + topo_info->threads_per_core), + nodes); + *eax |=3D (l3_cores - 1) << 14; } else { - *eax |=3D ((cs->nr_threads - 1) << 14); + *eax |=3D ((topo_info->threads_per_core - 1) << 14); } =20 assert(cache->line_size > 0); @@ -431,55 +381,17 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo *= cache, CPUState *cs, (cache->complex_indexing ? CACHE_COMPLEX_IDX : 0); } =20 -/* Data structure to hold the configuration info for a given core index */ -struct core_topology { - /* core complex id of the current core index */ - int ccx_id; - /* - * Adjusted core index for this core in the topology - * This can be 0,1,2,3 with max 4 cores in a core complex - */ - int core_id; - /* Node id for this core index */ - int node_id; - /* Number of nodes in this config */ - int num_nodes; -}; - -/* - * Build the configuration closely match the EPYC hardware. Using the EPYC - * hardware configuration values (MAX_CCX, MAX_CORES_IN_CCX, MAX_CORES_IN_= NODE) - * right now. This could change in future. - * nr_cores : Total number of cores in the config - * core_id : Core index of the current CPU - * topo : Data structure to hold all the config info for this core ind= ex - */ -static void build_core_topology(int nr_cores, int core_id, - struct core_topology *topo) -{ - int nodes, cores_in_ccx; - - /* First get the number of nodes required */ - nodes =3D nodes_in_socket(nr_cores); - - cores_in_ccx =3D cores_in_core_complex(nr_cores); - - topo->node_id =3D core_id / (cores_in_ccx * MAX_CCX); - topo->ccx_id =3D (core_id % (cores_in_ccx * MAX_CCX)) / cores_in_ccx; - topo->core_id =3D core_id % cores_in_ccx; - topo->num_nodes =3D nodes; -} - /* Encode cache info for CPUID[8000001E] */ -static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu, +static void encode_topo_cpuid8000001e(X86CPUTopoInfo *topo_info, X86CPU *c= pu, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { - struct core_topology topo =3D {0}; - unsigned long nodes; + X86CPUTopoIDs topo_ids =3D {0}; + unsigned long nodes =3D MAX(topo_info->nodes_per_pkg, 1); int shift; =20 - build_core_topology(cs->nr_cores, cpu->core_id, &topo); + x86_topo_ids_from_apicid_epyc(cpu->apic_id, topo_info, &topo_ids); + *eax =3D cpu->apic_id; /* * CPUID_Fn8000001E_EBX @@ -496,12 +408,8 @@ static void encode_topo_cpuid8000001e(CPUState *cs, X8= 6CPU *cpu, * 3 Core complex id * 1:0 Core id */ - if (cs->nr_threads - 1) { - *ebx =3D ((cs->nr_threads - 1) << 8) | (topo.node_id << 3) | - (topo.ccx_id << 2) | topo.core_id; - } else { - *ebx =3D (topo.node_id << 4) | (topo.ccx_id << 3) | topo.core_id; - } + *ebx =3D ((topo_info->threads_per_core - 1) << 8) | (topo_ids.node_id = << 3) | + (topo_ids.core_id); /* * CPUID_Fn8000001E_ECX * 31:11 Reserved @@ -510,9 +418,8 @@ static void encode_topo_cpuid8000001e(CPUState *cs, X86= CPU *cpu, * 2 Socket id * 1:0 Node id */ - if (topo.num_nodes <=3D 4) { - *ecx =3D ((topo.num_nodes - 1) << 8) | (cpu->socket_id << 2) | - topo.node_id; + if (nodes <=3D 4) { + *ecx =3D ((nodes - 1) << 8) | (topo_ids.pkg_id << 2) | topo_ids.no= de_id; } else { /* * Node id fix up. Actual hardware supports up to 4 nodes. But with @@ -527,10 +434,10 @@ static void encode_topo_cpuid8000001e(CPUState *cs, X= 86CPU *cpu, * number of nodes. find_last_bit returns last set bit(0 based). L= eft * shift(+1) the socket id to represent all the nodes. */ - nodes =3D topo.num_nodes - 1; + nodes -=3D 1; shift =3D find_last_bit(&nodes, 8); - *ecx =3D ((topo.num_nodes - 1) << 8) | (cpu->socket_id << (shift += 1)) | - topo.node_id; + *ecx =3D (nodes << 8) | (topo_ids.pkg_id << (shift + 1)) | + topo_ids.node_id; } *edx =3D 0; } @@ -5499,6 +5406,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, uint32_t signature[3]; X86CPUTopoInfo topo_info; =20 + topo_info.nodes_per_pkg =3D env->nr_nodes; topo_info.dies_per_pkg =3D env->nr_dies; topo_info.cores_per_die =3D cs->nr_cores; topo_info.threads_per_core =3D cs->nr_threads; @@ -5918,20 +5826,20 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index= , uint32_t count, } switch (count) { case 0: /* L1 dcache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, cs, - eax, ebx, ecx, edx); + encode_cache_cpuid8000001d(env->cache_info_amd.l1d_cache, + &topo_info, eax, ebx, ecx, edx); break; case 1: /* L1 icache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, cs, - eax, ebx, ecx, edx); + encode_cache_cpuid8000001d(env->cache_info_amd.l1i_cache, + &topo_info, eax, ebx, ecx, edx); break; case 2: /* L2 cache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, cs, - eax, ebx, ecx, edx); + encode_cache_cpuid8000001d(env->cache_info_amd.l2_cache, + &topo_info, eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ - encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, cs, - eax, ebx, ecx, edx); + encode_cache_cpuid8000001d(env->cache_info_amd.l3_cache, + &topo_info, eax, ebx, ecx, edx); break; default: /* end of info */ *eax =3D *ebx =3D *ecx =3D *edx =3D 0; @@ -5940,8 +5848,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, break; case 0x8000001E: assert(cpu->core_id <=3D 255); - encode_topo_cpuid8000001e(cs, cpu, - eax, ebx, ecx, edx); + encode_topo_cpuid8000001e(&topo_info, cpu, eax, ebx, ecx, edx); break; case 0xC0000000: *eax =3D env->cpuid_xlevel2; --=20 2.24.1 From nobody Fri Nov 14 06:41:31 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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bh=inJcenK3LfmE6yBK2CNwYk0BFCmfLzRCvOvDSMeoni8=; b=WxUVucGEOxaWLxiBn6bbvLiujtEc/zgsdbf6uTuneYb4W2oOTMEXXvGL7CJ1T3gH4iWxIp X+Ywkvy7eeD6xlLgFxksHKyR9IzrSPULEQ6V/E8gcOF4lFxyPGJiECzZ2zQ45FeDhtUd9c rDadvQ5YpDS3itHVg6z6W2DCxS/VqxM= X-MC-Unique: pnqr3dHXNbi5XmMWofCbVQ-1 From: Eduardo Habkost To: Peter Maydell , qemu-devel@nongnu.org Subject: [PULL 3/9] hw/i386: Introduce apicid functions inside X86MachineState Date: Thu, 2 Apr 2020 19:20:45 -0300 Message-Id: <20200402222051.523093-4-ehabkost@redhat.com> In-Reply-To: <20200402222051.523093-1-ehabkost@redhat.com> References: <20200402222051.523093-1-ehabkost@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.13 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Igor Mammedov , "Michael S . Tsirkin" , Babu Moger , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Babu Moger Introduce model specific apicid functions inside X86MachineState. These functions will be loaded from X86CPUDefinition. Signed-off-by: Babu Moger Reviewed-by: Igor Mammedov Acked-by: Michael S. Tsirkin Message-Id: <158396722838.58170.5675998866484476427.stgit@naples-babu.amd.c= om> Signed-off-by: Eduardo Habkost --- hw/i386/x86.c | 5 +++++ include/hw/i386/x86.h | 9 +++++++++ 2 files changed, 14 insertions(+) diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 6ca3cf936f..2168fc56c0 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -937,6 +937,11 @@ static void x86_machine_initfn(Object *obj) x86ms->acpi =3D ON_OFF_AUTO_AUTO; x86ms->max_ram_below_4g =3D 0; /* use default */ x86ms->smp_dies =3D 1; + + x86ms->apicid_from_cpu_idx =3D x86_apicid_from_cpu_idx; + x86ms->topo_ids_from_apicid =3D x86_topo_ids_from_apicid; + x86ms->apicid_from_topo_ids =3D x86_apicid_from_topo_ids; + x86ms->apicid_pkg_offset =3D apicid_pkg_offset; } =20 static void x86_machine_class_init(ObjectClass *oc, void *data) diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h index 54af8ab5cf..b522854816 100644 --- a/include/hw/i386/x86.h +++ b/include/hw/i386/x86.h @@ -66,6 +66,15 @@ typedef struct { OnOffAuto smm; OnOffAuto acpi; =20 + /* Apic id specific handlers */ + uint32_t (*apicid_from_cpu_idx)(X86CPUTopoInfo *topo_info, + unsigned cpu_index); + void (*topo_ids_from_apicid)(apic_id_t apicid, X86CPUTopoInfo *topo_in= fo, + X86CPUTopoIDs *topo_ids); + apic_id_t (*apicid_from_topo_ids)(X86CPUTopoInfo *topo_info, + const X86CPUTopoIDs *topo_ids); + uint32_t (*apicid_pkg_offset)(X86CPUTopoInfo *topo_info); + /* * Address space used by IOAPIC device. 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Thu, 2 Apr 2020 22:21:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1585866078; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=F9xqnO3YKJSTA/95yMX9uswZdwcSnnmlp7FyfTrYddI=; b=K0PK4SRfL7YR/5SieJz/nCnoJyuj8KO62PjNoeEWRaoi5K3csAouAoPiK1zZ/IvLebToWR D7gQr8q4MdBR8/IgSK49TXm0x39g7diJ4IIzqVSi/uR+vbigUK7pyBV51dJXCgj5MDJoJ0 L9CivX/EmFGqzFSpBRKzPwQ6SWn7eok= X-MC-Unique: qxc93IduMgmtF9UE-UymaA-1 From: Eduardo Habkost To: Peter Maydell , qemu-devel@nongnu.org Subject: [PULL 4/9] i386: Introduce use_epyc_apic_id_encoding in X86CPUDefinition Date: Thu, 2 Apr 2020 19:20:46 -0300 Message-Id: <20200402222051.523093-5-ehabkost@redhat.com> In-Reply-To: <20200402222051.523093-1-ehabkost@redhat.com> References: <20200402222051.523093-1-ehabkost@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Babu Moger , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Babu Moger Add a boolean variable use_epyc_apic_id_encoding in X86CPUDefinition. This will be set if this cpu model needs to use new EPYC based apic id encoding. Override the handlers with EPYC based handlers if use_epyc_apic_id_encoding is set. This will be done in x86_cpus_init. Signed-off-by: Babu Moger Message-Id: <158396723514.58170.14825482171652019765.stgit@naples-babu.amd.= com> Signed-off-by: Eduardo Habkost --- target/i386/cpu.c | 16 ++++++++++++++++ target/i386/cpu.h | 1 + 2 files changed, 17 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index c3eba567ea..50cd257a7e 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1614,6 +1614,10 @@ typedef struct X86CPUDefinition { FeatureWordArray features; const char *model_id; CPUCaches *cache_info; + + /* Use AMD EPYC encoding for apic id */ + bool use_epyc_apic_id_encoding; + /* * Definitions for alternative versions of CPU model. * List is terminated by item with version =3D=3D 0. @@ -1655,6 +1659,18 @@ static const X86CPUVersionDefinition *x86_cpu_def_ge= t_versions(X86CPUDefinition return def->versions ?: default_version_list; } =20 +bool cpu_x86_use_epyc_apic_id_encoding(const char *cpu_type) +{ + X86CPUClass *xcc =3D X86_CPU_CLASS(object_class_by_name(cpu_type)); + + assert(xcc); + if (xcc->model && xcc->model->cpudef) { + return xcc->model->cpudef->use_epyc_apic_id_encoding; + } else { + return false; + } +} + static CPUCaches epyc_cache_info =3D { .l1d_cache =3D &(CPUCacheInfo) { .type =3D DATA_CACHE, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 9af1b0c12e..8227479c94 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1897,6 +1897,7 @@ void cpu_clear_apic_feature(CPUX86State *env); void host_cpuid(uint32_t function, uint32_t count, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx= ); void host_vendor_fms(char *vendor, int *family, int *model, int *stepping); +bool cpu_x86_use_epyc_apic_id_encoding(const char *cpu_type); =20 /* helper.c */ bool x86_cpu_tlb_fill(CPUState *cs, vaddr address, int size, --=20 2.24.1 From nobody Fri Nov 14 06:41:31 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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bh=fvQ8Cu/rtKC0QG0MUs7bXrtrsZ1YpwTZi8eMAbxudpU=; b=Y28zHdfrg2reP5kKEXONUqFc88guIFnFJItn6Ej51/qC9Lgs8/o3H5onibR6CTryJIXsd3 LVUmM3OFH4lHORA1EsCZHmvghqA4Sv/ixiFzNFf9RE4Y+CLhgKD9Gu/uKG1v+ReB+2JnST PDy+5Z2NCDWJqm3200ysXNG4joliKPQ= X-MC-Unique: KRMqeHzzPC6MLs4rseh-iA-1 From: Eduardo Habkost To: Peter Maydell , qemu-devel@nongnu.org Subject: [PULL 5/9] hw/i386: Move arch_id decode inside x86_cpus_init Date: Thu, 2 Apr 2020 19:20:47 -0300 Message-Id: <20200402222051.523093-6-ehabkost@redhat.com> In-Reply-To: <20200402222051.523093-1-ehabkost@redhat.com> References: <20200402222051.523093-1-ehabkost@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.5.11.22 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Babu Moger , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Babu Moger Apicid calculation depends on knowing the total number of numa nodes for EPYC cpu models. Right now, we are calculating the arch_id while parsing the numa(parse_numa). At this time, it is not known how many total numa nodes are configured in the system. Move the arch_id calculation inside x86_cpus_init. At this time, smp parse is already completed and numa node information is available. Override the handlers if use_epyc_apic_id_encoding is enabled in cpu model definition. Also replace the calling convention to use handlers from X86MachineState. Signed-off-by: Babu Moger Message-Id: <158396724217.58170.12256158354204870716.stgit@naples-babu.amd.= com> Signed-off-by: Eduardo Habkost --- hw/i386/pc.c | 6 +++--- hw/i386/x86.c | 37 ++++++++++++++++++++++++++++++------- 2 files changed, 33 insertions(+), 10 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 0bf0aaca52..b58925d063 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1580,14 +1580,14 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug= _dev, topo_ids.die_id =3D cpu->die_id; topo_ids.core_id =3D cpu->core_id; topo_ids.smt_id =3D cpu->thread_id; - cpu->apic_id =3D x86_apicid_from_topo_ids(&topo_info, &topo_ids); + cpu->apic_id =3D x86ms->apicid_from_topo_ids(&topo_info, &topo_ids= ); } =20 cpu_slot =3D pc_find_cpu_slot(MACHINE(pcms), cpu->apic_id, &idx); if (!cpu_slot) { MachineState *ms =3D MACHINE(pcms); =20 - x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); + x86ms->topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); error_setg(errp, "Invalid CPU [socket: %u, die: %u, core: %u, thread: %u] with" " APIC ID %" PRIu32 ", valid index range 0:%d", @@ -1608,7 +1608,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_d= ev, /* TODO: move socket_id/core_id/thread_id checks into x86_cpu_realizef= n() * once -smp refactoring is complete and there will be CPU private * CPUState::nr_cores and CPUState::nr_threads fields instead of globa= ls */ - x86_topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); + x86ms->topo_ids_from_apicid(cpu->apic_id, &topo_info, &topo_ids); if (cpu->socket_id !=3D -1 && cpu->socket_id !=3D topo_ids.pkg_id) { error_setg(errp, "property socket-id: %u doesn't match set apic-id= :" " 0x%x (socket-id: %u)", cpu->socket_id, cpu->apic_id, diff --git a/hw/i386/x86.c b/hw/i386/x86.c index 2168fc56c0..b82770024c 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -68,6 +68,22 @@ inline void init_topo_info(X86CPUTopoInfo *topo_info, topo_info->threads_per_core =3D ms->smp.threads; } =20 +/* + * Set up with the new EPYC topology handlers + * + * AMD uses different apic id encoding for EPYC based cpus. Override + * the default topo handlers with EPYC encoding handlers. + */ +static void x86_set_epyc_topo_handlers(MachineState *machine) +{ + X86MachineState *x86ms =3D X86_MACHINE(machine); + + x86ms->apicid_from_cpu_idx =3D x86_apicid_from_cpu_idx_epyc; + x86ms->topo_ids_from_apicid =3D x86_topo_ids_from_apicid_epyc; + x86ms->apicid_from_topo_ids =3D x86_apicid_from_topo_ids_epyc; + x86ms->apicid_pkg_offset =3D apicid_pkg_offset_epyc; +} + /* * Calculates initial APIC ID for a specific CPU index * @@ -86,7 +102,7 @@ uint32_t x86_cpu_apic_id_from_index(X86MachineState *x86= ms, =20 init_topo_info(&topo_info, x86ms); =20 - correct_id =3D x86_apicid_from_cpu_idx(&topo_info, cpu_index); + correct_id =3D x86ms->apicid_from_cpu_idx(&topo_info, cpu_index); if (x86mc->compat_apic_id_mode) { if (cpu_index !=3D correct_id && !warned && !qtest_enabled()) { error_report("APIC IDs set in compatibility mode, " @@ -121,6 +137,11 @@ void x86_cpus_init(X86MachineState *x86ms, int default= _cpu_version) MachineState *ms =3D MACHINE(x86ms); MachineClass *mc =3D MACHINE_GET_CLASS(x86ms); =20 + /* Check for apicid encoding */ + if (cpu_x86_use_epyc_apic_id_encoding(ms->cpu_type)) { + x86_set_epyc_topo_handlers(ms); + } + x86_cpu_set_default_version(default_cpu_version); =20 /* @@ -134,6 +155,12 @@ void x86_cpus_init(X86MachineState *x86ms, int default= _cpu_version) x86ms->apic_id_limit =3D x86_cpu_apic_id_from_index(x86ms, ms->smp.max_cpus - 1= ) + 1; possible_cpus =3D mc->possible_cpu_arch_ids(ms); + + for (i =3D 0; i < ms->possible_cpus->len; i++) { + ms->possible_cpus->cpus[i].arch_id =3D + x86_cpu_apic_id_from_index(x86ms, i); + } + for (i =3D 0; i < ms->smp.cpus; i++) { x86_cpu_new(x86ms, possible_cpus->cpus[i].arch_id, &error_fatal); } @@ -158,8 +185,7 @@ int64_t x86_get_default_cpu_node_id(const MachineState = *ms, int idx) init_topo_info(&topo_info, x86ms); =20 assert(idx < ms->possible_cpus->len); - x86_topo_ids_from_apicid(ms->possible_cpus->cpus[idx].arch_id, - &topo_info, &topo_ids); + x86_topo_ids_from_idx(&topo_info, idx, &topo_ids); return topo_ids.pkg_id % ms->numa_state->num_nodes; } =20 @@ -190,10 +216,7 @@ const CPUArchIdList *x86_possible_cpu_arch_ids(Machine= State *ms) =20 ms->possible_cpus->cpus[i].type =3D ms->cpu_type; ms->possible_cpus->cpus[i].vcpus_count =3D 1; - ms->possible_cpus->cpus[i].arch_id =3D - x86_cpu_apic_id_from_index(x86ms, i); - x86_topo_ids_from_apicid(ms->possible_cpus->cpus[i].arch_id, - &topo_info, &topo_ids); + x86_topo_ids_from_idx(&topo_info, i, &topo_ids); ms->possible_cpus->cpus[i].props.has_socket_id =3D true; ms->possible_cpus->cpus[i].props.socket_id =3D topo_ids.pkg_id; if (x86ms->smp_dies > 1) { --=20 2.24.1 From nobody Fri Nov 14 06:41:31 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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bh=8eikJeiSTpVtVuqjHyYzgg7DESld7tVIUuqk7/szlPk=; b=Mg7eOtBjrdWj4qWmSLpCVMDyYGu676YnFD7x4blE6QVvutuR7gfmt+wodG9jUkPR2CiFYT gGCYEKhrJvKwcIhHpRKpj58CcMYzN7cqy+IllCsFpnAvOTwJH2DU8om103zwymEwvPhfim o+MiXwALcueE3bc5wwkFvtEjGmOKeO8= X-MC-Unique: pwCV72d8NoCUw5_XGb4rHg-1 From: Eduardo Habkost To: Peter Maydell , qemu-devel@nongnu.org Subject: [PULL 6/9] target/i386: Enable new apic id encoding for EPYC based cpus models Date: Thu, 2 Apr 2020 19:20:48 -0300 Message-Id: <20200402222051.523093-7-ehabkost@redhat.com> In-Reply-To: <20200402222051.523093-1-ehabkost@redhat.com> References: <20200402222051.523093-1-ehabkost@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.15 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.81 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Igor Mammedov , "Michael S . Tsirkin" , Babu Moger , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Babu Moger The APIC ID is decoded based on the sequence sockets->dies->cores->threads. This works fine for most standard AMD and other vendors' configurations, but this decoding sequence does not follow that of AMD's APIC ID enumeration strictly. In some cases this can cause CPU topology inconsistency. When booting a guest VM, the kernel tries to validate the topology, and fin= ds it inconsistent with the enumeration of EPYC cpu models. The more details a= re in the bug https://bugzilla.redhat.com/show_bug.cgi?id=3D1728166. To fix the problem we need to build the topology as per the Processor Programming Reference (PPR) for AMD Family 17h Model 01h, Revision B1 Processors. The documentation is available from the bugzilla Link below. Link: https://bugzilla.kernel.org/show_bug.cgi?id=3D206537 It is also available at https://www.amd.com/system/files/TechDocs/55570-B1_PUB.zip Here is the text from the PPR. Operating systems are expected to use Core::X86::Cpuid::SizeId[ApicIdSize],= the number of least significant bits in the Initial APIC ID that indicate core = ID within a processor, in constructing per-core CPUID masks. Core::X86::Cpuid::SizeId[ApicIdSize] determines the maximum number of cores (MNC) that the processor could theoretically support, not the actual number= of cores that are actually implemented or enabled on the processor, as indicat= ed by Core::X86::Cpuid::SizeId[NC]. Each Core::X86::Apic::ApicId[ApicId] register is preset as follows: =E2=80=A2 ApicId[6] =3D Socket ID. =E2=80=A2 ApicId[5:4] =3D Node ID. =E2=80=A2 ApicId[3] =3D Logical CCX L3 complex ID =E2=80=A2 ApicId[2:0]=3D (SMT) ? {LogicalCoreID[1:0],ThreadId} : {1'b0,Logi= calCoreID[1:0]} The new apic id encoding is enabled for EPYC and EPYC-Rome models. Signed-off-by: Babu Moger Acked-by: Michael S. Tsirkin Acked-by: Igor Mammedov Message-Id: <158396724913.58170.3539083528095710811.stgit@naples-babu.amd.c= om> Signed-off-by: Eduardo Habkost --- target/i386/cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 50cd257a7e..468e03a153 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -3925,6 +3925,7 @@ static X86CPUDefinition builtin_x86_defs[] =3D { .xlevel =3D 0x8000001E, .model_id =3D "AMD EPYC Processor", .cache_info =3D &epyc_cache_info, + .use_epyc_apic_id_encoding =3D 1, .versions =3D (X86CPUVersionDefinition[]) { { .version =3D 1 }, { @@ -4052,6 +4053,7 @@ static X86CPUDefinition builtin_x86_defs[] =3D { .xlevel =3D 0x8000001E, .model_id =3D "AMD EPYC-Rome Processor", .cache_info =3D &epyc_rome_cache_info, + .use_epyc_apic_id_encoding =3D 1, }, }; =20 --=20 2.24.1 From nobody Fri Nov 14 06:41:31 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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bh=Bk5VqIK038e7G5IPRCsE90+B2JrEtJOic+qVj7wHDQU=; b=iUxYGkdtLtuH06csAcf6gUM/e703p4DVX+CwIQSgTTcUkDog2sxj3T7gH2+TTsnOzPBp2+ zmxoATjU4oNO7O1472FvVrAhz1Sj2BzBts+HJV+KBl7dv1G8gxb7ZLXN1KAHmnPLm/MnSF nheSA6t+nsPFn3UDvaRAEuT8qRz7v3A= X-MC-Unique: DERb047rPj-5PIbnUN7pPw-1 From: Eduardo Habkost To: Peter Maydell , qemu-devel@nongnu.org Subject: [PULL 7/9] i386: Fix pkg_id offset for EPYC cpu models Date: Thu, 2 Apr 2020 19:20:49 -0300 Message-Id: <20200402222051.523093-8-ehabkost@redhat.com> In-Reply-To: <20200402222051.523093-1-ehabkost@redhat.com> References: <20200402222051.523093-1-ehabkost@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Igor Mammedov , "Michael S . Tsirkin" , Babu Moger , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Babu Moger If the system is numa configured the pkg_offset needs to be adjusted for EPYC cpu models. Fix it calling the model specific handler. Signed-off-by: Babu Moger Reviewed-by: Igor Mammedov Acked-by: Michael S. Tsirkin Message-Id: <158396725589.58170.16424607815207074485.stgit@naples-babu.amd.= com> Signed-off-by: Eduardo Habkost --- hw/i386/pc.c | 1 + target/i386/cpu.c | 4 ++-- target/i386/cpu.h | 1 + 3 files changed, 4 insertions(+), 2 deletions(-) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index b58925d063..5143c51653 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1526,6 +1526,7 @@ static void pc_cpu_pre_plug(HotplugHandler *hotplug_d= ev, =20 env->nr_dies =3D x86ms->smp_dies; env->nr_nodes =3D topo_info.nodes_per_pkg; + env->pkg_offset =3D x86ms->apicid_pkg_offset(&topo_info); =20 /* * If APIC ID is not set, diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 468e03a153..6ad24774c5 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5610,7 +5610,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, *ecx |=3D CPUID_TOPOLOGY_LEVEL_SMT; break; case 1: - *eax =3D apicid_pkg_offset(&topo_info); + *eax =3D env->pkg_offset; *ebx =3D cs->nr_cores * cs->nr_threads; *ecx |=3D CPUID_TOPOLOGY_LEVEL_CORE; break; @@ -5644,7 +5644,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, *ecx |=3D CPUID_TOPOLOGY_LEVEL_CORE; break; case 2: - *eax =3D apicid_pkg_offset(&topo_info); + *eax =3D env->pkg_offset; *ebx =3D env->nr_dies * cs->nr_cores * cs->nr_threads; *ecx |=3D CPUID_TOPOLOGY_LEVEL_DIE; break; diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 8227479c94..e818fc712a 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1610,6 +1610,7 @@ typedef struct CPUX86State { =20 unsigned nr_dies; unsigned nr_nodes; + unsigned pkg_offset; } CPUX86State; =20 struct kvm_msrs; --=20 2.24.1 From nobody Fri Nov 14 06:41:31 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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bh=yQ3U51HON3TXLJT8Q2aD4tlT/7B2ruyUCI5f++GmHKA=; b=LkQ7E8iEuRD5izGncSYwANeNeT75kk3jsbJ+zxdeBi5M+18pwJIfKfoTSC3fUKIgh45ZMN m0If0ckc1t8kRq94iykqPc1UgkgIce76Bo8sBQPWact/WbsUKlIttZAmJmhh7mc5/5P6/K Hkn8fSF7W2k9RNR77LEs50m3ftzzu0M= X-MC-Unique: qK1Dk4QSM8KQHtm1aAO3iA-1 From: Eduardo Habkost To: Peter Maydell , qemu-devel@nongnu.org Subject: [PULL 8/9] target/i386: set the CPUID level to 0x14 on old machine-type Date: Thu, 2 Apr 2020 19:20:50 -0300 Message-Id: <20200402222051.523093-9-ehabkost@redhat.com> In-Reply-To: <20200402222051.523093-1-ehabkost@redhat.com> References: <20200402222051.523093-1-ehabkost@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Luwei Kang , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Luwei Kang The CPUID level need to be set to 0x14 manually on old machine-type if Intel PT is enabled in guest. E.g. the CPUID[0].EAX(level)=3D7 and CPUID[7].EBX[25](intel-pt)=3D1 when the Qemu with "-machine pc-i440fx-3.1 -cpu qemu64,+intel-pt" parameter. Some Intel PT capabilities are exposed by leaf 0x14 and the missing capabilities will cause some MSRs access failed. This patch add a warning message to inform the user to extend the CPUID level. Suggested-by: Eduardo Habkost Signed-off-by: Luwei Kang Message-Id: <1584031686-16444-1-git-send-email-luwei.kang@intel.com> Signed-off-by: Eduardo Habkost --- target/i386/cpu.c | 11 ++++++++--- 1 file changed, 8 insertions(+), 3 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 6ad24774c5..f3b25c7301 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6356,9 +6356,14 @@ static void x86_cpu_expand_features(X86CPU *cpu, Err= or **errp) x86_cpu_adjust_feat_level(cpu, FEAT_XSAVE); =20 /* Intel Processor Trace requires CPUID[0x14] */ - if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT) && - kvm_enabled() && cpu->intel_pt_auto_level) { - x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); + if ((env->features[FEAT_7_0_EBX] & CPUID_7_0_EBX_INTEL_PT)) { + if (cpu->intel_pt_auto_level) { + x86_cpu_adjust_level(cpu, &cpu->env.cpuid_min_level, 0x14); + } else if (cpu->env.cpuid_min_level < 0x14) { + mark_unavailable_features(cpu, FEAT_7_0_EBX, + CPUID_7_0_EBX_INTEL_PT, + "Intel PT need CPUID leaf 0x14, please set by \"-cpu .= ..,+intel-pt,level=3D0x14\""); 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Thu, 2 Apr 2020 22:21:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1585866106; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=yrbPIW5gqhRnCWEkG5j7mbFg1TQSaM8JXVuIcl0GLaI=; b=i6UL09wnXKjFTeQtEbDkms5/+2dtnIK2P0rzJmYxUWaV4IiZK5lUEliI5RFvkY+1ZWRD3R aqPfliT46tke6z1EIRmLKoXf7ran7trPvD9Q7y9fqelpywT4roxxp4pFJnjdYY7N8Si5vm r4w6xi/aAQjJHBpR5oizQ3MT040O8Ww= X-MC-Unique: oiR23EhBNQid18D10zwgmQ-1 From: Eduardo Habkost To: Peter Maydell , qemu-devel@nongnu.org Subject: [PULL 9/9] target/i386: Add ARCH_CAPABILITIES related bits into Icelake-Server CPU model Date: Thu, 2 Apr 2020 19:20:51 -0300 Message-Id: <20200402222051.523093-10-ehabkost@redhat.com> In-Reply-To: <20200402222051.523093-1-ehabkost@redhat.com> References: <20200402222051.523093-1-ehabkost@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.79 on 10.5.11.11 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 205.139.110.61 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini , Xiaoyao Li , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" From: Xiaoyao Li Current Icelake-Server CPU model lacks all the features enumerated by MSR_IA32_ARCH_CAPABILITIES. Add them, so that guest of "Icelake-Server" can see all of them. Signed-off-by: Xiaoyao Li Message-Id: <20200316095605.12318-1-xiaoyao.li@intel.com> Signed-off-by: Eduardo Habkost --- target/i386/cpu.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f3b25c7301..90ffc5f3b1 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -3471,6 +3471,19 @@ static X86CPUDefinition builtin_x86_defs[] =3D { { /* end of list */ } }, }, + { + .version =3D 3, + .props =3D (PropValue[]) { + { "arch-capabilities", "on" }, + { "rdctl-no", "on" }, + { "ibrs-all", "on" }, + { "skip-l1dfl-vmentry", "on" }, + { "mds-no", "on" }, + { "pschange-mc-no", "on" }, + { "taa-no", "on" }, + { /* end of list */ } + }, + }, { /* end of list */ } } }, --=20 2.24.1