From nobody Tue Feb 10 19:17:55 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1585590243; cv=none; d=zohomail.com; s=zohoarc; b=numWwwuxXrBmWzR+dl3CUHjbngu+L6QHMwHVAwRpN9ZgC8pan0Z7aonBm6dSJnDjGDvZ8se8+ZlufiFSDvCjO6IaXdVI+Y+P9FZKletAFy2Ki7iVmLTazORSiyBJ5ahHmEj1vtx+IUIX/TGvymcdQqA7nQMbFnD3tbXd4p3It3g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1585590243; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WvSPRxYwGnk9ZaSy5woOq12nRgL5YZWGIrPbTs7dm/M=; b=nxCAjnx0ICgGoYMFQku/Q305Ox2knXkKgJED/1xsN5Hma+hq59SOSu0Lh1dnDDf3/bi10nU2/BRMc9RrC3HSBmkK+OxhfbvrbsTeuRQ7BND6Hm3y9VhAQNh962zr+vlt3UUiBaGagITgVvhfc+AOhyME2/MVcMd/rX2ncx+oYYk= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1585590243162916.8365642115361; Mon, 30 Mar 2020 10:44:03 -0700 (PDT) Received: from localhost ([::1]:54148 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jIySA-0006Qv-0E for importer@patchew.org; Mon, 30 Mar 2020 13:44:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35695) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jIyO6-0001xn-RD for qemu-devel@nongnu.org; Mon, 30 Mar 2020 13:39:52 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jIyO5-0002s1-IC for qemu-devel@nongnu.org; Mon, 30 Mar 2020 13:39:50 -0400 Received: from smtp2200-217.mail.aliyun.com ([121.197.200.217]:40023) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jIyO5-0002m4-49; Mon, 30 Mar 2020 13:39:49 -0400 Received: from L-PF1D6DP4-1208.hz.ali.com(mailfrom:zhiwei_liu@c-sky.com fp:SMTPD_---.H7m6S6D_1585589982) by smtp.aliyun-inc.com(10.147.44.129); Tue, 31 Mar 2020 01:39:42 +0800 X-Alimail-AntiSpam: AC=CONTINUE; BC=0.07438733|-1; CH=blue; DM=|OVERLOAD|false|; DS=CONTINUE|ham_system_inform|0.0358285-0.000344232-0.963827; FP=0|0|0|0|0|-1|-1|-1; HT=e02c03267; MF=zhiwei_liu@c-sky.com; NM=1; PH=DS; RN=11; RT=11; SR=0; TI=SMTPD_---.H7m6S6D_1585589982; From: LIU Zhiwei To: richard.henderson@linaro.org, alistair23@gmail.com, chihmin.chao@sifive.com, palmer@dabbelt.com Subject: [PATCH v7 61/61] target/riscv: configure and turn on vector extension from command line Date: Mon, 30 Mar 2020 23:36:33 +0800 Message-Id: <20200330153633.15298-62-zhiwei_liu@c-sky.com> X-Mailer: git-send-email 2.23.0 In-Reply-To: <20200330153633.15298-1-zhiwei_liu@c-sky.com> References: <20200330153633.15298-1-zhiwei_liu@c-sky.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 3.x [generic] [fuzzy] X-Received-From: 121.197.200.217 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: guoren@linux.alibaba.com, qemu-riscv@nongnu.org, qemu-devel@nongnu.org, wxy194768@alibaba-inc.com, wenmeng_zhang@c-sky.com, Alistair Francis , LIU Zhiwei Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Vector extension is default off. The only way to use vector extension is 1. use cpu rv32 or rv64 2. turn on it by command line "-cpu rv64,x-v=3Dtrue,vlen=3D128,elen=3D64,vext_spec=3Dv0.7.1". vlen is the vector register length, default value is 128 bit. elen is the max operator size in bits, default value is 64 bit. vext_spec is the vector specification version, default value is v0.7.1. These properties can be specified with other values. Signed-off-by: LIU Zhiwei Reviewed-by: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 44 +++++++++++++++++++++++++++++++++++++++++++- target/riscv/cpu.h | 2 ++ 2 files changed, 45 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 077a32526e..37d545c030 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -396,7 +396,6 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) } =20 set_priv_version(env, priv_version); - set_vext_version(env, vext_version); set_resetvec(env, DEFAULT_RSTVEC); =20 if (cpu->cfg.mmu) { @@ -464,6 +463,45 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) if (cpu->cfg.ext_h) { target_misa |=3D RVH; } + if (cpu->cfg.ext_v) { + target_misa |=3D RVV; + if (!is_power_of_2(cpu->cfg.vlen)) { + error_setg(errp, + "Vector extension VLEN must be power of 2"); + return; + } + if (cpu->cfg.vlen > RV_VLEN_MAX || cpu->cfg.vlen < 128) { + error_setg(errp, + "Vector extension implementation only supports VLE= N " + "in the range [128, %d]", RV_VLEN_MAX); + return; + } + if (!is_power_of_2(cpu->cfg.elen)) { + error_setg(errp, + "Vector extension ELEN must be power of 2"); + return; + } + if (cpu->cfg.elen > 64 || cpu->cfg.vlen < 8) { + error_setg(errp, + "Vector extension implementation only supports ELE= N " + "in the range [8, 64]"); + return; + } + if (cpu->cfg.vext_spec) { + if (!g_strcmp0(cpu->cfg.vext_spec, "v0.7.1")) { + vext_version =3D VEXT_VERSION_0_07_1; + } else { + error_setg(errp, + "Unsupported vector spec version '%s'", + cpu->cfg.vext_spec); + return; + } + } else { + qemu_log("vector verison is not specified, " + "use the default value v0.7.1\n"); + } + set_vext_version(env, vext_version); + } =20 set_misa(env, RVXLEN | target_misa); } @@ -501,10 +539,14 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), /* This is experimental so mark with 'x-' */ DEFINE_PROP_BOOL("x-h", RISCVCPU, cfg.ext_h, false), + DEFINE_PROP_BOOL("x-v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("Counters", RISCVCPU, cfg.ext_counters, true), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), + DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), + DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128), + DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), DEFINE_PROP_END_OF_LIST(), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ddd62b3ea1..2bdd85d370 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -285,12 +285,14 @@ typedef struct RISCVCPU { bool ext_s; bool ext_u; bool ext_h; + bool ext_v; bool ext_counters; bool ext_ifencei; bool ext_icsr; =20 char *priv_spec; char *user_spec; + char *vext_spec; uint16_t vlen; uint16_t elen; bool mmu; --=20 2.23.0