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X-Received-From: 2607:f8b0:4864:20::642 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, Changbin Du Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) Content-Type: text/plain; charset="utf-8" The arm_current_el() should be invoked after mode switching. Otherwise, we get a wrong current EL value, since current EL is also determined by current mode. Fixes: 4a2696c0d4 ("target/arm: Set PAN bit as required on exception entry") Signed-off-by: Changbin Du Reviewed-by: Richard Henderson --- target/arm/helper.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index b7b6887241..163c91a1cc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -9172,7 +9172,6 @@ static void take_aarch32_exception(CPUARMState *env, = int new_mode, =20 /* Change the CPU state so as to actually take the exception. */ switch_mode(env, new_mode); - new_el =3D arm_current_el(env); =20 /* * For exceptions taken to AArch32 we must clear the SS bit in both @@ -9184,6 +9183,10 @@ static void take_aarch32_exception(CPUARMState *env,= int new_mode, env->condexec_bits =3D 0; /* Switch to the new mode, and to the correct instruction set. */ env->uncached_cpsr =3D (env->uncached_cpsr & ~CPSR_M) | new_mode; + + /* This must be after mode switching. */ + new_el =3D arm_current_el(env); + /* Set new mode endianness */ env->uncached_cpsr &=3D ~CPSR_E; if (env->cp15.sctlr_el[new_el] & SCTLR_EE) { --=20 2.25.1