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X-Received-From: 2607:f8b0:4864:20::f41 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robert.foley@linaro.org, richard.henderson@linaro.org, Aleksandar Markovic , "Emilio G. Cota" , peter.puhov@linaro.org, alex.bennee@linaro.org, Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" Soon we will call cpu_has_work without the BQL. Cc: Aurelien Jarno Cc: Aleksandar Markovic Reviewed-by: Richard Henderson Signed-off-by: Emilio G. Cota Signed-off-by: Robert Foley --- target/mips/cpu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 761d8aaa54..ec9dde5100 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -58,6 +58,8 @@ static bool mips_cpu_has_work(CPUState *cs) bool has_work =3D false; uint32_t interrupt_request =3D cpu_interrupt_request(cs); =20 + g_assert(qemu_mutex_iothread_locked()); + /* * Prior to MIPS Release 6 it is implementation dependent if non-enabl= ed * interrupts wake-up the CPU, however most of the implementations only @@ -193,7 +195,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *d= ata) device_class_set_parent_reset(dc, mips_cpu_reset, &mcc->parent_reset); =20 cc->class_by_name =3D mips_cpu_class_by_name; - cc->has_work =3D mips_cpu_has_work; + cc->has_work_with_iothread_lock =3D mips_cpu_has_work; cc->do_interrupt =3D mips_cpu_do_interrupt; cc->cpu_exec_interrupt =3D mips_cpu_exec_interrupt; cc->dump_state =3D mips_cpu_dump_state; --=20 2.17.1