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Thu, 26 Mar 2020 12:38:23 -0700 (PDT) From: Robert Foley To: qemu-devel@nongnu.org Subject: [PATCH v8 36/74] i386: use cpu_reset_interrupt Date: Thu, 26 Mar 2020 15:31:18 -0400 Message-Id: <20200326193156.4322-37-robert.foley@linaro.org> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200326193156.4322-1-robert.foley@linaro.org> References: <20200326193156.4322-1-robert.foley@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::f42 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robert.foley@linaro.org, richard.henderson@linaro.org, "Emilio G . Cota" , peter.puhov@linaro.org, Paolo Bonzini , alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Paolo Bonzini Reviewed-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Paolo Bonzini Signed-off-by: Emilio G. Cota Signed-off-by: Robert Foley --- target/i386/hax-all.c | 4 ++-- target/i386/hvf/x86hvf.c | 8 ++++---- target/i386/kvm.c | 14 +++++++------- target/i386/seg_helper.c | 13 ++++++------- target/i386/svm_helper.c | 2 +- target/i386/whpx-all.c | 10 +++++----- 6 files changed, 25 insertions(+), 26 deletions(-) diff --git a/target/i386/hax-all.c b/target/i386/hax-all.c index 25bf80b5f2..1edd6c77df 100644 --- a/target/i386/hax-all.c +++ b/target/i386/hax-all.c @@ -425,7 +425,7 @@ static int hax_vcpu_interrupt(CPUArchState *env) irq =3D cpu_get_pic_interrupt(env); if (irq >=3D 0) { hax_inject_interrupt(env, irq); - cpu->interrupt_request &=3D ~CPU_INTERRUPT_HARD; + cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD); } } =20 @@ -473,7 +473,7 @@ static int hax_vcpu_hax_exec(CPUArchState *env) } =20 if (cpu->interrupt_request & CPU_INTERRUPT_POLL) { - cpu->interrupt_request &=3D ~CPU_INTERRUPT_POLL; + cpu_reset_interrupt(cpu, CPU_INTERRUPT_POLL); apic_poll_irq(x86_cpu->apic_state); } =20 diff --git a/target/i386/hvf/x86hvf.c b/target/i386/hvf/x86hvf.c index cbb2144724..90f1662d0c 100644 --- a/target/i386/hvf/x86hvf.c +++ b/target/i386/hvf/x86hvf.c @@ -402,7 +402,7 @@ bool hvf_inject_interrupts(CPUState *cpu_state) =20 if (cpu_state->interrupt_request & CPU_INTERRUPT_NMI) { if (!(env->hflags2 & HF2_NMI_MASK) && !(info & VMCS_INTR_VALID)) { - cpu_state->interrupt_request &=3D ~CPU_INTERRUPT_NMI; + cpu_reset_interrupt(cpu_state, CPU_INTERRUPT_NMI); info =3D VMCS_INTR_VALID | VMCS_INTR_T_NMI | EXCP02_NMI; wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INTR_INFO, info); } else { @@ -414,7 +414,7 @@ bool hvf_inject_interrupts(CPUState *cpu_state) (cpu_state->interrupt_request & CPU_INTERRUPT_HARD) && (EFLAGS(env) & IF_MASK) && !(info & VMCS_INTR_VALID)) { int line =3D cpu_get_pic_interrupt(&x86cpu->env); - cpu_state->interrupt_request &=3D ~CPU_INTERRUPT_HARD; + cpu_reset_interrupt(cpu_state, CPU_INTERRUPT_HARD); if (line >=3D 0) { wvmcs(cpu_state->hvf_fd, VMCS_ENTRY_INTR_INFO, line | VMCS_INTR_VALID | VMCS_INTR_T_HWINTR); @@ -440,7 +440,7 @@ int hvf_process_events(CPUState *cpu_state) } =20 if (cpu_state->interrupt_request & CPU_INTERRUPT_POLL) { - cpu_state->interrupt_request &=3D ~CPU_INTERRUPT_POLL; + cpu_reset_interrupt(cpu_state, CPU_INTERRUPT_POLL); apic_poll_irq(cpu->apic_state); } if (((cpu_state->interrupt_request & CPU_INTERRUPT_HARD) && @@ -453,7 +453,7 @@ int hvf_process_events(CPUState *cpu_state) do_cpu_sipi(cpu); } if (cpu_state->interrupt_request & CPU_INTERRUPT_TPR) { - cpu_state->interrupt_request &=3D ~CPU_INTERRUPT_TPR; + cpu_reset_interrupt(cpu_state, CPU_INTERRUPT_TPR); hvf_cpu_synchronize_state(cpu_state); apic_handle_tpr_access_report(cpu->apic_state, env->eip, env->tpr_access_type); diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 9f1e28387f..44a4d45980 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -3657,7 +3657,7 @@ static int kvm_put_vcpu_events(X86CPU *cpu, int level) */ events.smi.pending =3D cs->interrupt_request & CPU_INTERRUPT_S= MI; events.smi.latched_init =3D cs->interrupt_request & CPU_INTERR= UPT_INIT; - cs->interrupt_request &=3D ~(CPU_INTERRUPT_INIT | CPU_INTERRUP= T_SMI); + cpu_reset_interrupt(cs, CPU_INTERRUPT_INIT | CPU_INTERRUPT_SMI= ); } else { /* Keep these in cs->interrupt_request. */ events.smi.pending =3D 0; @@ -4020,7 +4020,7 @@ void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *= run) if (cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) { if (cpu->interrupt_request & CPU_INTERRUPT_NMI) { qemu_mutex_lock_iothread(); - cpu->interrupt_request &=3D ~CPU_INTERRUPT_NMI; + cpu_reset_interrupt(cpu, CPU_INTERRUPT_NMI); qemu_mutex_unlock_iothread(); DPRINTF("injected NMI\n"); ret =3D kvm_vcpu_ioctl(cpu, KVM_NMI); @@ -4031,7 +4031,7 @@ void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *= run) } if (cpu->interrupt_request & CPU_INTERRUPT_SMI) { qemu_mutex_lock_iothread(); - cpu->interrupt_request &=3D ~CPU_INTERRUPT_SMI; + cpu_reset_interrupt(cpu, CPU_INTERRUPT_SMI); qemu_mutex_unlock_iothread(); DPRINTF("injected SMI\n"); ret =3D kvm_vcpu_ioctl(cpu, KVM_SMI); @@ -4067,7 +4067,7 @@ void kvm_arch_pre_run(CPUState *cpu, struct kvm_run *= run) (env->eflags & IF_MASK)) { int irq; =20 - cpu->interrupt_request &=3D ~CPU_INTERRUPT_HARD; + cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD); irq =3D cpu_get_pic_interrupt(env); if (irq >=3D 0) { struct kvm_interrupt intr; @@ -4138,7 +4138,7 @@ int kvm_arch_process_async_events(CPUState *cs) /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */ assert(env->mcg_cap); =20 - cs->interrupt_request &=3D ~CPU_INTERRUPT_MCE; + cpu_reset_interrupt(cs, CPU_INTERRUPT_MCE); =20 kvm_cpu_synchronize_state(cs); =20 @@ -4168,7 +4168,7 @@ int kvm_arch_process_async_events(CPUState *cs) } =20 if (cs->interrupt_request & CPU_INTERRUPT_POLL) { - cs->interrupt_request &=3D ~CPU_INTERRUPT_POLL; + cpu_reset_interrupt(cs, CPU_INTERRUPT_POLL); apic_poll_irq(cpu->apic_state); } if (((cs->interrupt_request & CPU_INTERRUPT_HARD) && @@ -4181,7 +4181,7 @@ int kvm_arch_process_async_events(CPUState *cs) do_cpu_sipi(cpu); } if (cs->interrupt_request & CPU_INTERRUPT_TPR) { - cs->interrupt_request &=3D ~CPU_INTERRUPT_TPR; + cpu_reset_interrupt(cs, CPU_INTERRUPT_TPR); kvm_cpu_synchronize_state(cs); apic_handle_tpr_access_report(cpu->apic_state, env->eip, env->tpr_access_type); diff --git a/target/i386/seg_helper.c b/target/i386/seg_helper.c index b96de068ca..818f65f35f 100644 --- a/target/i386/seg_helper.c +++ b/target/i386/seg_helper.c @@ -1332,7 +1332,7 @@ bool x86_cpu_exec_interrupt(CPUState *cs, int interru= pt_request) switch (interrupt_request) { #if !defined(CONFIG_USER_ONLY) case CPU_INTERRUPT_POLL: - cs->interrupt_request &=3D ~CPU_INTERRUPT_POLL; + cpu_reset_interrupt(cs, CPU_INTERRUPT_POLL); apic_poll_irq(cpu->apic_state); break; #endif @@ -1341,23 +1341,22 @@ bool x86_cpu_exec_interrupt(CPUState *cs, int inter= rupt_request) break; case CPU_INTERRUPT_SMI: cpu_svm_check_intercept_param(env, SVM_EXIT_SMI, 0, 0); - cs->interrupt_request &=3D ~CPU_INTERRUPT_SMI; + cpu_reset_interrupt(cs, CPU_INTERRUPT_SMI); do_smm_enter(cpu); break; case CPU_INTERRUPT_NMI: cpu_svm_check_intercept_param(env, SVM_EXIT_NMI, 0, 0); - cs->interrupt_request &=3D ~CPU_INTERRUPT_NMI; + cpu_reset_interrupt(cs, CPU_INTERRUPT_NMI); env->hflags2 |=3D HF2_NMI_MASK; do_interrupt_x86_hardirq(env, EXCP02_NMI, 1); break; case CPU_INTERRUPT_MCE: - cs->interrupt_request &=3D ~CPU_INTERRUPT_MCE; + cpu_reset_interrupt(cs, CPU_INTERRUPT_MCE); do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0); break; case CPU_INTERRUPT_HARD: cpu_svm_check_intercept_param(env, SVM_EXIT_INTR, 0, 0); - cs->interrupt_request &=3D ~(CPU_INTERRUPT_HARD | - CPU_INTERRUPT_VIRQ); + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD | CPU_INTERRUPT_VIRQ); intno =3D cpu_get_pic_interrupt(env); qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=3D0x%02x\n", intno); @@ -1372,7 +1371,7 @@ bool x86_cpu_exec_interrupt(CPUState *cs, int interru= pt_request) qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=3D0x%02x\n", intno); do_interrupt_x86_hardirq(env, intno, 1); - cs->interrupt_request &=3D ~CPU_INTERRUPT_VIRQ; + cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); break; #endif } diff --git a/target/i386/svm_helper.c b/target/i386/svm_helper.c index 7b8105a1c3..63eb136743 100644 --- a/target/i386/svm_helper.c +++ b/target/i386/svm_helper.c @@ -700,7 +700,7 @@ void do_vmexit(CPUX86State *env, uint32_t exit_code, ui= nt64_t exit_info_1) env->hflags &=3D ~HF_GUEST_MASK; env->intercept =3D 0; env->intercept_exceptions =3D 0; - cs->interrupt_request &=3D ~CPU_INTERRUPT_VIRQ; + cpu_reset_interrupt(cs, CPU_INTERRUPT_VIRQ); env->tsc_offset =3D 0; =20 env->gdt.base =3D x86_ldq_phys(cs, env->vm_hsave + offsetof(struct vm= cb, diff --git a/target/i386/whpx-all.c b/target/i386/whpx-all.c index efc2d88810..d5beb4a5e2 100644 --- a/target/i386/whpx-all.c +++ b/target/i386/whpx-all.c @@ -790,14 +790,14 @@ static void whpx_vcpu_pre_run(CPUState *cpu) if (!vcpu->interruption_pending && cpu->interrupt_request & (CPU_INTERRUPT_NMI | CPU_INTERRUPT_SMI)) { if (cpu->interrupt_request & CPU_INTERRUPT_NMI) { - cpu->interrupt_request &=3D ~CPU_INTERRUPT_NMI; + cpu_reset_interrupt(cpu, CPU_INTERRUPT_NMI); vcpu->interruptable =3D false; new_int.InterruptionType =3D WHvX64PendingNmi; new_int.InterruptionPending =3D 1; new_int.InterruptionVector =3D 2; } if (cpu->interrupt_request & CPU_INTERRUPT_SMI) { - cpu->interrupt_request &=3D ~CPU_INTERRUPT_SMI; + cpu_reset_interrupt(cpu, CPU_INTERRUPT_SMI); } } =20 @@ -820,7 +820,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) vcpu->interruptable && (env->eflags & IF_MASK)) { assert(!new_int.InterruptionPending); if (cpu->interrupt_request & CPU_INTERRUPT_HARD) { - cpu->interrupt_request &=3D ~CPU_INTERRUPT_HARD; + cpu_reset_interrupt(cpu, CPU_INTERRUPT_HARD); irq =3D cpu_get_pic_interrupt(env); if (irq >=3D 0) { new_int.InterruptionType =3D WHvX64PendingInterrupt; @@ -911,7 +911,7 @@ static void whpx_vcpu_process_async_events(CPUState *cp= u) } =20 if (cpu->interrupt_request & CPU_INTERRUPT_POLL) { - cpu->interrupt_request &=3D ~CPU_INTERRUPT_POLL; + cpu_reset_interrupt(cpu, CPU_INTERRUPT_POLL); apic_poll_irq(x86_cpu->apic_state); } =20 @@ -927,7 +927,7 @@ static void whpx_vcpu_process_async_events(CPUState *cp= u) } =20 if (cpu->interrupt_request & CPU_INTERRUPT_TPR) { - cpu->interrupt_request &=3D ~CPU_INTERRUPT_TPR; + cpu_reset_interrupt(cpu, CPU_INTERRUPT_TPR); whpx_cpu_synchronize_state(cpu); apic_handle_tpr_access_report(x86_cpu->apic_state, env->eip, env->tpr_access_type); --=20 2.17.1