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X-Received-From: 2607:f8b0:4864:20::f43 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: robert.foley@linaro.org, richard.henderson@linaro.org, "Emilio G. Cota" , qemu-ppc@nongnu.org, peter.puhov@linaro.org, alex.bennee@linaro.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" From: "Emilio G. Cota" In ppce500_spin.c, acquire the lock just once to update both cpu->halted and cpu->stopped. In hw/ppc/spapr_hcall.c, acquire the lock just once to update cpu->halted and call cpu_has_work, since later in the series we'll acquire the BQL (if not already held) from cpu_has_work. Cc: David Gibson Cc: qemu-ppc@nongnu.org Reviewed-by: Richard Henderson Acked-by: David Gibson Signed-off-by: Emilio G. Cota [RF: hw/ppc/spapr_hcall.c, spapr_rtas.c more conversions] Signed-off-by: Robert Foley --- hw/ppc/e500.c | 4 ++-- hw/ppc/ppc.c | 10 +++++----- hw/ppc/ppce500_spin.c | 6 ++++-- hw/ppc/spapr_cpu_core.c | 4 ++-- hw/ppc/spapr_hcall.c | 14 ++++++++------ hw/ppc/spapr_rtas.c | 8 ++++---- target/ppc/excp_helper.c | 4 ++-- target/ppc/helper_regs.h | 2 +- target/ppc/kvm.c | 4 ++-- target/ppc/translate_init.inc.c | 8 ++++---- 10 files changed, 34 insertions(+), 30 deletions(-) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 854cd3ac46..77cc1d245b 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -706,7 +706,7 @@ static void ppce500_cpu_reset_sec(void *opaque) =20 /* Secondary CPU starts in halted state for now. Needs to change when implementing non-kernel boot. */ - cs->halted =3D 1; + cpu_halted_set(cs, 1); cs->exception_index =3D EXCP_HLT; } =20 @@ -720,7 +720,7 @@ static void ppce500_cpu_reset(void *opaque) cpu_reset(cs); =20 /* Set initial guest state. */ - cs->halted =3D 0; + cpu_halted_set(cs, 0); env->gpr[1] =3D (16 * MiB) - 8; env->gpr[3] =3D bi->dt_base; env->gpr[4] =3D 0; diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index 4a11fb1640..0e7386ff88 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -149,7 +149,7 @@ static void ppc6xx_set_irq(void *opaque, int pin, int l= evel) /* XXX: Note that the only way to restart the CPU is to reset = it */ if (level) { LOG_IRQ("%s: stop the CPU\n", __func__); - cs->halted =3D 1; + cpu_halted_set(cs, 1); } break; case PPC6xx_INPUT_HRESET: @@ -228,10 +228,10 @@ static void ppc970_set_irq(void *opaque, int pin, int= level) /* XXX: TODO: relay the signal to CKSTP_OUT pin */ if (level) { LOG_IRQ("%s: stop the CPU\n", __func__); - cs->halted =3D 1; + cpu_halted_set(cs, 1); } else { LOG_IRQ("%s: restart the CPU\n", __func__); - cs->halted =3D 0; + cpu_halted_set(cs, 0); qemu_cpu_kick(cs); } break; @@ -445,10 +445,10 @@ static void ppc40x_set_irq(void *opaque, int pin, int= level) /* Level sensitive - active low */ if (level) { LOG_IRQ("%s: stop the CPU\n", __func__); - cs->halted =3D 1; + cpu_halted_set(cs, 1); } else { LOG_IRQ("%s: restart the CPU\n", __func__); - cs->halted =3D 0; + cpu_halted_set(cs, 0); qemu_cpu_kick(cs); } break; diff --git a/hw/ppc/ppce500_spin.c b/hw/ppc/ppce500_spin.c index 66c1065db2..79313944cf 100644 --- a/hw/ppc/ppce500_spin.c +++ b/hw/ppc/ppce500_spin.c @@ -107,9 +107,11 @@ static void spin_kick(CPUState *cs, run_on_cpu_data da= ta) map_start =3D ldq_p(&curspin->addr) & ~(map_size - 1); mmubooke_create_initial_mapping(env, 0, map_start, map_size); =20 - cs->halted =3D 0; - cs->exception_index =3D -1; + cpu_mutex_lock(cs); + cpu_halted_set(cs, 0); cs->stopped =3D false; + cpu_mutex_unlock(cs); + cs->exception_index =3D -1; qemu_cpu_kick(cs); } =20 diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index ac1c109427..d655ce588f 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -39,7 +39,7 @@ static void spapr_reset_vcpu(PowerPCCPU *cpu) /* All CPUs start halted. CPU0 is unhalted from the machine level * reset code and the rest are explicitly started up by the guest * using an RTAS call */ - cs->halted =3D 1; + cpu_halted_set(cs, 1); =20 env->spr[SPR_HIOR] =3D 0; =20 @@ -88,7 +88,7 @@ void spapr_cpu_set_entry_state(PowerPCCPU *cpu, target_ul= ong nip, env->gpr[3] =3D r3; env->gpr[4] =3D r4; kvmppc_set_reg_ppc_online(cpu, 1); - CPU(cpu)->halted =3D 0; + cpu_halted_set(CPU(cpu), 0); /* Enable Power-saving mode Exit Cause exceptions */ ppc_store_lpcr(cpu, env->spr[SPR_LPCR] | pcc->lpcr_pm); } diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 0d50fc9117..a9485000e4 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -1058,17 +1058,19 @@ static target_ulong h_cede(PowerPCCPU *cpu, SpaprMa= chineState *spapr, env->msr |=3D (1ULL << MSR_EE); hreg_compute_hflags(env); =20 + cpu_mutex_lock(cs); if (spapr_cpu->prod) { spapr_cpu->prod =3D false; + cpu_mutex_unlock(cs); return H_SUCCESS; } =20 if (!cpu_has_work(cs)) { - cs->halted =3D 1; + cpu_halted_set(cs, 1); cs->exception_index =3D EXCP_HLT; cs->exit_request =3D 1; } - + cpu_mutex_unlock(cs); return H_SUCCESS; } =20 @@ -1085,7 +1087,7 @@ static target_ulong h_confer_self(PowerPCCPU *cpu) spapr_cpu->prod =3D false; return H_SUCCESS; } - cs->halted =3D 1; + cpu_halted_set(cs, 1); cs->exception_index =3D EXCP_HALTED; cs->exit_request =3D 1; =20 @@ -1116,7 +1118,7 @@ static target_ulong h_join(PowerPCCPU *cpu, SpaprMach= ineState *spapr, } =20 /* Don't have a way to indicate joined, so use halted && MSR[EE]= =3D0 */ - if (!cs->halted || (e->msr & (1ULL << MSR_EE))) { + if (!cpu_halted(cs) || (e->msr & (1ULL << MSR_EE))) { last_unjoined =3D false; break; } @@ -1199,7 +1201,7 @@ static target_ulong h_prod(PowerPCCPU *cpu, SpaprMach= ineState *spapr, =20 spapr_cpu =3D spapr_cpu_state(tcpu); spapr_cpu->prod =3D true; - cs->halted =3D 0; + cpu_halted_set(cs, 0); qemu_cpu_kick(cs); =20 return H_SUCCESS; @@ -1688,7 +1690,7 @@ static target_ulong h_client_architecture_support(Pow= erPCCPU *cpu, if (cs =3D=3D CPU(cpu)) { continue; } - if (!cs->halted) { + if (!cpu_halted(cs)) { warn_report("guest has multiple active vCPUs at CAS, which is = not allowed"); return H_MULTI_THREADS_ACTIVE; } diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index 9fb8c8632a..84c26edb60 100644 --- a/hw/ppc/spapr_rtas.c +++ b/hw/ppc/spapr_rtas.c @@ -111,7 +111,7 @@ static void rtas_query_cpu_stopped_state(PowerPCCPU *cp= u_, id =3D rtas_ld(args, 0); cpu =3D spapr_find_cpu(id); if (cpu !=3D NULL) { - if (CPU(cpu)->halted) { + if (cpu_halted(CPU(cpu))) { rtas_st(rets, 1, 0); } else { rtas_st(rets, 1, 2); @@ -155,7 +155,7 @@ static void rtas_start_cpu(PowerPCCPU *callcpu, SpaprMa= chineState *spapr, env =3D &newcpu->env; pcc =3D POWERPC_CPU_GET_CLASS(newcpu); =20 - if (!CPU(newcpu)->halted) { + if (!cpu_halted(CPU(newcpu))) { rtas_st(rets, 0, RTAS_OUT_HW_ERROR); return; } @@ -213,7 +213,7 @@ static void rtas_stop_self(PowerPCCPU *cpu, SpaprMachin= eState *spapr, */ ppc_store_lpcr(cpu, env->spr[SPR_LPCR] & ~pcc->lpcr_pm); env->spr[SPR_PSSCR] |=3D PSSCR_EC; - cs->halted =3D 1; + cpu_halted_set(cs, 1); kvmppc_set_reg_ppc_online(cpu, 0); qemu_cpu_kick(cs); } @@ -238,7 +238,7 @@ static void rtas_ibm_suspend_me(PowerPCCPU *cpu, SpaprM= achineState *spapr, } =20 /* See h_join */ - if (!cs->halted || (e->msr & (1ULL << MSR_EE))) { + if (!cpu_halted(cs) || (e->msr & (1ULL << MSR_EE))) { rtas_st(rets, 0, H_MULTI_THREADS_ACTIVE); return; } diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 08bc885ca6..e686eda0f4 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -276,7 +276,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int ex= cp_model, int excp) qemu_log("Machine check while not allowed. " "Entering checkstop state\n"); } - cs->halted =3D 1; + cpu_halted_set(cs, 1); cpu_interrupt_exittb(cs); } if (env->msr_mask & MSR_HVB) { @@ -1075,7 +1075,7 @@ void helper_pminsn(CPUPPCState *env, powerpc_pm_insn_= t insn) CPUState *cs; =20 cs =3D env_cpu(env); - cs->halted =3D 1; + cpu_halted_set(cs, 1); =20 /* * The architecture specifies that HDEC interrupts are discarded diff --git a/target/ppc/helper_regs.h b/target/ppc/helper_regs.h index d78c2af63e..f84438f639 100644 --- a/target/ppc/helper_regs.h +++ b/target/ppc/helper_regs.h @@ -168,7 +168,7 @@ static inline int hreg_store_msr(CPUPPCState *env, targ= et_ulong value, #if !defined(CONFIG_USER_ONLY) if (unlikely(msr_pow =3D=3D 1)) { if (!env->pending_interrupts && (*env->check_pow)(env)) { - cs->halted =3D 1; + cpu_halted_set(cs, 1); excp =3D EXCP_HALTED; } } diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 597f72be1b..13c6626ca7 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -1340,7 +1340,7 @@ MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm= _run *run) =20 int kvm_arch_process_async_events(CPUState *cs) { - return cs->halted; + return cpu_halted(cs); } =20 static int kvmppc_handle_halt(PowerPCCPU *cpu) @@ -1349,7 +1349,7 @@ static int kvmppc_handle_halt(PowerPCCPU *cpu) CPUPPCState *env =3D &cpu->env; =20 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) { - cs->halted =3D 1; + cpu_halted_set(cs, 1); cs->exception_index =3D EXCP_HLT; } =20 diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.in= c.c index e853164a86..5c2f8ffa4a 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -8539,7 +8539,7 @@ static bool cpu_has_work_POWER7(CPUState *cs) PowerPCCPU *cpu =3D POWERPC_CPU(cs); CPUPPCState *env =3D &cpu->env; =20 - if (cs->halted) { + if (cpu_halted(cs)) { if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { return false; } @@ -8701,7 +8701,7 @@ static bool cpu_has_work_POWER8(CPUState *cs) PowerPCCPU *cpu =3D POWERPC_CPU(cs); CPUPPCState *env =3D &cpu->env; =20 - if (cs->halted) { + if (cpu_halted(cs)) { if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { return false; } @@ -8901,7 +8901,7 @@ static bool cpu_has_work_POWER9(CPUState *cs) PowerPCCPU *cpu =3D POWERPC_CPU(cs); CPUPPCState *env =3D &cpu->env; =20 - if (cs->halted) { + if (cpu_halted(cs)) { uint64_t psscr =3D env->spr[SPR_PSSCR]; =20 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { @@ -9117,7 +9117,7 @@ static bool cpu_has_work_POWER10(CPUState *cs) PowerPCCPU *cpu =3D POWERPC_CPU(cs); CPUPPCState *env =3D &cpu->env; =20 - if (cs->halted) { + if (cpu_halted(cs)) { uint64_t psscr =3D env->spr[SPR_PSSCR]; =20 if (!(cs->interrupt_request & CPU_INTERRUPT_HARD)) { --=20 2.17.1