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[83.52.54.37]) by smtp.gmail.com with ESMTPSA id r17sm6345672wrx.46.2020.03.25.12.18.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Mar 2020 12:18:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GhVX8f98O0Xa/LOVRL95qx+viSjodj+CYTsM4Px49fY=; b=JK8Z5CR/vAs+6GNWR0Pc0Cq4xV4rhs44H+vI9mGz+3lT8gmhVFY1NllA7uofymoktC OOclKhzERBoU/GzD1dJES4G/UJgvl1RUJJ9kNghnhttGDn0bdwkHRf/Ey1VR0XFH3TzU wOWSW/pQABNh/pmWRlzEMb/uVMCGtnwmGdAEzsnIp+3iSJfmy8TBGnXws3x4QwZfrEPI a4XhOPv35/drV2M+Y8km8jAe9wb2fFCZoc0H/rR5waIKkt3oSsR5WnH7dkuTOkjjUnQw XRRO1F66lML2S3dfYwFA9yy8OFGtXGj0SjPtglj8dq2oQ2rylSGUuLclC8ky934kREEg 5tyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=GhVX8f98O0Xa/LOVRL95qx+viSjodj+CYTsM4Px49fY=; b=m6pgHU5lSG/HBgJLrYFb/d11O5UMaTciJVMnHa4LDinmiACMS04/Gtd4K6fYUsRLdb XeZBo4UsRaDoS6Kxb+X2DGddccmxTmfEeU7Q0fWxk0QS33vQn6aRva93w2RhWBWqyiiG x0ZmV270bix6vYU/YHWgzpFk50pPLyeiE2PEBuSwExhL9K4G+hATq820HzUr1Ilt13T9 DrfFZH/TynDpmjt5o983S4T6haZB2X9ABrxJRRvYUpUr+psOkWEItCLDHW8r/dm/Z53n 5tpB5k4vMrhBXpkQHargJouwEnMsEZWP2GaAklGNlPqRPOYgKJe3YKrIWKBUBgdXDmco ylBw== X-Gm-Message-State: ANhLgQ13tiHB97llkQ4bGrzsEaqw2zaptKW8NkAQ3nN155vHoDzKEmKX MgfKVJpwEKXCwjZKOv3Hrdx4j4juh30= X-Google-Smtp-Source: ADFU+vvTWcMqq/E0mn8RtOqbGbhhftd/mq/2WBj+7QJppdLptSgZJXwgm/gtKBHwIBbeIRUW73G1pQ== X-Received: by 2002:a1c:dc8b:: with SMTP id t133mr4615449wmg.99.1585163926248; Wed, 25 Mar 2020 12:18:46 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH-for-5.0 04/12] hw/arm/stm32fx05_soc: Add missing error-propagation code Date: Wed, 25 Mar 2020 20:18:22 +0100 Message-Id: <20200325191830.16553-5-f4bug@amsat.org> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200325191830.16553-1-f4bug@amsat.org> References: <20200325191830.16553-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::32d X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paul Burton , Sagar Karandikar , "Michael S. Tsirkin" , Jason Wang , Mark Cave-Ayland , Alistair Francis , "Edgar E. Iglesias" , Peter Maydell , Markus Armbruster , Aleksandar Markovic , Palmer Dabbelt , Aleksandar Rikalo , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Eduardo Habkost , Alistair Francis , qemu-arm@nongnu.org, David Gibson , qemu-riscv@nongnu.org, Bastian Koppelmann , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Andrew Baumann , Jean-Christophe Dubois , qemu-ppc@nongnu.org, Paolo Bonzini , Aurelien Jarno Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Patch created mechanically by running: $ spatch \ --macro-file scripts/cocci-macro-file.h --include-headers \ --sp-file scripts/coccinelle/object_property_missing_error_propagate.co= cci \ --keep-comments --smpl-spacing --in-place --dir hw Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Reviewed-by: Peter Maydell --- hw/arm/stm32f205_soc.c | 4 ++++ hw/arm/stm32f405_soc.c | 4 ++++ 2 files changed, 8 insertions(+) diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c index 118c342559..1d80f91dd7 100644 --- a/hw/arm/stm32f205_soc.c +++ b/hw/arm/stm32f205_soc.c @@ -83,113 +83,117 @@ static void stm32f205_soc_initfn(Object *obj) static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) { STM32F205State *s =3D STM32F205_SOC(dev_soc); DeviceState *dev, *armv7m; SysBusDevice *busdev; Error *err =3D NULL; int i; =20 MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *sram =3D g_new(MemoryRegion, 1); MemoryRegion *flash =3D g_new(MemoryRegion, 1); MemoryRegion *flash_alias =3D g_new(MemoryRegion, 1); =20 memory_region_init_rom(flash, OBJECT(dev_soc), "STM32F205.flash", FLASH_SIZE, &error_fatal); memory_region_init_alias(flash_alias, OBJECT(dev_soc), "STM32F205.flash.alias", flash, 0, FLASH_SIZE= ); =20 memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, flash); memory_region_add_subregion(system_memory, 0, flash_alias); =20 memory_region_init_ram(sram, NULL, "STM32F205.sram", SRAM_SIZE, &error_fatal); memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); =20 armv7m =3D DEVICE(&s->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 96); qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); qdev_prop_set_bit(armv7m, "enable-bitband", true); object_property_set_link(OBJECT(&s->armv7m), OBJECT(get_system_memory(= )), "memory", &error_abort); object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err); if (err !=3D NULL) { error_propagate(errp, err); return; } =20 /* System configuration controller */ dev =3D DEVICE(&s->syscfg); object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err); if (err !=3D NULL) { error_propagate(errp, err); return; } busdev =3D SYS_BUS_DEVICE(dev); sysbus_mmio_map(busdev, 0, 0x40013800); sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, 71)); =20 /* Attach UART (uses USART registers) and USART controllers */ for (i =3D 0; i < STM_NUM_USARTS; i++) { dev =3D DEVICE(&(s->usart[i])); qdev_prop_set_chr(dev, "chardev", serial_hd(i)); object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &= err); if (err !=3D NULL) { error_propagate(errp, err); return; } busdev =3D SYS_BUS_DEVICE(dev); sysbus_mmio_map(busdev, 0, usart_addr[i]); sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i= ])); } =20 /* Timer 2 to 5 */ for (i =3D 0; i < STM_NUM_TIMERS; i++) { dev =3D DEVICE(&(s->timer[i])); qdev_prop_set_uint64(dev, "clock-frequency", 1000000000); object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &= err); if (err !=3D NULL) { error_propagate(errp, err); return; } busdev =3D SYS_BUS_DEVICE(dev); sysbus_mmio_map(busdev, 0, timer_addr[i]); sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i= ])); } =20 /* ADC 1 to 3 */ object_property_set_int(OBJECT(s->adc_irqs), STM_NUM_ADCS, "num-lines", &err); + if (err) { + error_propagate(errp, err); + return; + } object_property_set_bool(OBJECT(s->adc_irqs), true, "realized", &err); if (err !=3D NULL) { error_propagate(errp, err); return; } qdev_connect_gpio_out(DEVICE(s->adc_irqs), 0, qdev_get_gpio_in(armv7m, ADC_IRQ)); =20 for (i =3D 0; i < STM_NUM_ADCS; i++) { dev =3D DEVICE(&(s->adc[i])); object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &er= r); if (err !=3D NULL) { error_propagate(errp, err); return; } busdev =3D SYS_BUS_DEVICE(dev); sysbus_mmio_map(busdev, 0, adc_addr[i]); sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(s->adc_irqs), i)); } =20 /* SPI 1 and 2 */ for (i =3D 0; i < STM_NUM_SPIS; i++) { dev =3D DEVICE(&(s->spi[i])); object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &er= r); if (err !=3D NULL) { error_propagate(errp, err); return; } busdev =3D SYS_BUS_DEVICE(dev); sysbus_mmio_map(busdev, 0, spi_addr[i]); sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i])= ); } } diff --git a/hw/arm/stm32f405_soc.c b/hw/arm/stm32f405_soc.c index 4f10ce6176..398a3b5b4f 100644 --- a/hw/arm/stm32f405_soc.c +++ b/hw/arm/stm32f405_soc.c @@ -89,183 +89,187 @@ static void stm32f405_soc_initfn(Object *obj) static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp) { STM32F405State *s =3D STM32F405_SOC(dev_soc); MemoryRegion *system_memory =3D get_system_memory(); DeviceState *dev, *armv7m; SysBusDevice *busdev; Error *err =3D NULL; int i; =20 memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F405.flash", FLASH_SIZE, &err); if (err !=3D NULL) { error_propagate(errp, err); return; } memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc), "STM32F405.flash.alias", &s->flash, 0, FLASH_SIZE); =20 memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->fla= sh); memory_region_add_subregion(system_memory, 0, &s->flash_alias); =20 memory_region_init_ram(&s->sram, NULL, "STM32F405.sram", SRAM_SIZE, &err); if (err !=3D NULL) { error_propagate(errp, err); return; } memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram= ); =20 armv7m =3D DEVICE(&s->armv7m); qdev_prop_set_uint32(armv7m, "num-irq", 96); qdev_prop_set_string(armv7m, "cpu-type", s->cpu_type); qdev_prop_set_bit(armv7m, "enable-bitband", true); object_property_set_link(OBJECT(&s->armv7m), OBJECT(system_memory), "memory", &error_abort); object_property_set_bool(OBJECT(&s->armv7m), true, "realized", &err); if (err !=3D NULL) { error_propagate(errp, err); return; } =20 /* System configuration controller */ dev =3D DEVICE(&s->syscfg); object_property_set_bool(OBJECT(&s->syscfg), true, "realized", &err); if (err !=3D NULL) { error_propagate(errp, err); return; } busdev =3D SYS_BUS_DEVICE(dev); sysbus_mmio_map(busdev, 0, SYSCFG_ADD); sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, SYSCFG_IRQ)); =20 /* Attach UART (uses USART registers) and USART controllers */ for (i =3D 0; i < STM_NUM_USARTS; i++) { dev =3D DEVICE(&(s->usart[i])); qdev_prop_set_chr(dev, "chardev", serial_hd(i)); object_property_set_bool(OBJECT(&s->usart[i]), true, "realized", &= err); if (err !=3D NULL) { error_propagate(errp, err); return; } busdev =3D SYS_BUS_DEVICE(dev); sysbus_mmio_map(busdev, 0, usart_addr[i]); sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i= ])); } =20 /* Timer 2 to 5 */ for (i =3D 0; i < STM_NUM_TIMERS; i++) { dev =3D DEVICE(&(s->timer[i])); qdev_prop_set_uint64(dev, "clock-frequency", 1000000000); object_property_set_bool(OBJECT(&s->timer[i]), true, "realized", &= err); if (err !=3D NULL) { error_propagate(errp, err); return; } busdev =3D SYS_BUS_DEVICE(dev); sysbus_mmio_map(busdev, 0, timer_addr[i]); sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i= ])); } =20 /* ADC device, the IRQs are ORed together */ object_initialize_child(OBJECT(s), "adc-orirq", &s->adc_irqs, sizeof(s->adc_irqs), TYPE_OR_IRQ, &err, NULL); if (err !=3D NULL) { error_propagate(errp, err); return; } object_property_set_int(OBJECT(&s->adc_irqs), STM_NUM_ADCS, "num-lines", &err); + if (err) { + error_propagate(errp, err); + return; + } object_property_set_bool(OBJECT(&s->adc_irqs), true, "realized", &err); if (err !=3D NULL) { error_propagate(errp, err); return; } qdev_connect_gpio_out(DEVICE(&s->adc_irqs), 0, qdev_get_gpio_in(armv7m, ADC_IRQ)); =20 dev =3D DEVICE(&(s->adc[i])); object_property_set_bool(OBJECT(&s->adc[i]), true, "realized", &err); if (err !=3D NULL) { error_propagate(errp, err); return; } busdev =3D SYS_BUS_DEVICE(dev); sysbus_mmio_map(busdev, 0, ADC_ADDR); sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->adc_irqs), i)); =20 /* SPI devices */ for (i =3D 0; i < STM_NUM_SPIS; i++) { dev =3D DEVICE(&(s->spi[i])); object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &er= r); if (err !=3D NULL) { error_propagate(errp, err); return; } busdev =3D SYS_BUS_DEVICE(dev); sysbus_mmio_map(busdev, 0, spi_addr[i]); sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i])= ); } =20 /* EXTI device */ dev =3D DEVICE(&s->exti); object_property_set_bool(OBJECT(&s->exti), true, "realized", &err); if (err !=3D NULL) { error_propagate(errp, err); return; } busdev =3D SYS_BUS_DEVICE(dev); sysbus_mmio_map(busdev, 0, EXTI_ADDR); for (i =3D 0; i < 16; i++) { sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i]= )); } for (i =3D 0; i < 16; i++) { qdev_connect_gpio_out(DEVICE(&s->syscfg), i, qdev_get_gpio_in(dev,= i)); } =20 create_unimplemented_device("timer[7]", 0x40001400, 0x400); create_unimplemented_device("timer[12]", 0x40001800, 0x400); create_unimplemented_device("timer[6]", 0x40001000, 0x400); create_unimplemented_device("timer[13]", 0x40001C00, 0x400); create_unimplemented_device("timer[14]", 0x40002000, 0x400); create_unimplemented_device("RTC and BKP", 0x40002800, 0x400); create_unimplemented_device("WWDG", 0x40002C00, 0x400); create_unimplemented_device("IWDG", 0x40003000, 0x400); create_unimplemented_device("I2S2ext", 0x40003000, 0x400); create_unimplemented_device("I2S3ext", 0x40004000, 0x400); create_unimplemented_device("I2C1", 0x40005400, 0x400); create_unimplemented_device("I2C2", 0x40005800, 0x400); create_unimplemented_device("I2C3", 0x40005C00, 0x400); create_unimplemented_device("CAN1", 0x40006400, 0x400); create_unimplemented_device("CAN2", 0x40006800, 0x400); create_unimplemented_device("PWR", 0x40007000, 0x400); create_unimplemented_device("DAC", 0x40007400, 0x400); create_unimplemented_device("timer[1]", 0x40010000, 0x400); create_unimplemented_device("timer[8]", 0x40010400, 0x400); create_unimplemented_device("SDIO", 0x40012C00, 0x400); create_unimplemented_device("timer[9]", 0x40014000, 0x400); create_unimplemented_device("timer[10]", 0x40014400, 0x400); create_unimplemented_device("timer[11]", 0x40014800, 0x400); create_unimplemented_device("GPIOA", 0x40020000, 0x400); create_unimplemented_device("GPIOB", 0x40020400, 0x400); create_unimplemented_device("GPIOC", 0x40020800, 0x400); create_unimplemented_device("GPIOD", 0x40020C00, 0x400); create_unimplemented_device("GPIOE", 0x40021000, 0x400); create_unimplemented_device("GPIOF", 0x40021400, 0x400); create_unimplemented_device("GPIOG", 0x40021800, 0x400); create_unimplemented_device("GPIOH", 0x40021C00, 0x400); create_unimplemented_device("GPIOI", 0x40022000, 0x400); create_unimplemented_device("CRC", 0x40023000, 0x400); create_unimplemented_device("RCC", 0x40023800, 0x400); create_unimplemented_device("Flash Int", 0x40023C00, 0x400); create_unimplemented_device("BKPSRAM", 0x40024000, 0x400); create_unimplemented_device("DMA1", 0x40026000, 0x400); create_unimplemented_device("DMA2", 0x40026400, 0x400); create_unimplemented_device("Ethernet", 0x40028000, 0x1400); create_unimplemented_device("USB OTG HS", 0x40040000, 0x30000); create_unimplemented_device("USB OTG FS", 0x50000000, 0x31000); create_unimplemented_device("DCMI", 0x50050000, 0x400); create_unimplemented_device("RNG", 0x50060800, 0x400); } --=20 2.21.1