From nobody Mon Feb 9 11:32:25 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com ARC-Seal: i=1; a=rsa-sha256; t=1584933417; cv=none; d=zohomail.com; s=zohoarc; b=jd8BudSYivWC7c1ptueGnBlCTsRxZuttuRyK4VnZwMgVa0dE3tHuKBc0QbwOcwPpsJX2lEeZeR0sbbQUDEaJaty466oj9iAOsgHctpuBczwqw7H3h9g12II/G/89U/0hrA6oPjynf1ISgslA22zORraSzEka0N5ApiaAvvZxKdY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1584933417; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pJ3GoyjcqKxWasKniGVSL64CcbWlMzx+/XcH3ZpZzmE=; b=KDvjESXDbjCNaHmkeIYby4QzQRmrpZhpgyMAUFTPp5gNTdYFm9m8JXnUbaMuGweX0zW5QK8Nl+WvKd4RIAeB6yTxmVT5p8nkdx/SZxDRNBnSg4NTwJec25KYaOnFeYPBbvpZnU3qUu1dfDM473rtXwCSclnH5JvvGMK1e//IVVs= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 158493341797492.17814121012054; Sun, 22 Mar 2020 20:16:57 -0700 (PDT) Received: from localhost ([::1]:56736 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jGDaC-0000aq-QR for importer@patchew.org; Sun, 22 Mar 2020 23:16:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51059) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jGDY5-0005ih-IK for qemu-devel@nongnu.org; Sun, 22 Mar 2020 23:14:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jGDY4-0003gC-90 for qemu-devel@nongnu.org; Sun, 22 Mar 2020 23:14:45 -0400 Received: from mga07.intel.com ([134.134.136.100]:56660) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jGDY3-0003fq-UT for qemu-devel@nongnu.org; Sun, 22 Mar 2020 23:14:44 -0400 Received: from fmsmga003.fm.intel.com ([10.253.24.29]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 22 Mar 2020 20:14:42 -0700 Received: from lxy-clx-4s.sh.intel.com ([10.239.43.161]) by FMSMGA003.fm.intel.com with ESMTP; 22 Mar 2020 20:14:40 -0700 IronPort-SDR: 8xGx7k2Ccaj7baqWqXbHRmzmnf3/2x1kgF6QWfU4WHxLaJiStsYBLXHaTbzWr3r14tXJOmgcL6 yMFF8T9L0fKg== X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False IronPort-SDR: Gg+QmSZ8XLK3JGiAcInv8v2C/jGZtEXMFOu8gL1rc12E5hYuMeikfstiUIPjnpYrAk6dz6rqwo ULjSfFlndTVg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.72,294,1580803200"; d="scan'208";a="292453684" From: Xiaoyao Li To: Paolo Bonzini , Marcelo Tosatti , Richard Henderson , Eduardo Habkost Subject: [PATCH 2/3] target/i386: Add support for TEST_CTRL MSR Date: Mon, 23 Mar 2020 10:56:57 +0800 Message-Id: <20200323025658.4540-3-xiaoyao.li@intel.com> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200323025658.4540-1-xiaoyao.li@intel.com> References: <20200323025658.4540-1-xiaoyao.li@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: FreeBSD 9.x [fuzzy] X-Received-From: 134.134.136.100 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Xiaoyao Li , qemu-devel@nongnu.org, kvm@vger.kernel.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" From: Xiaoyao Li MSR_TEST_CTRL is needed and accessed by feature split lock detection. Signed-off-by: Xiaoyao Li --- target/i386/cpu.h | 2 ++ target/i386/kvm.c | 13 +++++++++++++ target/i386/machine.c | 20 ++++++++++++++++++++ 3 files changed, 35 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index f6c54412ba5e..177732ad19da 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -343,6 +343,7 @@ typedef enum X86Seg { #define MSR_IA32_APICBASE_ENABLE (1<<11) #define MSR_IA32_APICBASE_EXTD (1 << 10) #define MSR_IA32_APICBASE_BASE (0xfffffU<<12) +#define MSR_TEST_CTRL 0x33 #define MSR_IA32_FEATURE_CONTROL 0x0000003a #define MSR_TSC_ADJUST 0x0000003b #define MSR_IA32_SPEC_CTRL 0x48 @@ -1466,6 +1467,7 @@ typedef struct CPUX86State { =20 uint64_t spec_ctrl; uint64_t virt_ssbd; + uint64_t msr_test_ctrl; =20 /* End of state preserved by INIT (dummy marker). */ struct {} end_init_save; diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 6888cb7caeae..411402aa29fa 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -101,6 +101,7 @@ static bool has_msr_umwait; static bool has_msr_spec_ctrl; static bool has_msr_tsx_ctrl; static bool has_msr_virt_ssbd; +static bool has_msr_test_ctrl; static bool has_msr_smi_count; static bool has_msr_arch_capabs; static bool has_msr_core_capabs; @@ -2048,6 +2049,9 @@ static int kvm_get_supported_msrs(KVMState *s) case MSR_VIRT_SSBD: has_msr_virt_ssbd =3D true; break; + case MSR_TEST_CTRL: + has_msr_test_ctrl =3D true; + break; case MSR_IA32_ARCH_CAPABILITIES: has_msr_arch_capabs =3D true; break; @@ -2766,6 +2770,9 @@ static int kvm_put_msrs(X86CPU *cpu, int level) if (has_msr_virt_ssbd) { kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, env->virt_ssbd); } + if (has_msr_test_ctrl) { + kvm_msr_entry_add(cpu, MSR_TEST_CTRL, env->msr_test_ctrl); + } =20 #ifdef TARGET_X86_64 if (lm_capable_kernel) { @@ -3154,6 +3161,9 @@ static int kvm_get_msrs(X86CPU *cpu) if (has_msr_virt_ssbd) { kvm_msr_entry_add(cpu, MSR_VIRT_SSBD, 0); } + if (has_msr_test_ctrl) { + kvm_msr_entry_add(cpu, MSR_TEST_CTRL, 0); + } if (!env->tsc_valid) { kvm_msr_entry_add(cpu, MSR_IA32_TSC, 0); env->tsc_valid =3D !runstate_is_running(); @@ -3549,6 +3559,9 @@ static int kvm_get_msrs(X86CPU *cpu) case MSR_VIRT_SSBD: env->virt_ssbd =3D msrs[i].data; break; + case MSR_TEST_CTRL: + env->msr_test_ctrl =3D msrs[i].data; + break; case MSR_IA32_RTIT_CTL: env->msr_rtit_ctrl =3D msrs[i].data; break; diff --git a/target/i386/machine.c b/target/i386/machine.c index 0c96531a56f0..a23c6687d5ba 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -1252,6 +1252,25 @@ static const VMStateDescription vmstate_msr_virt_ssb= d =3D { } }; =20 +static bool msr_test_ctrl_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return env->msr_test_ctrl !=3D 0; +} + +static const VMStateDescription vmstate_msr_test_ctrl =3D { + .name =3D "cpu/msr_test_ctrl", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D msr_test_ctrl_needed, + .fields =3D (VMStateField[]){ + VMSTATE_UINT64(env.msr_test_ctrl, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + static bool svm_npt_needed(void *opaque) { X86CPU *cpu =3D opaque; @@ -1439,6 +1458,7 @@ VMStateDescription vmstate_x86_cpu =3D { &vmstate_mcg_ext_ctl, &vmstate_msr_intel_pt, &vmstate_msr_virt_ssbd, + &vmstate_msr_test_ctrl, &vmstate_svm_npt, #ifndef TARGET_X86_64 &vmstate_efer32, --=20 2.20.1