From nobody Mon Feb 9 02:13:16 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1584916329; cv=none; d=zohomail.com; s=zohoarc; b=J2IYHndTuZi88G+c01AOQex59LdDOBCw0ATXn7hLOVG3HE2p9fsv7PVvd4kFO1IWaAdC56cXSEVpw9LbdQlOFJRSzIYhVg0NGDycVXa/ZGDWIP9l8QXwwnZgnEFIx/N0Ho9NayW4j68RbyQ63Zw2OcxxaH4N7dcMORT6GQ0I3eo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1584916329; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=icQASRE5zbUwjEx3SfSkFive8J2TBJbkiETKhnGSSjM=; b=leZXO7SuMvr0Aay15IWQUzNtgXSHi2WsXFJxWmuYKfyo47aNPIAHujr7L5gXVrzHQcAjgqutws/rFxqkOiDLIXPkOz0cFq4DznHa4H+Ttk8qJV3Q3dMFvzZgywlC+08zoBXonRZabiRrVmgVQ5VPNoU+XQtzq5wamf5+ymxJffQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 158491632962414.640578943218884; Sun, 22 Mar 2020 15:32:09 -0700 (PDT) Received: from localhost ([::1]:50528 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jG98a-0001Me-6K for importer@patchew.org; Sun, 22 Mar 2020 18:32:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50177) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jG95U-0005im-JQ for qemu-devel@nongnu.org; Sun, 22 Mar 2020 18:29:01 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jG95P-0001mP-M2 for qemu-devel@nongnu.org; Sun, 22 Mar 2020 18:28:56 -0400 Received: from mail-pf1-x443.google.com ([2607:f8b0:4864:20::443]:45931) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1jG95P-0001mB-95 for qemu-devel@nongnu.org; Sun, 22 Mar 2020 18:28:51 -0400 Received: by mail-pf1-x443.google.com with SMTP id j10so6496545pfi.12 for ; Sun, 22 Mar 2020 15:28:51 -0700 (PDT) Received: from localhost.localdomain ([75.167.220.149]) by smtp.gmail.com with ESMTPSA id e10sm11440315pfm.121.2020.03.22.15.28.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Mar 2020 15:28:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=icQASRE5zbUwjEx3SfSkFive8J2TBJbkiETKhnGSSjM=; b=OB5qPJW0VDBR61ceZXe2YcH2d5rd859YQBocj5L79S70N9quvxN1ijrtbAvKxQQzj0 8S8XCpyNhfrQ3NbSgpBUCATmgJcb7BaSvnqO81aJMPU6XesJwK3P6YfT5AnG37CDID+j Wr2fDzaDFav5xHkUmxy4XbT3D9k5Z1kZUS/9Eh+DR2PR9Unt9vwPvHom5rtcltvX/hRt j0cUxMRzYwj16pVqFRSMFSDkibGg2Bu9P3grZUdkDYvcqIyljY9PjHJgP45kdUfQzj5B WmfNuG6HHev0jjDM+k6FXYH1nr/47tlzFSQGAoxShxabY4ILoFq7pEX4dbwtB+W6yp0Y 1yaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=icQASRE5zbUwjEx3SfSkFive8J2TBJbkiETKhnGSSjM=; b=uNjvqssXeuyuzuGi+zz2AI6dqnbez9Inbw7Xb/kPqwPSjbAej8By9jog1rQ7EFnu+1 5T6WAcJKC3aGYHGs1eFE3tJFjYUuihAoQ8MdMBahOT+kJmpKFQp3BnL+yDPmkVAFLIZP 8oBOOgtzQd1UiT/evaNOWpIMX6Df+n+ZTl5b2NVkUK+2MTZW3iQloHx1TnlnyK9swM9z 4zcC8mm8eYLCM6kstV53u87R4rQgiJBcf34Fk1oYuE6u+/SUVRXJ3ecoK8xj3moN747V k/y2/rznhTlbT/Z14suJibup89RSnf0lQWViwK1LfS38/Lxw6Gm27oPH5BY4YXqG8jVC tDgA== X-Gm-Message-State: ANhLgQ0W67kdnFskQJF3K3cPlKQerfIfH2iCptVUVBRDwdI6/Ryf6jCj 3Jvbunyh1wZJJVKAk4/1vbvjV5qPnvkIhw== X-Google-Smtp-Source: ADFU+vt9Oecd+Wgs9guKvoY6ra1QC2q0XIl7pWjdy1dfn71ckBCj9dXLz4fS3XYR+xGZCDxM6YMqKg== X-Received: by 2002:aa7:868e:: with SMTP id d14mr19917110pfo.250.1584916129692; Sun, 22 Mar 2020 15:28:49 -0700 (PDT) From: Paul Zimmerman To: kraxel@redhat.com Subject: [PATCH 4/6] dwc-hsotg USB host controller emulation Date: Sun, 22 Mar 2020 15:27:24 -0700 Message-Id: <20200322222726.10244-5-pauldzim@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200322222726.10244-1-pauldzim@gmail.com> References: <20200322222726.10244-1-pauldzim@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, stefanha@gmail.com, qemu-devel@nongnu.org, Paul Zimmerman , jsnow@redhat.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add the dwc-hsotg (dwc2) USB host controller emulation code. Based on hw/usb/hcd-ehci.c and hw/usb/hcd-ohci.c. Note that to use this with the dwc-otg driver in the Raspbian kernel, you must pass the option "dwc_otg.fiq_fsm_enable=3D0" on the kernel command line. I have used some on-line sources of information while developing this emulation, including: http://www.capital-micro.com/PDF/CME-M7_Family_User_Guide_EN.pdf has a pretty complete description of the controller starting on page 370. https://sourceforge.net/p/wive-ng/wive-ng-mt/ci/master/tree/docs/DataSheets= /RT3050_5x_V2.0_081408_0902.pdf has a description of the controller registers starting on page 130. Signed-off-by: Paul Zimmerman --- hw/usb/hcd-dwc2.c | 1353 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 1353 insertions(+) create mode 100644 hw/usb/hcd-dwc2.c diff --git a/hw/usb/hcd-dwc2.c b/hw/usb/hcd-dwc2.c new file mode 100644 index 0000000000..fd33190611 --- /dev/null +++ b/hw/usb/hcd-dwc2.c @@ -0,0 +1,1353 @@ +/* + * dwc-hsotg (dwc2) USB host controller emulation + * + * Based on hw/usb/hcd-ehci.c and hw/usb/hcd-ohci.c + * + * Copyright (c) 2020 Paul Zimmerman + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/usb/dwc2-regs.h" +#include "hw/usb/hcd-dwc2.h" +#include "qemu/error-report.h" +#include "qemu/main-loop.h" + +//#define DWC2_DEBUG 1 + +#ifdef DWC2_DEBUG +#define DPRINTF(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__) +#else +#define DPRINTF(fmt, ...) do {} while(0) +#endif + +#define DWC2_DO_SOFS 1 + +#define USB_HZ_FS 12000000 +#define USB_HZ_HS 96000000 + +/* nifty macros from Arnon's EHCI version */ +#define get_field(data, field) \ + (((data) & field##_MASK) >> field##_SHIFT) + +#define set_field(data, newval, field) do { \ + uint32_t val =3D *data; \ + val &=3D ~ field##_MASK; \ + val |=3D ((newval) << field##_SHIFT) & field##_MASK; \ + *data =3D val; \ +} while (0) + +#define get_bit(data, bitmask) \ + (!!((data) & bitmask)) + +/* update irq line */ +static inline void dwc2_update_irq(DWC2State *s) +{ + static int oldlevel; + int level =3D 0; + + if ((s->gintsts & s->gintmsk) && (s->gahbcfg & GAHBCFG_GLBL_INTR_EN)) + level =3D 1; + if (level !=3D oldlevel) { + /*DPRINTF("dwc2_update_irq, sts 0x%08x msk 0x%08x level %d\n", + s->gintsts, s->gintmsk, level);*/ + oldlevel =3D level; + qemu_set_irq(s->irq, level); + } +} + +/* flag interrupt condition */ +static inline void dwc2_raise_global_irq(DWC2State *s, uint32_t intr) +{ + /*DPRINTF("dwc2_raise_global_irq, 0x%08x\n", intr);*/ + s->gintsts |=3D intr; + dwc2_update_irq(s); +} + +static inline void dwc2_lower_global_irq(DWC2State *s, uint32_t intr) +{ + /*DPRINTF("dwc2_lower_global_irq, 0x%08x\n", intr);*/ + s->gintsts &=3D ~intr; + dwc2_update_irq(s); +} + +static inline void dwc2_raise_host_irq(DWC2State *s, uint32_t intr) +{ + /*DPRINTF("dwc2_raise_host_irq, 0x%04x\n", intr);*/ + s->haint |=3D intr; + s->haint &=3D 0xffff; + if (s->haint & s->haintmsk) { + dwc2_raise_global_irq(s, GINTSTS_HCHINT); + } +} + +static inline void dwc2_lower_host_irq(DWC2State *s, uint32_t intr) +{ + /*DPRINTF("dwc2_lower_host_irq, 0x%04x\n", intr);*/ + s->haint &=3D ~intr; + if (!(s->haint & s->haintmsk)) { + dwc2_lower_global_irq(s, GINTSTS_HCHINT); + } +} + +static inline void dwc2_update_hc_irq(DWC2State *s, int index) +{ + uint32_t intr =3D 1 << (index >> 3); + + /*DPRINTF("dwc2_update_hc_irq, hcint%d 0x%04x hcintmsk%d 0x%04x\n", + index >> 3, s->hreg1[index + 2], index >> 3, s->hreg1[index + = 3]);*/ + if (s->hreg1[index + 2] & s->hreg1[index + 3]) { + dwc2_raise_host_irq(s, intr); + } else { + dwc2_lower_host_irq(s, intr); + } +} + +/* set a timer for EOF */ +static void dwc2_eof_timer(DWC2State *s) +{ +#ifdef DWC2_DO_SOFS + timer_mod(s->eof_timer, s->sof_time + s->usb_frame_time); +#endif +} + +#ifdef DWC2_DO_SOFS +/* Set a timer for EOF and generate a SOF event */ +static void dwc2_sof(DWC2State *s) +{ + s->sof_time +=3D s->usb_frame_time; + dwc2_eof_timer(s); + dwc2_raise_global_irq(s, GINTSTS_SOF); +} + +/* Do frame processing on frame boundary */ +static void dwc2_frame_boundary(void *opaque) +{ + DWC2State *s =3D opaque; + + /* Frame boundary, so do EOF stuff here */ + + /* Increment frame number */ + s->frame_number =3D (s->frame_number + 1) & 0xffff; + s->hfnum =3D (s->hfnum & ~HFNUM_FRNUM_MASK) | + (s->frame_number & HFNUM_MAX_FRNUM); + + /* Do SOF stuff here */ + dwc2_sof(s); +} +#endif + +/* Start sending SOF tokens across the USB bus, lists are processed in + * next frame + */ +static int dwc2_bus_start(DWC2State *s) +{ + /* Delay the first SOF event by one frame time as + * linux driver is not ready to receive it and + * can meet some race conditions + */ + + s->sof_time =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + dwc2_eof_timer(s); + + return 1; +} + +/* Stop sending SOF tokens on the bus */ +static void dwc2_bus_stop(DWC2State *s) +{ +#ifdef DWC2_DO_SOFS + timer_del(s->eof_timer); +#endif +} + +static USBDevice *dwc2_find_device(DWC2State *s, uint8_t addr) +{ + USBDevice *dev; + USBPort *port; + int i; + + DPRINTF("dwc2_find_device\n"); + for (i =3D 0; i < NB_PORTS; i++) { + port =3D &s->ports[i]; + if (!(s->hprt0 & HPRT0_ENA)) { + DPRINTF("Port %d not enabled\n", i); + continue; + } + dev =3D usb_find_device(port, addr); + if (dev !=3D NULL) { + DPRINTF("found device\n"); + return dev; + } + } + DPRINTF("device NOT found\n"); + return NULL; +} + +static const char *pstatus[] =3D { + "USB_RET_SUCCESS", "USB_RET_NODEV", "USB_RET_NAK", "USB_RET_STALL", + "USB_RET_BABBLE", "USB_RET_IOERROR", "USB_RET_ASYNC", + "USB_RET_ADD_TO_QUEUE", "USB_RET_REMOVE_FROM_QUEUE" +}; + +static uint32_t pintr[] =3D { + HCINTMSK_XFERCOMPL, HCINTMSK_XACTERR, HCINTMSK_NAK, HCINTMSK_STALL, + HCINTMSK_BBLERR, HCINTMSK_XACTERR, HCINTMSK_XACTERR, HCINTMSK_XACTERR, + HCINTMSK_XACTERR +}; + +#ifdef DWC2_DEBUG +static const char *types[] =3D { + "Ctrl", "Isoc", "Bulk", "Intr" +}; + +static const char *dirs[] =3D { + "Out", "In" +}; +#endif + +static void dwc2_handle_packet(DWC2State *s, USBDevice *dev, USBEndpoint *= ep, + uint32_t index, bool send) { + DWC2Packet *p; + uint32_t hcchar =3D s->hreg1[index]; + uint32_t hctsiz =3D s->hreg1[index + 4]; + uint32_t hcdma =3D s->hreg1[index + 5]; + uint32_t chan, epnum, epdir, eptype, mps, pid, pcnt, len, tlen, intr = =3D 0; + uint32_t tpcnt, stsidx, actual =3D 0; + int i; + bool done =3D false; + + epnum =3D get_field(hcchar, HCCHAR_EPNUM); + epdir =3D get_bit(hcchar, HCCHAR_EPDIR); + eptype =3D get_field(hcchar, HCCHAR_EPTYPE); + mps =3D get_field(hcchar, HCCHAR_MPS); + pid =3D get_field(hctsiz, TSIZ_SC_MC_PID); + pcnt =3D get_field(hctsiz, TSIZ_PKTCNT); + len =3D get_field(hctsiz, TSIZ_XFERSIZE); + assert(len <=3D MAX_XFER_SIZE); + chan =3D index >> 3; + p =3D &s->packet[chan]; + + DPRINTF("dwc2_handle_packet," + " ch %d dev %p pkt %p ep %d type %s dir %s mps %d len %d pcnt = %d\n", + chan, dev, &p->packet, epnum, types[eptype], dirs[epdir], mps,= len, + pcnt); + + if (eptype =3D=3D USB_ENDPOINT_XFER_CONTROL && pid =3D=3D TSIZ_SC_MC_P= ID_SETUP) { + pid =3D USB_TOKEN_SETUP; + } else { + pid =3D epdir ? USB_TOKEN_IN : USB_TOKEN_OUT; + } + + tlen =3D len; + if (p->small) { + if (tlen > mps) { + tlen =3D mps; + } + } + + if (send) { + if (pid !=3D USB_TOKEN_IN) { + DPRINTF("calling dma_memory_read, len %u\n", tlen); + if (dma_memory_read(&s->dma_as, hcdma, + s->usb_buf[chan], tlen) !=3D MEMTX_OK) { + fprintf(stderr, "dma_memory_read failed\n"); + } + if (tlen > 0) { + for (i =3D 0; i < 8; i++) + DPRINTF(" %02x", s->usb_buf[chan][i]); + DPRINTF("\n"); + } + } + + usb_packet_init(&p->packet); + usb_packet_setup(&p->packet, pid, ep, 0, hcdma, + pid !=3D USB_TOKEN_IN, true); + usb_packet_addbuf(&p->packet, s->usb_buf[chan], tlen); + p->async =3D DWC2_ASYNC_NONE; + usb_handle_packet(dev, &p->packet); + } + + stsidx =3D -p->packet.status; + assert(stsidx < sizeof(pstatus) / sizeof(*pstatus)); + DPRINTF("packet status %s len %d\n", pstatus[stsidx], + p->packet.actual_length); + if (p->packet.status !=3D USB_RET_SUCCESS && + p->packet.status !=3D USB_RET_NAK && + p->packet.status !=3D USB_RET_STALL) { + fprintf(stderr, "dwc2_handle_packet: packet status %s\n", + pstatus[stsidx]); + } + + if (p->packet.status =3D=3D USB_RET_ASYNC) { + usb_device_flush_ep_queue(dev, ep); + assert(p->async !=3D DWC2_ASYNC_INFLIGHT); + p->dev =3D dev; + p->ep =3D ep; + p->index =3D index; + p->epnum =3D epnum; + p->mps =3D mps; + p->pid =3D pid; + p->pcnt =3D pcnt; + p->len =3D tlen; + p->needs_service =3D false; + p->async =3D DWC2_ASYNC_INFLIGHT; + return; + } + + if (p->packet.status =3D=3D USB_RET_SUCCESS) { + actual =3D p->packet.actual_length; + if (pid =3D=3D USB_TOKEN_IN) { + DPRINTF("calling dma_memory_write, len %u\n", actual); + if (dma_memory_write(&s->dma_as, hcdma, s->usb_buf[chan], + actual) !=3D MEMTX_OK) { + fprintf(stderr, "dma_memory_write failed\n"); + } + if (actual > 0) { + for (i =3D 0; i < 8; i++) + DPRINTF(" %02x", s->usb_buf[chan][i]); + DPRINTF("\n"); + } + } + + tpcnt =3D actual / mps; + if (actual % mps) { + tpcnt++; + if (pid =3D=3D USB_TOKEN_IN) + done =3D true; + } + + pcnt -=3D tpcnt < pcnt ? tpcnt : pcnt; + set_field(&hctsiz, pcnt, TSIZ_PKTCNT); + len -=3D actual < len ? actual : len; + set_field(&hctsiz, len, TSIZ_XFERSIZE); + s->hreg1[index + 4] =3D hctsiz; + + hcdma +=3D actual; + s->hreg1[index + 5] =3D hcdma; + + if (!pcnt || len =3D=3D 0 || actual =3D=3D 0) { + done =3D true; + } + } else { + intr |=3D pintr[stsidx]; + if (p->packet.status =3D=3D USB_RET_NAK && + (eptype =3D=3D USB_ENDPOINT_XFER_CONTROL || + eptype =3D=3D USB_ENDPOINT_XFER_BULK)) { + /* for ctrl/bulk, automatically retry on NAK, + but send the interrupt anyway */ + intr &=3D ~HCINTMSK_RESERVED14_31; + s->hreg1[index + 2] |=3D intr; + } else { + intr |=3D HCINTMSK_CHHLTD; + done =3D true; + } + } + + usb_packet_cleanup(&p->packet); + + if (done) { + hcchar &=3D ~HCCHAR_CHENA; + s->hreg1[index] =3D hcchar; + if (!(intr & HCINTMSK_CHHLTD)) { + intr |=3D HCINTMSK_CHHLTD | HCINTMSK_XFERCOMPL; + } + intr &=3D ~HCINTMSK_RESERVED14_31; + s->hreg1[index + 2] |=3D intr; + p->needs_service =3D false; + DPRINTF("done %s len %d actual %d pcnt %d\n", pstatus[stsidx], len= , actual, pcnt); + dwc2_update_hc_irq(s, index); + return; + } + + p->dev =3D dev; + p->ep =3D ep; + p->index =3D index; + p->epnum =3D epnum; + p->mps =3D mps; + p->pid =3D pid; + p->pcnt =3D pcnt; + p->len =3D tlen; + p->needs_service =3D true; + DPRINTF("cont %s len %d actual %d pcnt %d\n", pstatus[stsidx], len, ac= tual, pcnt); +} + +/* Attach or detach a device on root hub */ + +static void dwc2_attach(USBPort *port) +{ + DWC2State *s =3D port->opaque; + int hispd =3D 0; + + DPRINTF("dwc2_attach, port %p\n", port); + assert(port->index < NB_PORTS); + + if (!port->dev || !port->dev->attached) + return; + + s->hprt0 &=3D ~HPRT0_SPD_MASK; + + switch (port->dev->speed) { + case USB_SPEED_LOW: + DPRINTF("low-speed device attached\n"); + s->hprt0 |=3D HPRT0_SPD_LOW_SPEED << HPRT0_SPD_SHIFT; + break; + case USB_SPEED_FULL: + DPRINTF("full-speed device attached\n"); + s->hprt0 |=3D HPRT0_SPD_FULL_SPEED << HPRT0_SPD_SHIFT; + break; + case USB_SPEED_HIGH: + DPRINTF("high-speed device attached\n"); + s->hprt0 |=3D HPRT0_SPD_HIGH_SPEED << HPRT0_SPD_SHIFT; + hispd =3D 1; + break; + } + + if (hispd) { + s->usb_frame_time =3D NANOSECONDS_PER_SECOND / 8000; /* 125= 000 */ + if (NANOSECONDS_PER_SECOND >=3D USB_HZ_HS) { + s->usb_bit_time =3D NANOSECONDS_PER_SECOND / USB_HZ_HS; /* 10.= 4 */ + } else { + s->usb_bit_time =3D 1; + } + } else { + s->usb_frame_time =3D NANOSECONDS_PER_SECOND / 1000; /* 100= 0000 */ + if (NANOSECONDS_PER_SECOND >=3D USB_HZ_FS) { + s->usb_bit_time =3D NANOSECONDS_PER_SECOND / USB_HZ_FS; /* 83.= 3 */ + } else { + s->usb_bit_time =3D 1; + } + } + + s->fi =3D 11999; + s->hprt0 |=3D HPRT0_CONNDET | HPRT0_CONNSTS; + + dwc2_bus_start(s); + dwc2_raise_global_irq(s, GINTSTS_PRTINT); +} + +static void dwc2_detach(USBPort *port) +{ + DWC2State *s =3D port->opaque; + + DPRINTF("dwc2_detach, port %p\n", port); + assert(port->index < NB_PORTS); + + dwc2_bus_stop(s); + + s->hprt0 &=3D ~(HPRT0_SPD_MASK | HPRT0_SUSP | HPRT0_ENA | HPRT0_CONNST= S); + s->hprt0 |=3D HPRT0_CONNDET | HPRT0_ENACHG; + + dwc2_raise_global_irq(s, GINTSTS_PRTINT); +} + +static void dwc2_child_detach(USBPort *port, USBDevice *child) +{ + DPRINTF("dwc2_child_detach, port %p child %p\n", port, child); + assert(port->index < NB_PORTS); +} + +static void dwc2_wakeup(USBPort *port) +{ + DWC2State *s =3D port->opaque; + + DPRINTF("dwc2_wakeup, port %p\n", port); + assert(port->index < NB_PORTS); + + if (s->hprt0 & HPRT0_SUSP) { + s->hprt0 |=3D HPRT0_RES; + dwc2_raise_global_irq(s, GINTSTS_PRTINT); + } + + qemu_bh_schedule(s->async_bh); +} + +static void dwc2_async_complete_packet(USBPort *port, USBPacket *packet) +{ + DWC2State *s =3D port->opaque; + DWC2Packet *p; + + DPRINTF("dwc2_async_complete_packet, port %p packet %p\n", port, packe= t); + assert(port->index < NB_PORTS); + + p =3D container_of(packet, DWC2Packet, packet); + DPRINTF("ch %d dev %p epnum %d\n", p->index >> 3, p->dev, p->epnum); + assert(p->async =3D=3D DWC2_ASYNC_INFLIGHT); + + if (packet->status =3D=3D USB_RET_REMOVE_FROM_QUEUE) { + usb_packet_cleanup(packet); + return; + } + + dwc2_handle_packet(s, p->dev, p->ep, p->index, false); + + p->async =3D DWC2_ASYNC_FINISHED; + qemu_bh_schedule(s->async_bh); +} + +static USBPortOps dwc2_port_ops =3D { + .attach =3D dwc2_attach, + .detach =3D dwc2_detach, + .child_detach =3D dwc2_child_detach, + .wakeup =3D dwc2_wakeup, + .complete =3D dwc2_async_complete_packet, +}; + +static uint32_t dwc2_get_frame_remaining(DWC2State *s) +{ + uint32_t fr =3D 0; + int64_t tks; + + tks =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->sof_time; + if (tks < 0) { + tks =3D 0; + } + + /* avoid muldiv if possible */ + if (tks >=3D s->usb_frame_time || tks < s->usb_bit_time) { + goto out; + } + + /* tks =3D number of ns since SOF, divided by 83 (fs) or 10 (hs) */ + tks =3D tks / s->usb_bit_time; + if (tks >=3D (int64_t)s->fi) { + goto out; + } + + /* remaining =3D frame interval minus tks */ + fr =3D (uint32_t)((int64_t)s->fi - tks); + +out: + return fr; +} + +static void dwc2_work_bh(void *opaque) +{ + DWC2State *s =3D opaque; + DWC2Packet *p; + int64_t t_now, expire_time; + int chan; + bool done =3D false, need_timer =3D false; + + DPRINTF("dwc2_work_bh\n"); + if (s->working) { + return; + } + s->working =3D true; + + t_now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + chan =3D s->next_chan; + + while (true) { + p =3D &s->packet[chan]; + if (p->needs_service) { + DPRINTF("start %d servicing ch %d dev %p epnum %d\n", + s->next_chan, chan, p->dev, p->epnum); + dwc2_handle_packet(s, p->dev, p->ep, p->index, true); + need_timer =3D true; + done =3D true; + } + if (++chan =3D=3D NB_CHAN) { + chan =3D 0; + } + if (done) { + s->next_chan =3D chan; + DPRINTF("next %d\n", chan); + break; + } + if (chan =3D=3D s->next_chan) { + break; + } + } + + if (need_timer) { + expire_time =3D t_now + NANOSECONDS_PER_SECOND / 4000; + timer_mod(s->frame_timer, expire_time); + } + s->working =3D false; +} + +static void dwc2_enable_chan(DWC2State *s, uint32_t index) +{ + USBDevice *dev; + USBEndpoint *ep; + uint32_t hcchar; + uint32_t hctsiz; + uint32_t devadr, epnum, epdir, eptype, pid, len; + DWC2Packet *p; + + assert((index >> 3) < NB_CHAN); + p =3D &s->packet[index >> 3]; + hcchar =3D s->hreg1[index]; + hctsiz =3D s->hreg1[index + 4]; + devadr =3D get_field(hcchar, HCCHAR_DEVADDR); + epnum =3D get_field(hcchar, HCCHAR_EPNUM); + epdir =3D get_bit(hcchar, HCCHAR_EPDIR); + eptype =3D get_field(hcchar, HCCHAR_EPTYPE); + pid =3D get_field(hctsiz, TSIZ_SC_MC_PID); + len =3D get_field(hctsiz, TSIZ_XFERSIZE); + + dev =3D dwc2_find_device(s, devadr); + + DPRINTF("dwc2_enable_chan, ch %d dev %p pkt %p epnum %d\n", + index >> 3, dev, &p->packet, epnum); + if (dev =3D=3D NULL) { + fprintf(stderr, "no device found\n"); + return; + } + + if (eptype =3D=3D USB_ENDPOINT_XFER_CONTROL && pid =3D=3D TSIZ_SC_MC_P= ID_SETUP) { + pid =3D USB_TOKEN_SETUP; + } else { + pid =3D epdir ? USB_TOKEN_IN : USB_TOKEN_OUT; + } + + ep =3D usb_ep_get(dev, pid, epnum); + + /* Hack: Networking doesn't like us delivering large transfers, it kind + * of works but the latency is horrible. So if the tansfer is <=3D the= mtu + * size, we take that as a hint that this might be a network transfer, + * and do the transfer packet-by-packet. + */ + if (len > 1536) { + p->small =3D false; + } else { + p->small =3D true; + } + + dwc2_handle_packet(s, dev, ep, index, true); + qemu_bh_schedule(s->async_bh); +} + +#ifdef DWC2_DEBUG +static const char *glbregnm[] =3D { + "GOTGCTL ", "GOTGINT ", "GAHBCFG ", "GUSBCFG ", "GRSTCTL ", "GINT= STS ", + "GINTMSK ", "GRXSTSR ", "GRXSTSP ", "GRXFSIZ ", "GNPTXFSIZ", "GNPT= XSTS ", + "GI2CCTL ", "GPVNDCTL ", "GGPIO ", "GUID ", "GSNPSID ", "GHWC= FG1 ", + "GHWCFG2 ", "GHWCFG3 ", "GHWCFG4 ", "GLPMCFG ", "GPWRDN ", "GDFI= FOCFG", + "GADPCTL ", "GREFCLK ", "GINTMSK2 ", "GINTSTS2 " +}; +#endif + +static uint64_t dwc2_glbreg_read(void *ptr, hwaddr addr, unsigned size) +{ + DWC2State *s =3D ptr; + uint32_t reg =3D s->glbregbase + addr; + uint32_t val; + + assert(reg <=3D GINTSTS2); + val =3D s->glbreg[addr >> 2]; + + switch (reg) { + case GRSTCTL: + /* clear any self-clearing bits that were set */ + val &=3D ~(GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH | GRSTCTL_IN_TKNQ_FLS= H | + GRSTCTL_FRMCNTRRST | GRSTCTL_HSFTRST | GRSTCTL_CSFTRST); + s->glbreg[addr >> 2] =3D val; + break; + default: + break; + } + + if (reg !=3D GAHBCFG && reg !=3D GINTSTS && reg !=3D GINTMSK && reg != =3D GSNPSID) { + DPRINTF("dwc2_glbreg_read 0x%04lx %s val 0x%08x\n", + addr, glbregnm[addr >> 2], val); + } + + return val; +} + +static void dwc2_glbreg_write(void *ptr, hwaddr addr, uint64_t val, + unsigned size) +{ + DWC2State *s =3D ptr; + uint32_t reg =3D s->glbregbase + addr; + uint32_t *mmio; + uint32_t old; + int iflg =3D 0; + + assert(reg <=3D GINTSTS2); + mmio =3D &s->glbreg[addr >> 2]; + old =3D *mmio; + + if (reg !=3D GINTSTS && reg !=3D GINTMSK) { + DPRINTF("dwc2_glbreg_write 0x%04lx %s val 0x%08lx old 0x%08x ", + addr, glbregnm[addr >> 2], val, old); + } + + switch (reg) { + case GOTGCTL: + /* don't allow setting of read-only bits */ + val &=3D ~(GOTGCTL_MULT_VALID_BC_MASK | GOTGCTL_BSESVLD | + GOTGCTL_ASESVLD | GOTGCTL_DBNC_SHORT | GOTGCTL_CONID_B | + GOTGCTL_HSTNEGSCS | GOTGCTL_SESREQSCS); + /* don't allow clearing of read-only bits */ + val |=3D old & (GOTGCTL_MULT_VALID_BC_MASK | GOTGCTL_BSESVLD | + GOTGCTL_ASESVLD | GOTGCTL_DBNC_SHORT | GOTGCTL_CONID= _B | + GOTGCTL_HSTNEGSCS | GOTGCTL_SESREQSCS); + break; + case GAHBCFG: + if ((val & GAHBCFG_GLBL_INTR_EN) && !(old & GAHBCFG_GLBL_INTR_EN))= { + iflg =3D 1; + } + break; + case GRSTCTL: + val |=3D GRSTCTL_AHBIDLE; + val &=3D ~GRSTCTL_DMAREQ; + if (!(old & GRSTCTL_TXFFLSH) && (val & GRSTCTL_TXFFLSH)) { + /* TODO - TX fifo flush */ + } + if (!(old & GRSTCTL_RXFFLSH) && (val & GRSTCTL_RXFFLSH)) { + /* TODO - RX fifo flush */ + } + if (!(old & GRSTCTL_IN_TKNQ_FLSH) && (val & GRSTCTL_IN_TKNQ_FLSH))= { + /* TODO - device IN token queue flush */ + } + if (!(old & GRSTCTL_FRMCNTRRST) && (val & GRSTCTL_FRMCNTRRST)) { + /* TODO - host frame counter reset */ + } + if (!(old & GRSTCTL_HSFTRST) && (val & GRSTCTL_HSFTRST)) { + /* TODO - ? soft reset */ + } + if (!(old & GRSTCTL_CSFTRST) && (val & GRSTCTL_CSFTRST)) { + /* TODO - core soft reset */ + } + /* don't allow clearing of self-clearing bits */ + val |=3D old & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH | + GRSTCTL_IN_TKNQ_FLSH | GRSTCTL_FRMCNTRRST | + GRSTCTL_HSFTRST | GRSTCTL_CSFTRST); + break; + case GINTSTS: + /* clear the write-1-to-clear bits */ + val |=3D ~old; + val =3D ~val; + /* don't allow clearing of read-only bits */ + val |=3D old & (GINTSTS_PTXFEMP | GINTSTS_HCHINT | GINTSTS_PRTINT | + GINTSTS_OEPINT | GINTSTS_IEPINT | GINTSTS_GOUTNAKEFF= | + GINTSTS_GINNAKEFF | GINTSTS_NPTXFEMP | GINTSTS_RXFLV= L | + GINTSTS_OTGINT | GINTSTS_CURMODE_HOST); + iflg =3D 1; + break; + case GINTMSK: + iflg =3D 1; + break; + default: + break; + } + + val &=3D 0xffffffff; + if (reg !=3D GINTSTS && reg !=3D GINTMSK) { + DPRINTF("result 0x%08lx\n", val); + } + *mmio =3D val; + if (iflg) { + dwc2_update_irq(s); + } +} + +static uint64_t dwc2_fszreg_read(void *ptr, hwaddr addr, unsigned size) +{ + DWC2State *s =3D ptr; + uint32_t reg =3D s->fszregbase + addr; + uint32_t val; + + assert(reg <=3D HPTXFSIZ); + val =3D s->fszreg[addr >> 2]; + + DPRINTF("dwc2_fszreg_read 0x%04lx HPTXFSIZ val 0x%08x\n", + addr, val); + return val; +} + +static void dwc2_fszreg_write(void *ptr, hwaddr addr, uint64_t val, + unsigned size) +{ + DWC2State *s =3D ptr; + uint32_t reg =3D s->fszregbase + addr; + uint32_t *mmio; +#ifdef DWC2_DEBUG + uint32_t old; +#endif + + assert(reg <=3D HPTXFSIZ); + mmio =3D &s->fszreg[addr >> 2]; +#ifdef DWC2_DEBUG + old =3D *mmio; +#endif + + DPRINTF("dwc2_fszreg_write 0x%04lx HPTXFSIZ val 0x%08lx old 0x%08x ", + addr, val, old); + val &=3D 0xffffffff; + DPRINTF("result 0x%lx\n", val); + *mmio =3D val; +} + +#ifdef DWC2_DEBUG +static const char *hreg0nm[] =3D { + "HCFG ", "HFIR ", "HFNUM ", " ", "HPTXSTS ", "HAIN= T ", + "HAINTMSK ", "HFLBADDR ", " ", " ", " ", " ", + " ", " ", " ", " ", "HPRT0 " +}; +#endif + +static uint64_t dwc2_hreg0_read(void *ptr, hwaddr addr, unsigned size) +{ + DWC2State *s =3D ptr; + uint32_t reg =3D s->hreg0base + addr; + uint32_t val; + + assert(reg <=3D HPRT0); + val =3D s->hreg0[addr >> 2]; + + switch (reg) { + case HFNUM: + val =3D (dwc2_get_frame_remaining(s) << HFNUM_FRREM_SHIFT) | + ((s->frame_number & HFNUM_MAX_FRNUM) << HFNUM_FRNUM_SHIFT); + break; + default: + break; + } + + if (reg !=3D HFNUM) { + DPRINTF("dwc2_hreg0_read 0x%04lx %s val 0x%08x\n", + addr, hreg0nm[addr >> 2], val); + } + return val; +} + +static void dwc2_hreg0_write(void *ptr, hwaddr addr, uint64_t val, + unsigned size) +{ + DWC2State *s =3D ptr; + uint32_t reg =3D s->hreg0base + addr; + USBDevice *dev =3D s->ports[0].dev; + uint32_t *mmio; + uint32_t tval, told, old; + int prst =3D 0; + int iflg =3D 0; + + assert(reg <=3D HPRT0); + mmio =3D &s->hreg0[addr >> 2]; + old =3D *mmio; + + DPRINTF("dwc2_hreg0_write 0x%04lx %s val 0x%08lx old 0x%08x ", + addr, hreg0nm[addr >> 2], val, old); + + switch (reg) { + case HFIR: + break; + case HFNUM: + case HPTXSTS: + case HAINT: + DPRINTF("**write to read-only register**\n"); + return; + case HAINTMSK: + val &=3D 0xffff; + break; + case HPRT0: + /* don't allow clearing of read-only bits */ + val |=3D old & (HPRT0_SPD_MASK | HPRT0_LNSTS_MASK | HPRT0_OVRCURRA= CT | + HPRT0_CONNSTS); + /* don't allow clearing of self-clearing bits */ + val |=3D old & (HPRT0_SUSP | HPRT0_RES); + /* don't allow setting of self-setting bits */ + if (!(old & HPRT0_ENA) && (val & HPRT0_ENA)) { + val &=3D ~HPRT0_ENA; + } + /* clear the write-1-to-clear bits */ + tval =3D val & (HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_ENA | HPRT= 0_CONNDET); + told =3D old & (HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_ENA | HPRT= 0_CONNDET); + tval |=3D ~told; + tval =3D ~tval; + tval &=3D (HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_ENA | HPRT0_CON= NDET); + val &=3D ~(HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_ENA | HPRT0_CON= NDET); + val |=3D tval; + if (!(val & HPRT0_RST) && (old & HPRT0_RST)) { + if (dev && dev->attached) { + val |=3D HPRT0_ENA | HPRT0_ENACHG; + prst =3D 1; + } + } + if (val & (HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_CONNDET)) { + iflg =3D 1; + } else { + iflg =3D -1; + } + break; + default: + break; + } + + if (prst) { + DPRINTF("call usb_port_reset\n"); + usb_port_reset(&s->ports[0]); + val &=3D ~HPRT0_CONNDET; + } + val &=3D 0xffffffff; + DPRINTF("result 0x%08lx\n", val); + *mmio =3D val; + if (iflg) { + if (iflg > 0) { + DPRINTF("enable PRTINT\n"); + dwc2_raise_global_irq(s, GINTSTS_PRTINT); + } else { + DPRINTF("disable PRTINT\n"); + dwc2_lower_global_irq(s, GINTSTS_PRTINT); + } + } +} + +#ifdef DWC2_DEBUG +static const char *hreg1nm[] =3D { + "HCCHAR ", "HCSPLT ", "HCINT ", "HCINTMSK", "HCTSIZ ", "HCDMA ", + " ", "HCDMAB " +}; +#endif + +static uint64_t dwc2_hreg1_read(void *ptr, hwaddr addr, unsigned size) +{ + DWC2State *s =3D ptr; + uint32_t reg =3D s->hreg1base + addr; + uint32_t val; + + assert(reg <=3D HCDMAB(NB_CHAN - 1)); + val =3D s->hreg1[addr >> 2]; + + DPRINTF("dwc2_hreg1_read 0x%04lx %s%ld val 0x%08x\n", + addr, hreg1nm[(addr >> 2) & 7], addr >> 5, val); + assert(s->hreg1base + (addr & 0x1c) <=3D HCDMAB(NB_CHAN)); + return val; +} + +static void dwc2_hreg1_write(void *ptr, hwaddr addr, uint64_t val, + unsigned size) +{ + DWC2State *s =3D ptr; + uint32_t reg =3D s->hreg1base + addr; + uint32_t *mmio; + uint32_t old; + int iflg =3D 0; + int enflg =3D 0; + int disflg =3D 0; + + assert(reg <=3D HCDMAB(NB_CHAN - 1)); + mmio =3D &s->hreg1[addr >> 2]; + old =3D *mmio; + + DPRINTF("dwc2_hreg1_write 0x%04lx %s%ld val 0x%08lx old 0x%08x ", + addr, hreg1nm[(addr >> 2) & 7], addr >> 5, val, old); + + switch (s->hreg1base + (addr & 0x1c)) { + case HCCHAR(0): + if ((val & HCCHAR_CHDIS) && !(old & HCCHAR_CHDIS)) { + val &=3D ~(HCCHAR_CHENA | HCCHAR_CHDIS); + disflg =3D 1; + } else { + val |=3D old & HCCHAR_CHDIS; + if ((val & HCCHAR_CHENA) && !(old & HCCHAR_CHENA)) { + val &=3D ~HCCHAR_CHDIS; + enflg =3D 1; + } else { + val |=3D old & HCCHAR_CHENA; + } + } + break; + case HCINT(0): + /* clear the write-1-to-clear bits */ + val |=3D ~old; + val =3D ~val; + val &=3D ~HCINTMSK_RESERVED14_31; + iflg =3D 1; + break; + case HCINTMSK(0): + val &=3D ~HCINTMSK_RESERVED14_31; + iflg =3D 1; + break; + case HCDMAB(0): + DPRINTF("**write to read-only register**\n"); + return; + default: + break; + } + + val &=3D 0xffffffff; + DPRINTF("result 0x%08lx\n", val); + *mmio =3D val; + if (disflg) { + /* set ChHltd in HCINT */ + s->hreg1[((addr >> 2) & ~7) + 2] |=3D HCINTMSK_CHHLTD; + iflg =3D 1; + } + if (enflg) { + dwc2_enable_chan(s, (addr >> 2) & ~7); + } + if (iflg) { + dwc2_update_hc_irq(s, (addr >> 2) & ~7); + } +} + +#ifdef DWC2_DEBUG +static const char *pcgregnm[] =3D { + "PCGCTL ", "PCGCCTL1 " +}; +#endif + +static uint64_t dwc2_pcgreg_read(void *ptr, hwaddr addr, unsigned size) +{ + DWC2State *s =3D ptr; + uint32_t reg =3D s->pcgregbase + addr; + uint32_t val; + + assert(reg <=3D PCGCCTL1); + val =3D s->pcgreg[addr >> 2]; + + DPRINTF("dwc2_pcgreg_read 0x%04lx %s val 0x%08x\n", + addr, pcgregnm[addr >> 2], val); + return val; +} + +static void dwc2_pcgreg_write(void *ptr, hwaddr addr, uint64_t val, + unsigned size) +{ + DWC2State *s =3D ptr; + uint32_t reg =3D s->pcgregbase + addr; + uint32_t *mmio; +#ifdef DWC2_DEBUG + uint32_t old; +#endif + + assert(reg <=3D PCGCCTL1); + mmio =3D &s->pcgreg[addr >> 2]; +#ifdef DWC2_DEBUG + old =3D *mmio; +#endif + + DPRINTF("dwc2_pcgreg_write 0x%04lx %s val 0x%08lx old 0x%08x ", + addr, pcgregnm[addr >> 2], val, old); + val &=3D 0xffffffff; + DPRINTF("result 0x%08lx\n", val); + *mmio =3D val; +} + +static uint64_t dwc2_hreg2_read(void *ptr, hwaddr addr, unsigned size) +{ + /* TODO - implement FIFOs to support slave mode */ + DPRINTF("dwc2_hreg2_read 0x%04lx FIFO%ld val 0x%08x\n", + addr, addr >> 12, 0); + return 0; +} + +static void dwc2_hreg2_write(void *ptr, hwaddr addr, uint64_t val, + unsigned size) +{ + /* TODO - implement FIFOs to support slave mode */ + DPRINTF("dwc2_hreg2_write 0x%04lx FIFO%ld val 0x%08lx ", + addr, addr >> 12, val); + val &=3D 0xffffffff; + DPRINTF("result 0x%08lx\n", val); +} + +static const MemoryRegionOps dwc2_mmio_glbreg_ops =3D { + .read =3D dwc2_glbreg_read, + .write =3D dwc2_glbreg_write, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static const MemoryRegionOps dwc2_mmio_fszreg_ops =3D { + .read =3D dwc2_fszreg_read, + .write =3D dwc2_fszreg_write, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static const MemoryRegionOps dwc2_mmio_hreg0_ops =3D { + .read =3D dwc2_hreg0_read, + .write =3D dwc2_hreg0_write, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static const MemoryRegionOps dwc2_mmio_hreg1_ops =3D { + .read =3D dwc2_hreg1_read, + .write =3D dwc2_hreg1_write, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static const MemoryRegionOps dwc2_mmio_pcgreg_ops =3D { + .read =3D dwc2_pcgreg_read, + .write =3D dwc2_pcgreg_write, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static const MemoryRegionOps dwc2_mmio_hreg2_ops =3D { + .read =3D dwc2_hreg2_read, + .write =3D dwc2_hreg2_write, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static void dwc2_wakeup_endpoint(USBBus *bus, USBEndpoint *ep, + unsigned int stream) +{ + DWC2State *s =3D container_of(bus, DWC2State, bus); + + /* TODO - do something here? */ + qemu_bh_schedule(s->async_bh); +} + +static USBBusOps dwc2_bus_ops =3D { + .wakeup_endpoint =3D dwc2_wakeup_endpoint, +}; + +static void dwc2_work_timer(void *opaque) +{ + DWC2State *s =3D opaque; + + DPRINTF("dwc2_work_timer\n"); + qemu_bh_schedule(s->async_bh); +} + +/* host controller initialization */ +static void dwc2_reset(DWC2State *s) +{ + USBDevice *devs[NB_PORTS]; + int i; + + DPRINTF("dwc2_reset, s %p\n", s); + timer_del(s->frame_timer); + qemu_bh_cancel(s->async_bh); + + for (i =3D 0; i < NB_PORTS; i++) { + devs[i] =3D s->ports[i].dev; + if (devs[i] && devs[i]->attached) { + usb_detach(&s->ports[i]); + } + } + + dwc2_bus_stop(s); + + s->gotgctl =3D GOTGCTL_BSESVLD | GOTGCTL_ASESVLD | GOTGCTL_CONID_B; + s->gotgint =3D 0; + s->gahbcfg =3D 0; + s->gusbcfg =3D 5 << GUSBCFG_USBTRDTIM_SHIFT; + s->grstctl =3D GRSTCTL_AHBIDLE; + s->gintsts =3D GINTSTS_CONIDSTSCHNG | GINTSTS_PTXFEMP | GINTSTS_NPTXFE= MP | + GINTSTS_CURMODE_HOST; + s->gintmsk =3D 0; + s->grxstsr =3D 0; + s->grxstsp =3D 0; + s->grxfsiz =3D 1024; + s->gnptxfsiz =3D 1024 << FIFOSIZE_DEPTH_SHIFT; + s->gnptxsts =3D (4 << FIFOSIZE_DEPTH_SHIFT) | 1024; + s->gi2cctl =3D GI2CCTL_I2CDATSE0 | GI2CCTL_ACK; + s->gpvndctl =3D 0; + s->ggpio =3D 0; + s->guid =3D 0; + s->gsnpsid =3D 0x4f54294a; + s->ghwcfg1 =3D 0; + s->ghwcfg2 =3D (8 << GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT) | + (4 << GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT) | + (4 << GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT) | + GHWCFG2_DYNAMIC_FIFO | + GHWCFG2_PERIO_EP_SUPPORTED | + ((NB_CHAN - 1) << GHWCFG2_NUM_HOST_CHAN_SHIFT) | + (GHWCFG2_INT_DMA_ARCH << GHWCFG2_ARCHITECTURE_SHIFT) | + (GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST << GHWCFG2_OP_MODE_S= HIFT); + s->ghwcfg3 =3D (4096 << GHWCFG3_DFIFO_DEPTH_SHIFT) | + (4 << GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT) | + (4 << GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT); + s->ghwcfg4 =3D 0; + s->glpmcfg =3D 0; + s->gpwrdn =3D GPWRDN_PWRDNRSTN; + s->gdfifocfg =3D 0; + s->gadpctl =3D 0; + s->grefclk =3D 0; + s->gintmsk2 =3D 0; + s->gintsts2 =3D 0; + + s->hptxfsiz =3D 500 << FIFOSIZE_DEPTH_SHIFT; + + s->hcfg =3D 2 << HCFG_RESVALID_SHIFT; + s->hfir =3D 60000; + s->hfnum =3D 0x3fff; + s->hptxsts =3D (16 << TXSTS_QSPCAVAIL_SHIFT) | 32768; + s->haint =3D 0; + s->haintmsk =3D 0; + s->hprt0 =3D 0; + + memset(s->hreg1, 0, sizeof(s->hreg1)); + memset(s->pcgreg, 0, sizeof(s->pcgreg)); + + s->sof_time =3D 0; + s->fsmps =3D 0x2778; + s->fi =3D 11999; + s->frame_number =3D 0; + + for (i =3D 0; i < NB_CHAN; i++) { + s->packet[i].needs_service =3D false; + } + + dwc2_update_irq(s); + + for (i =3D 0; i < NB_PORTS; i++) { + s->hprt0 =3D HPRT0_PWR; + if (devs[i] && devs[i]->attached) { + usb_attach(&s->ports[i]); + usb_device_reset(devs[i]); + } + } +} + +static void dwc2_realize(DWC2State *s, DeviceState *dev, Error **errp) +{ + Object *obj; + Error *err =3D NULL; + int i; + + DPRINTF("dwc2_realize, s %p dev %p\n", s, dev); + if (s->portnr > NB_PORTS) { + error_setg(errp, "Too many ports! Max port number is %d", + NB_PORTS); + return; + } + + obj =3D object_property_get_link(OBJECT(dev), "dma-mr", &err); + if (err || obj =3D=3D NULL) { + error_setg(errp, "dwc2: required dma-mr link not found: %s", + error_get_pretty(err)); + return; + } + + s->dma_mr =3D MEMORY_REGION(obj); + address_space_init(&s->dma_as, s->dma_mr, NULL); + + usb_bus_new(&s->bus, sizeof(s->bus), &dwc2_bus_ops, dev); + for (i =3D 0; i < s->portnr; i++) { + usb_register_port(&s->bus, &s->ports[i], s, i, &dwc2_port_ops, + USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL | + USB_SPEED_MASK_HIGH); + s->ports[i].dev =3D 0; + } + + s->frame_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, dwc2_work_timer, s= ); + s->async_bh =3D qemu_bh_new(dwc2_work_bh, s); + s->working =3D false; + s->next_chan =3D 0; + s->device =3D dev; +} + +static void dwc2_init(DWC2State *s, DeviceState *dev) +{ + DPRINTF("dwc2_init, s %p dev %p\n", s, dev); + + s->usb_frame_time =3D NANOSECONDS_PER_SECOND / 1000; /* 10000= 00 */ + if (NANOSECONDS_PER_SECOND >=3D USB_HZ_FS) { + s->usb_bit_time =3D NANOSECONDS_PER_SECOND / USB_HZ_FS; /* 83.3 = */ + } else { + s->usb_bit_time =3D 1; + } + + s->fi =3D 11999; + + memory_region_init(&s->mem, OBJECT(dev), "dwc2", DWC2_MMIO_SIZE); + memory_region_init_io(&s->mem_glbreg, OBJECT(dev), &dwc2_mmio_glbreg_o= ps, s, + "global", 0x70); + memory_region_init_io(&s->mem_fszreg, OBJECT(dev), &dwc2_mmio_fszreg_o= ps, s, + "hptxfsiz", 0x4); + memory_region_init_io(&s->mem_hreg0, OBJECT(dev), &dwc2_mmio_hreg0_ops= , s, + "host", 0x44); + memory_region_init_io(&s->mem_hreg1, OBJECT(dev), &dwc2_mmio_hreg1_ops= , s, + "host channels", 0x20 * NB_CHAN); + memory_region_init_io(&s->mem_pcgreg, OBJECT(dev), &dwc2_mmio_pcgreg_o= ps, s, + "power/clock", 0x8); + memory_region_init_io(&s->mem_hreg2, OBJECT(dev), &dwc2_mmio_hreg2_ops= , s, + "host fifos", NB_CHAN * 0x1000); + + memory_region_add_subregion(&s->mem, s->glbregbase, &s->mem_glbreg); + memory_region_add_subregion(&s->mem, s->fszregbase, &s->mem_fszreg); + memory_region_add_subregion(&s->mem, s->hreg0base, &s->mem_hreg0); + memory_region_add_subregion(&s->mem, s->hreg1base, &s->mem_hreg1); + memory_region_add_subregion(&s->mem, s->pcgregbase, &s->mem_pcgreg); + memory_region_add_subregion(&s->mem, s->hreg2base, &s->mem_hreg2); + +#ifdef DWC2_DO_SOFS + s->eof_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, + dwc2_frame_boundary, s); +#endif +} + +static void dwc2_sysbus_reset(DeviceState *dev) +{ + SysBusDevice *d =3D SYS_BUS_DEVICE(dev); + DWC2State *s =3D DWC2_USB(d); + + DPRINTF("dwc2_sysbus_reset, dev %p d %p s %p\n", dev, d, s); + dwc2_reset(s); +} + +static void dwc2_sysbus_realize(DeviceState *dev, Error **errp) +{ + SysBusDevice *d =3D SYS_BUS_DEVICE(dev); + DWC2State *s =3D DWC2_USB(dev); + + DPRINTF("dwc2_sysbus_realize, dev %p d %p s %p\n", dev, d, s); + s->glbregbase =3D 0; + s->fszregbase =3D 0x0100; + s->hreg0base =3D 0x0400; + s->hreg1base =3D 0x0500; + s->pcgregbase =3D 0x0e00; + s->hreg2base =3D 0x1000; + s->portnr =3D NB_PORTS; + s->as =3D &address_space_memory; + + DPRINTF("0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", s->glbregbase, s->fszregbas= e, + s->hreg0base, s->hreg1base, s->pcgregbase, s->hreg2base); + dwc2_realize(s, dev, errp); + dwc2_init(s, dev); + sysbus_init_irq(d, &s->irq); + sysbus_init_mmio(d, &s->mem); +} + +static void dwc2_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + DPRINTF("dwc2_class_init, class %p dc %p\n", klass, dc); + dc->realize =3D dwc2_sysbus_realize; + dc->reset =3D dwc2_sysbus_reset; + set_bit(DEVICE_CATEGORY_USB, dc->categories); +} + +static const TypeInfo dwc2_usb_type_info =3D { + .name =3D TYPE_DWC2_USB, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(DWC2State), + .class_init =3D dwc2_class_init, +}; + +static void dwc2_usb_register_types(void) +{ + DPRINTF("dwc2_usb_register_types\n"); + type_register_static(&dwc2_usb_type_info); +} + +type_init(dwc2_usb_register_types) --=20 2.17.1