From nobody Fri May 3 21:45:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1584916176; cv=none; d=zohomail.com; s=zohoarc; b=ZadWVIlIkx15GxCF9mAQLDT+/H/TvF3qMNWwbUufDPwsWzWSuWO2h0Z2/UqPVKpVKcvB+RwllTdEDfA7EQu8L1oynzL2ta8HTfwd5t1L6GKVLWoTCmt7TUQa6TLnVkPNIpOQR5A/wHO09hvu3rouSTAetkZDp5kDr4IruaXYxMU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1584916176; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=OdBk7fBl+khEi1+sSGi994OMCvR7ndIiJGrmG/gZmGo=; b=RiHQ2gbjhjlhXjNfpG5Qu4fFUdhH5FEwe7JQIupMAyavtxVF158Xb1r0QSd/vCjFfc/xqRRB1h6urOrHdw100oQRYaWoVcHUz1v22dR7uc6QKK0NvoILDXXOzYWVYACLTOYScDJLJ0AnT59fjMjkEiuDd5clheVIq9BkPvb/W84= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1584916176713731.1302655030172; Sun, 22 Mar 2020 15:29:36 -0700 (PDT) Received: from localhost ([::1]:50480 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jG967-0006MK-Ct for importer@patchew.org; Sun, 22 Mar 2020 18:29:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50093) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jG952-0005Hm-J7 for qemu-devel@nongnu.org; Sun, 22 Mar 2020 18:28:31 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jG950-0001fx-Pi for qemu-devel@nongnu.org; Sun, 22 Mar 2020 18:28:28 -0400 Received: from mail-pj1-x1042.google.com ([2607:f8b0:4864:20::1042]:51956) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1jG950-0001fa-Je for qemu-devel@nongnu.org; Sun, 22 Mar 2020 18:28:26 -0400 Received: by mail-pj1-x1042.google.com with SMTP id hg10so5214741pjb.1 for ; Sun, 22 Mar 2020 15:28:26 -0700 (PDT) Received: from localhost.localdomain ([75.167.220.149]) by smtp.gmail.com with ESMTPSA id e10sm11440315pfm.121.2020.03.22.15.28.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 22 Mar 2020 15:28:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=OdBk7fBl+khEi1+sSGi994OMCvR7ndIiJGrmG/gZmGo=; b=UNX8GcxDDpXI2Tf02unvG94JXmfhmrkgajRcBhFXxyd+2BPcs3A//osXmWONViISTZ TdRldqhA4LW97JPzbvnfHe5VQ0OpUxNR+Kisr8FFL3vTeLZmeZFF1fMDXeAm8DKXeD9t PJNSNo+8Q6/bwryEbAk0dP3mQ9m9FRP0bB1PRF9e4OhfV6Q2nDJ9cC44AbLpkpj0V2rb ByxIdt4OnzzCBqoDmAouefS6Sy6QOSWxEBKwKZXU5BNdBmMfkPsx34p6H3FoPC7pSFJz ZTnvvIOD24d7GPTeA3qjJRvZAKjgjsM+kiYY78oHt62UykqV2TJlyVW1dP9mWzYa42mQ R9lw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=OdBk7fBl+khEi1+sSGi994OMCvR7ndIiJGrmG/gZmGo=; b=q5Jz1lbf7QSdVgMStBixWpVhj3BsKTW7WRVK/Tzt03AzQdao9vo5GJNVZlWKL2R1qJ JI4KctC/PALAHm3OODbVLW27G7W9ipMsBsGHaBRygrYSKmUWQn8gMMG/5xzSYNomJCVP xtpUvv8BmvRst5beIcX33lhmeR2Zq69E0ZgJnHPqWmA5lDdFo7M24Bfb4IWreRlBiR6g LJeFfITU9O/g2lrB/P+0ptIfAghJy381VpxJfYwmIlQynyarG735ukzmNrVT4seBMGY9 zQm6gUiJAu1b8LXYUJZQhkIU70lXgTAGmh687qcMbhjZWYGIWT/kHzyvIBdo4ZPTuKeJ Wq+A== X-Gm-Message-State: ANhLgQ3ziDPGVgvF99LxLbLSJmqBwlZzPutsaFwexRWSe0be6ovlofK+ L9xYOqor8Lgw5BobejZZses= X-Google-Smtp-Source: ADFU+vvII6vv7jEiiNg7n1ZgEpsQckUqS3ly3m5BCnbMsrtl7cIYmh1JfQaMPAVvU30Weg+sR7ubOQ== X-Received: by 2002:a17:90a:3acc:: with SMTP id b70mr21568068pjc.179.1584916105582; Sun, 22 Mar 2020 15:28:25 -0700 (PDT) From: Paul Zimmerman To: kraxel@redhat.com Subject: [PATCH 1/6] Add BCM2835 SOC MPHI emulation Date: Sun, 22 Mar 2020 15:27:21 -0700 Message-Id: <20200322222726.10244-2-pauldzim@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200322222726.10244-1-pauldzim@gmail.com> References: <20200322222726.10244-1-pauldzim@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1042 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, stefanha@gmail.com, qemu-devel@nongnu.org, Paul Zimmerman , jsnow@redhat.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add BCM2835 SOC MPHI emulation. It is very basic, only providing the FIQ interrupt needed to allow the dwc-otg USB host controller driver in the Raspbian kernel to function. Signed-off-by: Paul Zimmerman --- hw/arm/bcm2835_peripherals.c | 17 +++ hw/misc/Makefile.objs | 1 + hw/misc/bcm2835_mphi.c | 215 +++++++++++++++++++++++++++ include/hw/arm/bcm2835_peripherals.h | 2 + include/hw/misc/bcm2835_mphi.h | 50 +++++++ 5 files changed, 285 insertions(+) create mode 100644 hw/misc/bcm2835_mphi.c create mode 100644 include/hw/misc/bcm2835_mphi.h diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c index 17207ae07e..dd7e6883cb 100644 --- a/hw/arm/bcm2835_peripherals.c +++ b/hw/arm/bcm2835_peripherals.c @@ -123,6 +123,10 @@ static void bcm2835_peripherals_init(Object *obj) sysbus_init_child_obj(obj, "gpio", &s->gpio, sizeof(s->gpio), TYPE_BCM2835_GPIO); =20 + /* Mphi */ + sysbus_init_child_obj(obj, "mphi", &s->mphi, sizeof(s->mphi), + TYPE_BCM2835_MPHI); + object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhci", OBJECT(&s->sdhci.sdbus), &error_abort); object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhost", @@ -367,6 +371,19 @@ static void bcm2835_peripherals_realize(DeviceState *d= ev, Error **errp) return; } =20 + /* Mphi */ + object_property_set_bool(OBJECT(&s->mphi), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + memory_region_add_subregion(&s->peri_mr, MPHI_OFFSET, + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->mphi), 0)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->mphi), 0, + qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, + INTERRUPT_HOSTPORT)); + create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, = 0x40); create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x1000); create_unimp(s, &s->a2w, "bcm2835-a2w", A2W_OFFSET, 0x1000); diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index 68aae2eabb..91085cc21b 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -57,6 +57,7 @@ common-obj-$(CONFIG_OMAP) +=3D omap_l4.o common-obj-$(CONFIG_OMAP) +=3D omap_sdrc.o common-obj-$(CONFIG_OMAP) +=3D omap_tap.o common-obj-$(CONFIG_RASPI) +=3D bcm2835_mbox.o +common-obj-$(CONFIG_RASPI) +=3D bcm2835_mphi.o common-obj-$(CONFIG_RASPI) +=3D bcm2835_property.o common-obj-$(CONFIG_RASPI) +=3D bcm2835_rng.o common-obj-$(CONFIG_RASPI) +=3D bcm2835_thermal.o diff --git a/hw/misc/bcm2835_mphi.c b/hw/misc/bcm2835_mphi.c new file mode 100644 index 0000000000..32433ce156 --- /dev/null +++ b/hw/misc/bcm2835_mphi.c @@ -0,0 +1,215 @@ +/* + * BCM2835 SOC MPHI emulation + * + * Very basic emulation, only providing the FIQ interrupt needed to + * allow the dwc-otg USB host controller driver in the Raspbian kernel + * to function. + * + * Copyright (c) 2020 Paul Zimmerman + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/misc/bcm2835_mphi.h" +#include "qemu/error-report.h" +#include "qemu/main-loop.h" + +//#define MPHI_DEBUG 1 + +#ifdef MPHI_DEBUG +#define DPRINTF(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__) +#else +#define DPRINTF(fmt, ...) do {} while(0) +#endif + +static inline void mphi_raise_irq(BCM2835MphiState *s) +{ + DPRINTF("mphi_raise_irq, s %p\n", s); + qemu_set_irq(s->irq, 1); +} + +static inline void mphi_lower_irq(BCM2835MphiState *s) +{ + DPRINTF("mphi_lower_irq, s %p\n", s); + qemu_set_irq(s->irq, 0); +} + +static uint64_t mphi_reg_read(void *ptr, hwaddr addr, unsigned size) +{ + BCM2835MphiState *s =3D ptr; + uint32_t reg =3D s->regbase + addr; + uint32_t val =3D 0; + + switch (reg) { + case 0x28: /* outdda */ + val =3D s->outdda; + break; + case 0x2c: /* outddb */ + val =3D s->outddb; + break; + case 0x4c: /* ctrl */ + val =3D s->ctrl; + val |=3D 1 << 17; + break; + case 0x50: /* intstat */ + val =3D s->intstat; + break; + case 0x1f0: /* swirq_set */ + val =3D s->swirq_set; + break; + case 0x1f4: /* swirq_clr */ + val =3D s->swirq_clr; + break; + default: + break; + } + + DPRINTF("mphi_reg_read 0x%04lx val 0x%08x\n", addr, val); + return val; +} + +static void mphi_reg_write(void *ptr, hwaddr addr, uint64_t val, unsigned = size) +{ + BCM2835MphiState *s =3D ptr; + uint32_t reg =3D s->regbase + addr; + uint32_t old; + int do_irq =3D 0; + + DPRINTF("mphi_reg_write 0x%04lx val 0x%08lx ", addr, val); + val &=3D 0xffffffff; + + switch (reg) { + case 0x28: /* outdda */ + old =3D s->outdda; + s->outdda =3D val; + break; + case 0x2c: /* outddb */ + old =3D s->outddb; + s->outddb =3D val; + if (val & (1 << 29)) + do_irq =3D 1; + break; + case 0x4c: /* ctrl */ + old =3D s->ctrl; + s->ctrl =3D val; + if (val & (1 << 16)) + do_irq =3D -1; + break; + case 0x50: /* intstat */ + old =3D s->intstat; + s->intstat =3D val; + if (val & ((1 << 16) | (1 << 29))) + do_irq =3D -1; + break; + case 0x1f0: /* swirq_set */ + old =3D s->swirq_set; + s->swirq_set =3D val; + do_irq =3D 1; + break; + case 0x1f4: /* swirq_clr */ + old =3D s->swirq_clr; + s->swirq_clr =3D val; + do_irq =3D -1; + break; + default: + break; + } + + DPRINTF("old 0x%08x result 0x%08lx\n", old, val); + old =3D old; + if (do_irq > 0) + mphi_raise_irq(s); + else if (do_irq < 0) + mphi_lower_irq(s); +} + +static const MemoryRegionOps mphi_mmio_ops =3D { + .read =3D mphi_reg_read, + .write =3D mphi_reg_write, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static void mphi_realize(BCM2835MphiState *s, DeviceState *dev, Error **er= rp) +{ + DPRINTF("mphi_realize, s %p dev %p\n", s, dev); + s->device =3D dev; +} + +static void mphi_init(BCM2835MphiState *s, DeviceState *dev) +{ + DPRINTF("usb_mphi_init, s %p dev %p\n", s, dev); + + memory_region_init(&s->mem, OBJECT(dev), "mphi", MPHI_MMIO_SIZE); + memory_region_init_io(&s->mem_reg, OBJECT(dev), &mphi_mmio_ops, s, + "global", 0x200); + memory_region_add_subregion(&s->mem, s->regbase, &s->mem_reg); +} + +static void mphi_sysbus_reset(DeviceState *dev) +{ +#ifdef MPHI_DEBUG + SysBusDevice *d =3D SYS_BUS_DEVICE(dev); + BCM2835MphiState *s =3D BCM2835_MPHI(d); +#endif + + DPRINTF("mphi_sysbus_reset, dev %p d %p s %p\n", dev, d, s); +} + +static void mphi_sysbus_realize(DeviceState *dev, Error **errp) +{ + SysBusDevice *d =3D SYS_BUS_DEVICE(dev); + BCM2835MphiState *s =3D BCM2835_MPHI(dev); + + DPRINTF("mphi_sysbus_realize, dev %p d %p s %p\n", dev, d, s); + mphi_realize(s, dev, errp); + sysbus_init_irq(d, &s->irq); +} + +static void mphi_sysbus_init(Object *obj) +{ + SysBusDevice *d =3D SYS_BUS_DEVICE(obj); + BCM2835MphiState *s =3D BCM2835_MPHI(obj); + + DPRINTF("mphi_sysbus_init, obj %p d %p s %p\n", obj, d, s); + s->regbase =3D 0; + s->as =3D &address_space_memory; + mphi_init(s, DEVICE(obj)); + sysbus_init_mmio(d, &s->mem); +} + +static void mphi_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + DPRINTF("mphi_class_init, class %p dc %p\n", klass, dc); + dc->realize =3D mphi_sysbus_realize; + dc->reset =3D mphi_sysbus_reset; +} + +static const TypeInfo bcm2835_mphi_type_info =3D { + .name =3D TYPE_BCM2835_MPHI, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(BCM2835MphiState), + .instance_init =3D mphi_sysbus_init, + .class_init =3D mphi_class_init, +}; + +static void bcm2835_mphi_register_types(void) +{ + DPRINTF("bcm2835_mphi_register_types\n"); + type_register_static(&bcm2835_mphi_type_info); +} + +type_init(bcm2835_mphi_register_types) diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_= peripherals.h index 7859281e11..77958ca60e 100644 --- a/include/hw/arm/bcm2835_peripherals.h +++ b/include/hw/arm/bcm2835_peripherals.h @@ -20,6 +20,7 @@ #include "hw/misc/bcm2835_property.h" #include "hw/misc/bcm2835_rng.h" #include "hw/misc/bcm2835_mbox.h" +#include "hw/misc/bcm2835_mphi.h" #include "hw/misc/bcm2835_thermal.h" #include "hw/sd/sdhci.h" #include "hw/sd/bcm2835_sdhost.h" @@ -41,6 +42,7 @@ typedef struct BCM2835PeripheralState { qemu_irq irq, fiq; =20 BCM2835SystemTimerState systmr; + BCM2835MphiState mphi; UnimplementedDeviceState armtmr; UnimplementedDeviceState cprman; UnimplementedDeviceState a2w; diff --git a/include/hw/misc/bcm2835_mphi.h b/include/hw/misc/bcm2835_mphi.h new file mode 100644 index 0000000000..826ae2af3b --- /dev/null +++ b/include/hw/misc/bcm2835_mphi.h @@ -0,0 +1,50 @@ +/* + * BCM2835 SOC MPHI state definitions + * + * Copyright (c) 2020 Paul Zimmerman + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef HW_MISC_BCM2835_MPHI_H +#define HW_MISC_BCM2835_MPHI_H + +#include "hw/irq.h" +#include "hw/sysbus.h" +#include "sysemu/dma.h" + +#define MPHI_MMIO_SIZE 0x1000 + +typedef struct BCM2835MphiState BCM2835MphiState; + +struct BCM2835MphiState { + SysBusDevice parent_obj; + DeviceState *device; + qemu_irq irq; + AddressSpace *as; + MemoryRegion mem; + MemoryRegion mem_reg; + uint16_t regbase; + + uint32_t outdda; + uint32_t outddb; + uint32_t ctrl; + uint32_t intstat; + uint32_t swirq_set; + uint32_t swirq_clr; +}; + +#define TYPE_BCM2835_MPHI "bcm2835-mphi" + +#define BCM2835_MPHI(obj) \ + OBJECT_CHECK(BCM2835MphiState, (obj), TYPE_BCM2835_MPHI) + +#endif --=20 2.17.1 From nobody Fri May 3 21:45:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=CCnfu1Z748v+6BTrHSgS8Uo5vb6agk/mdt+wqRNnq6U=; b=iZfJ8+wTaIwsXh8k+ay4R08Tzu6F40TcAP7cwMVolzgGDWTReHiMFbTf0bR+q7pD0k PhgEz8an8tSJ/45OkFm0hNV6lCjAKCwRvNMcpuCCMhWJuBB97DoBDcMJQ1s9GWlTBF3k Nci7qydDSsPiVHj70Mocpnxb9HbcabjBrlguuY+wHixWOgEVhlSZnes59c5GdsvlB/8l EAtjRg05i6/+NovMfGtU6w9AulwTR8rlQyHehRWckXbVIsA5C3Zr3pjGSGrJ6/lUBZeV GmwfMdAjnz0w7MZkg7AsUs27r1aBPkgWLeEnqlVEV+4Mrwvc+vLpJqwpccwYSRom2xvn emXQ== X-Gm-Message-State: ANhLgQ2em3ZKGRU3I7XgtILgGDTDKeqqms16BUtacB2Fbpq10begxB8e wyVFnYqTA+yGE6DZWdcwsRc= X-Google-Smtp-Source: ADFU+vvBZUeAYKOdMzXyr5+kp+Hx3KQ36smHsLcPNvE5t37VGapoGnS+Awlbz5GsyPnZGlHlx47QVA== X-Received: by 2002:a62:3784:: with SMTP id e126mr20847157pfa.50.1584916113467; Sun, 22 Mar 2020 15:28:33 -0700 (PDT) From: Paul Zimmerman To: kraxel@redhat.com Subject: [PATCH 2/6] dwc-hsotg USB host controller register definitions Date: Sun, 22 Mar 2020 15:27:22 -0700 Message-Id: <20200322222726.10244-3-pauldzim@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200322222726.10244-1-pauldzim@gmail.com> References: <20200322222726.10244-1-pauldzim@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::543 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, stefanha@gmail.com, qemu-devel@nongnu.org, Paul Zimmerman , jsnow@redhat.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Import the dwc2 register definitions file from the Linux kernel. This is a copy of drivers/usb/dwc2/hw.h from the mainline Linux kernel, the only changes being two instances of 'u32' changed to 'uint32_t' to allow it to compile Signed-off-by: Paul Zimmerman --- include/hw/usb/dwc2-regs.h | 895 +++++++++++++++++++++++++++++++++++++ 1 file changed, 895 insertions(+) create mode 100644 include/hw/usb/dwc2-regs.h diff --git a/include/hw/usb/dwc2-regs.h b/include/hw/usb/dwc2-regs.h new file mode 100644 index 0000000000..96dc07fb6f --- /dev/null +++ b/include/hw/usb/dwc2-regs.h @@ -0,0 +1,895 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) +/* + * hw.h - DesignWare HS OTG Controller hardware definitions + * + * Copyright 2004-2013 Synopsys, Inc. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions, and the following disclaimer, + * without modification. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. + * 3. The names of the above-listed copyright holders may not be used + * to endorse or promote products derived from this software without + * specific prior written permission. + * + * ALTERNATIVELY, this software may be distributed under the terms of the + * GNU General Public License ("GPL") as published by the Free Software + * Foundation; either version 2 of the License, or (at your option) any + * later version. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS + * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED T= O, + * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR + * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR + * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, + * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, + * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR + * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF + * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING + * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS + * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + */ + +#ifndef __DWC2_HW_H__ +#define __DWC2_HW_H__ + +#define HSOTG_REG(x) (x) + +#define GOTGCTL HSOTG_REG(0x000) +#define GOTGCTL_CHIRPEN BIT(27) +#define GOTGCTL_MULT_VALID_BC_MASK (0x1f << 22) +#define GOTGCTL_MULT_VALID_BC_SHIFT 22 +#define GOTGCTL_OTGVER BIT(20) +#define GOTGCTL_BSESVLD BIT(19) +#define GOTGCTL_ASESVLD BIT(18) +#define GOTGCTL_DBNC_SHORT BIT(17) +#define GOTGCTL_CONID_B BIT(16) +#define GOTGCTL_DBNCE_FLTR_BYPASS BIT(15) +#define GOTGCTL_DEVHNPEN BIT(11) +#define GOTGCTL_HSTSETHNPEN BIT(10) +#define GOTGCTL_HNPREQ BIT(9) +#define GOTGCTL_HSTNEGSCS BIT(8) +#define GOTGCTL_SESREQ BIT(1) +#define GOTGCTL_SESREQSCS BIT(0) + +#define GOTGINT HSOTG_REG(0x004) +#define GOTGINT_DBNCE_DONE BIT(19) +#define GOTGINT_A_DEV_TOUT_CHG BIT(18) +#define GOTGINT_HST_NEG_DET BIT(17) +#define GOTGINT_HST_NEG_SUC_STS_CHNG BIT(9) +#define GOTGINT_SES_REQ_SUC_STS_CHNG BIT(8) +#define GOTGINT_SES_END_DET BIT(2) + +#define GAHBCFG HSOTG_REG(0x008) +#define GAHBCFG_AHB_SINGLE BIT(23) +#define GAHBCFG_NOTI_ALL_DMA_WRIT BIT(22) +#define GAHBCFG_REM_MEM_SUPP BIT(21) +#define GAHBCFG_P_TXF_EMP_LVL BIT(8) +#define GAHBCFG_NP_TXF_EMP_LVL BIT(7) +#define GAHBCFG_DMA_EN BIT(5) +#define GAHBCFG_HBSTLEN_MASK (0xf << 1) +#define GAHBCFG_HBSTLEN_SHIFT 1 +#define GAHBCFG_HBSTLEN_SINGLE 0 +#define GAHBCFG_HBSTLEN_INCR 1 +#define GAHBCFG_HBSTLEN_INCR4 3 +#define GAHBCFG_HBSTLEN_INCR8 5 +#define GAHBCFG_HBSTLEN_INCR16 7 +#define GAHBCFG_GLBL_INTR_EN BIT(0) +#define GAHBCFG_CTRL_MASK (GAHBCFG_P_TXF_EMP_LVL | \ + GAHBCFG_NP_TXF_EMP_LVL | \ + GAHBCFG_DMA_EN | \ + GAHBCFG_GLBL_INTR_EN) + +#define GUSBCFG HSOTG_REG(0x00C) +#define GUSBCFG_FORCEDEVMODE BIT(30) +#define GUSBCFG_FORCEHOSTMODE BIT(29) +#define GUSBCFG_TXENDDELAY BIT(28) +#define GUSBCFG_ICTRAFFICPULLREMOVE BIT(27) +#define GUSBCFG_ICUSBCAP BIT(26) +#define GUSBCFG_ULPI_INT_PROT_DIS BIT(25) +#define GUSBCFG_INDICATORPASSTHROUGH BIT(24) +#define GUSBCFG_INDICATORCOMPLEMENT BIT(23) +#define GUSBCFG_TERMSELDLPULSE BIT(22) +#define GUSBCFG_ULPI_INT_VBUS_IND BIT(21) +#define GUSBCFG_ULPI_EXT_VBUS_DRV BIT(20) +#define GUSBCFG_ULPI_CLK_SUSP_M BIT(19) +#define GUSBCFG_ULPI_AUTO_RES BIT(18) +#define GUSBCFG_ULPI_FS_LS BIT(17) +#define GUSBCFG_OTG_UTMI_FS_SEL BIT(16) +#define GUSBCFG_PHY_LP_CLK_SEL BIT(15) +#define GUSBCFG_USBTRDTIM_MASK (0xf << 10) +#define GUSBCFG_USBTRDTIM_SHIFT 10 +#define GUSBCFG_HNPCAP BIT(9) +#define GUSBCFG_SRPCAP BIT(8) +#define GUSBCFG_DDRSEL BIT(7) +#define GUSBCFG_PHYSEL BIT(6) +#define GUSBCFG_FSINTF BIT(5) +#define GUSBCFG_ULPI_UTMI_SEL BIT(4) +#define GUSBCFG_PHYIF16 BIT(3) +#define GUSBCFG_PHYIF8 (0 << 3) +#define GUSBCFG_TOUTCAL_MASK (0x7 << 0) +#define GUSBCFG_TOUTCAL_SHIFT 0 +#define GUSBCFG_TOUTCAL_LIMIT 0x7 +#define GUSBCFG_TOUTCAL(_x) ((_x) << 0) + +#define GRSTCTL HSOTG_REG(0x010) +#define GRSTCTL_AHBIDLE BIT(31) +#define GRSTCTL_DMAREQ BIT(30) +#define GRSTCTL_TXFNUM_MASK (0x1f << 6) +#define GRSTCTL_TXFNUM_SHIFT 6 +#define GRSTCTL_TXFNUM_LIMIT 0x1f +#define GRSTCTL_TXFNUM(_x) ((_x) << 6) +#define GRSTCTL_TXFFLSH BIT(5) +#define GRSTCTL_RXFFLSH BIT(4) +#define GRSTCTL_IN_TKNQ_FLSH BIT(3) +#define GRSTCTL_FRMCNTRRST BIT(2) +#define GRSTCTL_HSFTRST BIT(1) +#define GRSTCTL_CSFTRST BIT(0) + +#define GINTSTS HSOTG_REG(0x014) +#define GINTMSK HSOTG_REG(0x018) +#define GINTSTS_WKUPINT BIT(31) +#define GINTSTS_SESSREQINT BIT(30) +#define GINTSTS_DISCONNINT BIT(29) +#define GINTSTS_CONIDSTSCHNG BIT(28) +#define GINTSTS_LPMTRANRCVD BIT(27) +#define GINTSTS_PTXFEMP BIT(26) +#define GINTSTS_HCHINT BIT(25) +#define GINTSTS_PRTINT BIT(24) +#define GINTSTS_RESETDET BIT(23) +#define GINTSTS_FET_SUSP BIT(22) +#define GINTSTS_INCOMPL_IP BIT(21) +#define GINTSTS_INCOMPL_SOOUT BIT(21) +#define GINTSTS_INCOMPL_SOIN BIT(20) +#define GINTSTS_OEPINT BIT(19) +#define GINTSTS_IEPINT BIT(18) +#define GINTSTS_EPMIS BIT(17) +#define GINTSTS_RESTOREDONE BIT(16) +#define GINTSTS_EOPF BIT(15) +#define GINTSTS_ISOUTDROP BIT(14) +#define GINTSTS_ENUMDONE BIT(13) +#define GINTSTS_USBRST BIT(12) +#define GINTSTS_USBSUSP BIT(11) +#define GINTSTS_ERLYSUSP BIT(10) +#define GINTSTS_I2CINT BIT(9) +#define GINTSTS_ULPI_CK_INT BIT(8) +#define GINTSTS_GOUTNAKEFF BIT(7) +#define GINTSTS_GINNAKEFF BIT(6) +#define GINTSTS_NPTXFEMP BIT(5) +#define GINTSTS_RXFLVL BIT(4) +#define GINTSTS_SOF BIT(3) +#define GINTSTS_OTGINT BIT(2) +#define GINTSTS_MODEMIS BIT(1) +#define GINTSTS_CURMODE_HOST BIT(0) + +#define GRXSTSR HSOTG_REG(0x01C) +#define GRXSTSP HSOTG_REG(0x020) +#define GRXSTS_FN_MASK (0x7f << 25) +#define GRXSTS_FN_SHIFT 25 +#define GRXSTS_PKTSTS_MASK (0xf << 17) +#define GRXSTS_PKTSTS_SHIFT 17 +#define GRXSTS_PKTSTS_GLOBALOUTNAK 1 +#define GRXSTS_PKTSTS_OUTRX 2 +#define GRXSTS_PKTSTS_HCHIN 2 +#define GRXSTS_PKTSTS_OUTDONE 3 +#define GRXSTS_PKTSTS_HCHIN_XFER_COMP 3 +#define GRXSTS_PKTSTS_SETUPDONE 4 +#define GRXSTS_PKTSTS_DATATOGGLEERR 5 +#define GRXSTS_PKTSTS_SETUPRX 6 +#define GRXSTS_PKTSTS_HCHHALTED 7 +#define GRXSTS_HCHNUM_MASK (0xf << 0) +#define GRXSTS_HCHNUM_SHIFT 0 +#define GRXSTS_DPID_MASK (0x3 << 15) +#define GRXSTS_DPID_SHIFT 15 +#define GRXSTS_BYTECNT_MASK (0x7ff << 4) +#define GRXSTS_BYTECNT_SHIFT 4 +#define GRXSTS_EPNUM_MASK (0xf << 0) +#define GRXSTS_EPNUM_SHIFT 0 + +#define GRXFSIZ HSOTG_REG(0x024) +#define GRXFSIZ_DEPTH_MASK (0xffff << 0) +#define GRXFSIZ_DEPTH_SHIFT 0 + +#define GNPTXFSIZ HSOTG_REG(0x028) +/* Use FIFOSIZE_* constants to access this register */ + +#define GNPTXSTS HSOTG_REG(0x02C) +#define GNPTXSTS_NP_TXQ_TOP_MASK (0x7f << 24) +#define GNPTXSTS_NP_TXQ_TOP_SHIFT 24 +#define GNPTXSTS_NP_TXQ_SPC_AVAIL_MASK (0xff << 16) +#define GNPTXSTS_NP_TXQ_SPC_AVAIL_SHIFT 16 +#define GNPTXSTS_NP_TXQ_SPC_AVAIL_GET(_v) (((_v) >> 16) & 0xff) +#define GNPTXSTS_NP_TXF_SPC_AVAIL_MASK (0xffff << 0) +#define GNPTXSTS_NP_TXF_SPC_AVAIL_SHIFT 0 +#define GNPTXSTS_NP_TXF_SPC_AVAIL_GET(_v) (((_v) >> 0) & 0xffff) + +#define GI2CCTL HSOTG_REG(0x0030) +#define GI2CCTL_BSYDNE BIT(31) +#define GI2CCTL_RW BIT(30) +#define GI2CCTL_I2CDATSE0 BIT(28) +#define GI2CCTL_I2CDEVADDR_MASK (0x3 << 26) +#define GI2CCTL_I2CDEVADDR_SHIFT 26 +#define GI2CCTL_I2CSUSPCTL BIT(25) +#define GI2CCTL_ACK BIT(24) +#define GI2CCTL_I2CEN BIT(23) +#define GI2CCTL_ADDR_MASK (0x7f << 16) +#define GI2CCTL_ADDR_SHIFT 16 +#define GI2CCTL_REGADDR_MASK (0xff << 8) +#define GI2CCTL_REGADDR_SHIFT 8 +#define GI2CCTL_RWDATA_MASK (0xff << 0) +#define GI2CCTL_RWDATA_SHIFT 0 + +#define GPVNDCTL HSOTG_REG(0x0034) +#define GGPIO HSOTG_REG(0x0038) +#define GGPIO_STM32_OTG_GCCFG_PWRDWN BIT(16) + +#define GUID HSOTG_REG(0x003c) +#define GSNPSID HSOTG_REG(0x0040) +#define GHWCFG1 HSOTG_REG(0x0044) +#define GSNPSID_ID_MASK GENMASK(31, 16) + +#define GHWCFG2 HSOTG_REG(0x0048) +#define GHWCFG2_OTG_ENABLE_IC_USB BIT(31) +#define GHWCFG2_DEV_TOKEN_Q_DEPTH_MASK (0x1f << 26) +#define GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT 26 +#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_MASK (0x3 << 24) +#define GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT 24 +#define GHWCFG2_NONPERIO_TX_Q_DEPTH_MASK (0x3 << 22) +#define GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT 22 +#define GHWCFG2_MULTI_PROC_INT BIT(20) +#define GHWCFG2_DYNAMIC_FIFO BIT(19) +#define GHWCFG2_PERIO_EP_SUPPORTED BIT(18) +#define GHWCFG2_NUM_HOST_CHAN_MASK (0xf << 14) +#define GHWCFG2_NUM_HOST_CHAN_SHIFT 14 +#define GHWCFG2_NUM_DEV_EP_MASK (0xf << 10) +#define GHWCFG2_NUM_DEV_EP_SHIFT 10 +#define GHWCFG2_FS_PHY_TYPE_MASK (0x3 << 8) +#define GHWCFG2_FS_PHY_TYPE_SHIFT 8 +#define GHWCFG2_FS_PHY_TYPE_NOT_SUPPORTED 0 +#define GHWCFG2_FS_PHY_TYPE_DEDICATED 1 +#define GHWCFG2_FS_PHY_TYPE_SHARED_UTMI 2 +#define GHWCFG2_FS_PHY_TYPE_SHARED_ULPI 3 +#define GHWCFG2_HS_PHY_TYPE_MASK (0x3 << 6) +#define GHWCFG2_HS_PHY_TYPE_SHIFT 6 +#define GHWCFG2_HS_PHY_TYPE_NOT_SUPPORTED 0 +#define GHWCFG2_HS_PHY_TYPE_UTMI 1 +#define GHWCFG2_HS_PHY_TYPE_ULPI 2 +#define GHWCFG2_HS_PHY_TYPE_UTMI_ULPI 3 +#define GHWCFG2_POINT2POINT BIT(5) +#define GHWCFG2_ARCHITECTURE_MASK (0x3 << 3) +#define GHWCFG2_ARCHITECTURE_SHIFT 3 +#define GHWCFG2_SLAVE_ONLY_ARCH 0 +#define GHWCFG2_EXT_DMA_ARCH 1 +#define GHWCFG2_INT_DMA_ARCH 2 +#define GHWCFG2_OP_MODE_MASK (0x7 << 0) +#define GHWCFG2_OP_MODE_SHIFT 0 +#define GHWCFG2_OP_MODE_HNP_SRP_CAPABLE 0 +#define GHWCFG2_OP_MODE_SRP_ONLY_CAPABLE 1 +#define GHWCFG2_OP_MODE_NO_HNP_SRP_CAPABLE 2 +#define GHWCFG2_OP_MODE_SRP_CAPABLE_DEVICE 3 +#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_DEVICE 4 +#define GHWCFG2_OP_MODE_SRP_CAPABLE_HOST 5 +#define GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST 6 +#define GHWCFG2_OP_MODE_UNDEFINED 7 + +#define GHWCFG3 HSOTG_REG(0x004c) +#define GHWCFG3_DFIFO_DEPTH_MASK (0xffff << 16) +#define GHWCFG3_DFIFO_DEPTH_SHIFT 16 +#define GHWCFG3_OTG_LPM_EN BIT(15) +#define GHWCFG3_BC_SUPPORT BIT(14) +#define GHWCFG3_OTG_ENABLE_HSIC BIT(13) +#define GHWCFG3_ADP_SUPP BIT(12) +#define GHWCFG3_SYNCH_RESET_TYPE BIT(11) +#define GHWCFG3_OPTIONAL_FEATURES BIT(10) +#define GHWCFG3_VENDOR_CTRL_IF BIT(9) +#define GHWCFG3_I2C BIT(8) +#define GHWCFG3_OTG_FUNC BIT(7) +#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_MASK (0x7 << 4) +#define GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT 4 +#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_MASK (0xf << 0) +#define GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT 0 + +#define GHWCFG4 HSOTG_REG(0x0050) +#define GHWCFG4_DESC_DMA_DYN BIT(31) +#define GHWCFG4_DESC_DMA BIT(30) +#define GHWCFG4_NUM_IN_EPS_MASK (0xf << 26) +#define GHWCFG4_NUM_IN_EPS_SHIFT 26 +#define GHWCFG4_DED_FIFO_EN BIT(25) +#define GHWCFG4_DED_FIFO_SHIFT 25 +#define GHWCFG4_SESSION_END_FILT_EN BIT(24) +#define GHWCFG4_B_VALID_FILT_EN BIT(23) +#define GHWCFG4_A_VALID_FILT_EN BIT(22) +#define GHWCFG4_VBUS_VALID_FILT_EN BIT(21) +#define GHWCFG4_IDDIG_FILT_EN BIT(20) +#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_MASK (0xf << 16) +#define GHWCFG4_NUM_DEV_MODE_CTRL_EP_SHIFT 16 +#define GHWCFG4_UTMI_PHY_DATA_WIDTH_MASK (0x3 << 14) +#define GHWCFG4_UTMI_PHY_DATA_WIDTH_SHIFT 14 +#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8 0 +#define GHWCFG4_UTMI_PHY_DATA_WIDTH_16 1 +#define GHWCFG4_UTMI_PHY_DATA_WIDTH_8_OR_16 2 +#define GHWCFG4_ACG_SUPPORTED BIT(12) +#define GHWCFG4_IPG_ISOC_SUPPORTED BIT(11) +#define GHWCFG4_SERVICE_INTERVAL_SUPPORTED BIT(10) +#define GHWCFG4_XHIBER BIT(7) +#define GHWCFG4_HIBER BIT(6) +#define GHWCFG4_MIN_AHB_FREQ BIT(5) +#define GHWCFG4_POWER_OPTIMIZ BIT(4) +#define GHWCFG4_NUM_DEV_PERIO_IN_EP_MASK (0xf << 0) +#define GHWCFG4_NUM_DEV_PERIO_IN_EP_SHIFT 0 + +#define GLPMCFG HSOTG_REG(0x0054) +#define GLPMCFG_INVSELHSIC BIT(31) +#define GLPMCFG_HSICCON BIT(30) +#define GLPMCFG_RSTRSLPSTS BIT(29) +#define GLPMCFG_ENBESL BIT(28) +#define GLPMCFG_LPM_RETRYCNT_STS_MASK (0x7 << 25) +#define GLPMCFG_LPM_RETRYCNT_STS_SHIFT 25 +#define GLPMCFG_SNDLPM BIT(24) +#define GLPMCFG_RETRY_CNT_MASK (0x7 << 21) +#define GLPMCFG_RETRY_CNT_SHIFT 21 +#define GLPMCFG_LPM_REJECT_CTRL_CONTROL BIT(21) +#define GLPMCFG_LPM_ACCEPT_CTRL_ISOC BIT(22) +#define GLPMCFG_LPM_CHNL_INDX_MASK (0xf << 17) +#define GLPMCFG_LPM_CHNL_INDX_SHIFT 17 +#define GLPMCFG_L1RESUMEOK BIT(16) +#define GLPMCFG_SLPSTS BIT(15) +#define GLPMCFG_COREL1RES_MASK (0x3 << 13) +#define GLPMCFG_COREL1RES_SHIFT 13 +#define GLPMCFG_HIRD_THRES_MASK (0x1f << 8) +#define GLPMCFG_HIRD_THRES_SHIFT 8 +#define GLPMCFG_HIRD_THRES_EN (0x10 << 8) +#define GLPMCFG_ENBLSLPM BIT(7) +#define GLPMCFG_BREMOTEWAKE BIT(6) +#define GLPMCFG_HIRD_MASK (0xf << 2) +#define GLPMCFG_HIRD_SHIFT 2 +#define GLPMCFG_APPL1RES BIT(1) +#define GLPMCFG_LPMCAP BIT(0) + +#define GPWRDN HSOTG_REG(0x0058) +#define GPWRDN_MULT_VAL_ID_BC_MASK (0x1f << 24) +#define GPWRDN_MULT_VAL_ID_BC_SHIFT 24 +#define GPWRDN_ADP_INT BIT(23) +#define GPWRDN_BSESSVLD BIT(22) +#define GPWRDN_IDSTS BIT(21) +#define GPWRDN_LINESTATE_MASK (0x3 << 19) +#define GPWRDN_LINESTATE_SHIFT 19 +#define GPWRDN_STS_CHGINT_MSK BIT(18) +#define GPWRDN_STS_CHGINT BIT(17) +#define GPWRDN_SRP_DET_MSK BIT(16) +#define GPWRDN_SRP_DET BIT(15) +#define GPWRDN_CONNECT_DET_MSK BIT(14) +#define GPWRDN_CONNECT_DET BIT(13) +#define GPWRDN_DISCONN_DET_MSK BIT(12) +#define GPWRDN_DISCONN_DET BIT(11) +#define GPWRDN_RST_DET_MSK BIT(10) +#define GPWRDN_RST_DET BIT(9) +#define GPWRDN_LNSTSCHG_MSK BIT(8) +#define GPWRDN_LNSTSCHG BIT(7) +#define GPWRDN_DIS_VBUS BIT(6) +#define GPWRDN_PWRDNSWTCH BIT(5) +#define GPWRDN_PWRDNRSTN BIT(4) +#define GPWRDN_PWRDNCLMP BIT(3) +#define GPWRDN_RESTORE BIT(2) +#define GPWRDN_PMUACTV BIT(1) +#define GPWRDN_PMUINTSEL BIT(0) + +#define GDFIFOCFG HSOTG_REG(0x005c) +#define GDFIFOCFG_EPINFOBASE_MASK (0xffff << 16) +#define GDFIFOCFG_EPINFOBASE_SHIFT 16 +#define GDFIFOCFG_GDFIFOCFG_MASK (0xffff << 0) +#define GDFIFOCFG_GDFIFOCFG_SHIFT 0 + +#define ADPCTL HSOTG_REG(0x0060) +#define ADPCTL_AR_MASK (0x3 << 27) +#define ADPCTL_AR_SHIFT 27 +#define ADPCTL_ADP_TMOUT_INT_MSK BIT(26) +#define ADPCTL_ADP_SNS_INT_MSK BIT(25) +#define ADPCTL_ADP_PRB_INT_MSK BIT(24) +#define ADPCTL_ADP_TMOUT_INT BIT(23) +#define ADPCTL_ADP_SNS_INT BIT(22) +#define ADPCTL_ADP_PRB_INT BIT(21) +#define ADPCTL_ADPENA BIT(20) +#define ADPCTL_ADPRES BIT(19) +#define ADPCTL_ENASNS BIT(18) +#define ADPCTL_ENAPRB BIT(17) +#define ADPCTL_RTIM_MASK (0x7ff << 6) +#define ADPCTL_RTIM_SHIFT 6 +#define ADPCTL_PRB_PER_MASK (0x3 << 4) +#define ADPCTL_PRB_PER_SHIFT 4 +#define ADPCTL_PRB_DELTA_MASK (0x3 << 2) +#define ADPCTL_PRB_DELTA_SHIFT 2 +#define ADPCTL_PRB_DSCHRG_MASK (0x3 << 0) +#define ADPCTL_PRB_DSCHRG_SHIFT 0 + +#define GREFCLK HSOTG_REG(0x0064) +#define GREFCLK_REFCLKPER_MASK (0x1ffff << 15) +#define GREFCLK_REFCLKPER_SHIFT 15 +#define GREFCLK_REF_CLK_MODE BIT(14) +#define GREFCLK_SOF_CNT_WKUP_ALERT_MASK (0x3ff) +#define GREFCLK_SOF_CNT_WKUP_ALERT_SHIFT 0 + +#define GINTMSK2 HSOTG_REG(0x0068) +#define GINTMSK2_WKUP_ALERT_INT_MSK BIT(0) + +#define GINTSTS2 HSOTG_REG(0x006c) +#define GINTSTS2_WKUP_ALERT_INT BIT(0) + +#define HPTXFSIZ HSOTG_REG(0x100) +/* Use FIFOSIZE_* constants to access this register */ + +#define DPTXFSIZN(_a) HSOTG_REG(0x104 + (((_a) - 1) * 4)) +/* Use FIFOSIZE_* constants to access this register */ + +/* These apply to the GNPTXFSIZ, HPTXFSIZ and DPTXFSIZN registers */ +#define FIFOSIZE_DEPTH_MASK (0xffff << 16) +#define FIFOSIZE_DEPTH_SHIFT 16 +#define FIFOSIZE_STARTADDR_MASK (0xffff << 0) +#define FIFOSIZE_STARTADDR_SHIFT 0 +#define FIFOSIZE_DEPTH_GET(_x) (((_x) >> 16) & 0xffff) + +/* Device mode registers */ + +#define DCFG HSOTG_REG(0x800) +#define DCFG_DESCDMA_EN BIT(23) +#define DCFG_EPMISCNT_MASK (0x1f << 18) +#define DCFG_EPMISCNT_SHIFT 18 +#define DCFG_EPMISCNT_LIMIT 0x1f +#define DCFG_EPMISCNT(_x) ((_x) << 18) +#define DCFG_IPG_ISOC_SUPPORDED BIT(17) +#define DCFG_PERFRINT_MASK (0x3 << 11) +#define DCFG_PERFRINT_SHIFT 11 +#define DCFG_PERFRINT_LIMIT 0x3 +#define DCFG_PERFRINT(_x) ((_x) << 11) +#define DCFG_DEVADDR_MASK (0x7f << 4) +#define DCFG_DEVADDR_SHIFT 4 +#define DCFG_DEVADDR_LIMIT 0x7f +#define DCFG_DEVADDR(_x) ((_x) << 4) +#define DCFG_NZ_STS_OUT_HSHK BIT(2) +#define DCFG_DEVSPD_MASK (0x3 << 0) +#define DCFG_DEVSPD_SHIFT 0 +#define DCFG_DEVSPD_HS 0 +#define DCFG_DEVSPD_FS 1 +#define DCFG_DEVSPD_LS 2 +#define DCFG_DEVSPD_FS48 3 + +#define DCTL HSOTG_REG(0x804) +#define DCTL_SERVICE_INTERVAL_SUPPORTED BIT(19) +#define DCTL_PWRONPRGDONE BIT(11) +#define DCTL_CGOUTNAK BIT(10) +#define DCTL_SGOUTNAK BIT(9) +#define DCTL_CGNPINNAK BIT(8) +#define DCTL_SGNPINNAK BIT(7) +#define DCTL_TSTCTL_MASK (0x7 << 4) +#define DCTL_TSTCTL_SHIFT 4 +#define DCTL_GOUTNAKSTS BIT(3) +#define DCTL_GNPINNAKSTS BIT(2) +#define DCTL_SFTDISCON BIT(1) +#define DCTL_RMTWKUPSIG BIT(0) + +#define DSTS HSOTG_REG(0x808) +#define DSTS_SOFFN_MASK (0x3fff << 8) +#define DSTS_SOFFN_SHIFT 8 +#define DSTS_SOFFN_LIMIT 0x3fff +#define DSTS_SOFFN(_x) ((_x) << 8) +#define DSTS_ERRATICERR BIT(3) +#define DSTS_ENUMSPD_MASK (0x3 << 1) +#define DSTS_ENUMSPD_SHIFT 1 +#define DSTS_ENUMSPD_HS 0 +#define DSTS_ENUMSPD_FS 1 +#define DSTS_ENUMSPD_LS 2 +#define DSTS_ENUMSPD_FS48 3 +#define DSTS_SUSPSTS BIT(0) + +#define DIEPMSK HSOTG_REG(0x810) +#define DIEPMSK_NAKMSK BIT(13) +#define DIEPMSK_BNAININTRMSK BIT(9) +#define DIEPMSK_TXFIFOUNDRNMSK BIT(8) +#define DIEPMSK_TXFIFOEMPTY BIT(7) +#define DIEPMSK_INEPNAKEFFMSK BIT(6) +#define DIEPMSK_INTKNEPMISMSK BIT(5) +#define DIEPMSK_INTKNTXFEMPMSK BIT(4) +#define DIEPMSK_TIMEOUTMSK BIT(3) +#define DIEPMSK_AHBERRMSK BIT(2) +#define DIEPMSK_EPDISBLDMSK BIT(1) +#define DIEPMSK_XFERCOMPLMSK BIT(0) + +#define DOEPMSK HSOTG_REG(0x814) +#define DOEPMSK_BNAMSK BIT(9) +#define DOEPMSK_BACK2BACKSETUP BIT(6) +#define DOEPMSK_STSPHSERCVDMSK BIT(5) +#define DOEPMSK_OUTTKNEPDISMSK BIT(4) +#define DOEPMSK_SETUPMSK BIT(3) +#define DOEPMSK_AHBERRMSK BIT(2) +#define DOEPMSK_EPDISBLDMSK BIT(1) +#define DOEPMSK_XFERCOMPLMSK BIT(0) + +#define DAINT HSOTG_REG(0x818) +#define DAINTMSK HSOTG_REG(0x81C) +#define DAINT_OUTEP_SHIFT 16 +#define DAINT_OUTEP(_x) (1 << ((_x) + 16)) +#define DAINT_INEP(_x) (1 << (_x)) + +#define DTKNQR1 HSOTG_REG(0x820) +#define DTKNQR2 HSOTG_REG(0x824) +#define DTKNQR3 HSOTG_REG(0x830) +#define DTKNQR4 HSOTG_REG(0x834) +#define DIEPEMPMSK HSOTG_REG(0x834) + +#define DVBUSDIS HSOTG_REG(0x828) +#define DVBUSPULSE HSOTG_REG(0x82C) + +#define DIEPCTL0 HSOTG_REG(0x900) +#define DIEPCTL(_a) HSOTG_REG(0x900 + ((_a) * 0x20)) + +#define DOEPCTL0 HSOTG_REG(0xB00) +#define DOEPCTL(_a) HSOTG_REG(0xB00 + ((_a) * 0x20)) + +/* EP0 specialness: + * bits[29..28] - reserved (no SetD0PID, SetD1PID) + * bits[25..22] - should always be zero, this isn't a periodic endpoint + * bits[10..0] - MPS setting different for EP0 + */ +#define D0EPCTL_MPS_MASK (0x3 << 0) +#define D0EPCTL_MPS_SHIFT 0 +#define D0EPCTL_MPS_64 0 +#define D0EPCTL_MPS_32 1 +#define D0EPCTL_MPS_16 2 +#define D0EPCTL_MPS_8 3 + +#define DXEPCTL_EPENA BIT(31) +#define DXEPCTL_EPDIS BIT(30) +#define DXEPCTL_SETD1PID BIT(29) +#define DXEPCTL_SETODDFR BIT(29) +#define DXEPCTL_SETD0PID BIT(28) +#define DXEPCTL_SETEVENFR BIT(28) +#define DXEPCTL_SNAK BIT(27) +#define DXEPCTL_CNAK BIT(26) +#define DXEPCTL_TXFNUM_MASK (0xf << 22) +#define DXEPCTL_TXFNUM_SHIFT 22 +#define DXEPCTL_TXFNUM_LIMIT 0xf +#define DXEPCTL_TXFNUM(_x) ((_x) << 22) +#define DXEPCTL_STALL BIT(21) +#define DXEPCTL_SNP BIT(20) +#define DXEPCTL_EPTYPE_MASK (0x3 << 18) +#define DXEPCTL_EPTYPE_CONTROL (0x0 << 18) +#define DXEPCTL_EPTYPE_ISO (0x1 << 18) +#define DXEPCTL_EPTYPE_BULK (0x2 << 18) +#define DXEPCTL_EPTYPE_INTERRUPT (0x3 << 18) + +#define DXEPCTL_NAKSTS BIT(17) +#define DXEPCTL_DPID BIT(16) +#define DXEPCTL_EOFRNUM BIT(16) +#define DXEPCTL_USBACTEP BIT(15) +#define DXEPCTL_NEXTEP_MASK (0xf << 11) +#define DXEPCTL_NEXTEP_SHIFT 11 +#define DXEPCTL_NEXTEP_LIMIT 0xf +#define DXEPCTL_NEXTEP(_x) ((_x) << 11) +#define DXEPCTL_MPS_MASK (0x7ff << 0) +#define DXEPCTL_MPS_SHIFT 0 +#define DXEPCTL_MPS_LIMIT 0x7ff +#define DXEPCTL_MPS(_x) ((_x) << 0) + +#define DIEPINT(_a) HSOTG_REG(0x908 + ((_a) * 0x20)) +#define DOEPINT(_a) HSOTG_REG(0xB08 + ((_a) * 0x20)) +#define DXEPINT_SETUP_RCVD BIT(15) +#define DXEPINT_NYETINTRPT BIT(14) +#define DXEPINT_NAKINTRPT BIT(13) +#define DXEPINT_BBLEERRINTRPT BIT(12) +#define DXEPINT_PKTDRPSTS BIT(11) +#define DXEPINT_BNAINTR BIT(9) +#define DXEPINT_TXFIFOUNDRN BIT(8) +#define DXEPINT_OUTPKTERR BIT(8) +#define DXEPINT_TXFEMP BIT(7) +#define DXEPINT_INEPNAKEFF BIT(6) +#define DXEPINT_BACK2BACKSETUP BIT(6) +#define DXEPINT_INTKNEPMIS BIT(5) +#define DXEPINT_STSPHSERCVD BIT(5) +#define DXEPINT_INTKNTXFEMP BIT(4) +#define DXEPINT_OUTTKNEPDIS BIT(4) +#define DXEPINT_TIMEOUT BIT(3) +#define DXEPINT_SETUP BIT(3) +#define DXEPINT_AHBERR BIT(2) +#define DXEPINT_EPDISBLD BIT(1) +#define DXEPINT_XFERCOMPL BIT(0) + +#define DIEPTSIZ0 HSOTG_REG(0x910) +#define DIEPTSIZ0_PKTCNT_MASK (0x3 << 19) +#define DIEPTSIZ0_PKTCNT_SHIFT 19 +#define DIEPTSIZ0_PKTCNT_LIMIT 0x3 +#define DIEPTSIZ0_PKTCNT(_x) ((_x) << 19) +#define DIEPTSIZ0_XFERSIZE_MASK (0x7f << 0) +#define DIEPTSIZ0_XFERSIZE_SHIFT 0 +#define DIEPTSIZ0_XFERSIZE_LIMIT 0x7f +#define DIEPTSIZ0_XFERSIZE(_x) ((_x) << 0) + +#define DOEPTSIZ0 HSOTG_REG(0xB10) +#define DOEPTSIZ0_SUPCNT_MASK (0x3 << 29) +#define DOEPTSIZ0_SUPCNT_SHIFT 29 +#define DOEPTSIZ0_SUPCNT_LIMIT 0x3 +#define DOEPTSIZ0_SUPCNT(_x) ((_x) << 29) +#define DOEPTSIZ0_PKTCNT BIT(19) +#define DOEPTSIZ0_XFERSIZE_MASK (0x7f << 0) +#define DOEPTSIZ0_XFERSIZE_SHIFT 0 + +#define DIEPTSIZ(_a) HSOTG_REG(0x910 + ((_a) * 0x20)) +#define DOEPTSIZ(_a) HSOTG_REG(0xB10 + ((_a) * 0x20)) +#define DXEPTSIZ_MC_MASK (0x3 << 29) +#define DXEPTSIZ_MC_SHIFT 29 +#define DXEPTSIZ_MC_LIMIT 0x3 +#define DXEPTSIZ_MC(_x) ((_x) << 29) +#define DXEPTSIZ_PKTCNT_MASK (0x3ff << 19) +#define DXEPTSIZ_PKTCNT_SHIFT 19 +#define DXEPTSIZ_PKTCNT_LIMIT 0x3ff +#define DXEPTSIZ_PKTCNT_GET(_v) (((_v) >> 19) & 0x3ff) +#define DXEPTSIZ_PKTCNT(_x) ((_x) << 19) +#define DXEPTSIZ_XFERSIZE_MASK (0x7ffff << 0) +#define DXEPTSIZ_XFERSIZE_SHIFT 0 +#define DXEPTSIZ_XFERSIZE_LIMIT 0x7ffff +#define DXEPTSIZ_XFERSIZE_GET(_v) (((_v) >> 0) & 0x7ffff) +#define DXEPTSIZ_XFERSIZE(_x) ((_x) << 0) + +#define DIEPDMA(_a) HSOTG_REG(0x914 + ((_a) * 0x20)) +#define DOEPDMA(_a) HSOTG_REG(0xB14 + ((_a) * 0x20)) + +#define DTXFSTS(_a) HSOTG_REG(0x918 + ((_a) * 0x20)) + +#define PCGCTL HSOTG_REG(0x0e00) +#define PCGCTL_IF_DEV_MODE BIT(31) +#define PCGCTL_P2HD_PRT_SPD_MASK (0x3 << 29) +#define PCGCTL_P2HD_PRT_SPD_SHIFT 29 +#define PCGCTL_P2HD_DEV_ENUM_SPD_MASK (0x3 << 27) +#define PCGCTL_P2HD_DEV_ENUM_SPD_SHIFT 27 +#define PCGCTL_MAC_DEV_ADDR_MASK (0x7f << 20) +#define PCGCTL_MAC_DEV_ADDR_SHIFT 20 +#define PCGCTL_MAX_TERMSEL BIT(19) +#define PCGCTL_MAX_XCVRSELECT_MASK (0x3 << 17) +#define PCGCTL_MAX_XCVRSELECT_SHIFT 17 +#define PCGCTL_PORT_POWER BIT(16) +#define PCGCTL_PRT_CLK_SEL_MASK (0x3 << 14) +#define PCGCTL_PRT_CLK_SEL_SHIFT 14 +#define PCGCTL_ESS_REG_RESTORED BIT(13) +#define PCGCTL_EXTND_HIBER_SWITCH BIT(12) +#define PCGCTL_EXTND_HIBER_PWRCLMP BIT(11) +#define PCGCTL_ENBL_EXTND_HIBER BIT(10) +#define PCGCTL_RESTOREMODE BIT(9) +#define PCGCTL_RESETAFTSUSP BIT(8) +#define PCGCTL_DEEP_SLEEP BIT(7) +#define PCGCTL_PHY_IN_SLEEP BIT(6) +#define PCGCTL_ENBL_SLEEP_GATING BIT(5) +#define PCGCTL_RSTPDWNMODULE BIT(3) +#define PCGCTL_PWRCLMP BIT(2) +#define PCGCTL_GATEHCLK BIT(1) +#define PCGCTL_STOPPCLK BIT(0) + +#define PCGCCTL1 HSOTG_REG(0xe04) +#define PCGCCTL1_TIMER (0x3 << 1) +#define PCGCCTL1_GATEEN BIT(0) + +#define EPFIFO(_a) HSOTG_REG(0x1000 + ((_a) * 0x1000)) + +/* Host Mode Registers */ + +#define HCFG HSOTG_REG(0x0400) +#define HCFG_MODECHTIMEN BIT(31) +#define HCFG_PERSCHEDENA BIT(26) +#define HCFG_FRLISTEN_MASK (0x3 << 24) +#define HCFG_FRLISTEN_SHIFT 24 +#define HCFG_FRLISTEN_8 (0 << 24) +#define FRLISTEN_8_SIZE 8 +#define HCFG_FRLISTEN_16 BIT(24) +#define FRLISTEN_16_SIZE 16 +#define HCFG_FRLISTEN_32 (2 << 24) +#define FRLISTEN_32_SIZE 32 +#define HCFG_FRLISTEN_64 (3 << 24) +#define FRLISTEN_64_SIZE 64 +#define HCFG_DESCDMA BIT(23) +#define HCFG_RESVALID_MASK (0xff << 8) +#define HCFG_RESVALID_SHIFT 8 +#define HCFG_ENA32KHZ BIT(7) +#define HCFG_FSLSSUPP BIT(2) +#define HCFG_FSLSPCLKSEL_MASK (0x3 << 0) +#define HCFG_FSLSPCLKSEL_SHIFT 0 +#define HCFG_FSLSPCLKSEL_30_60_MHZ 0 +#define HCFG_FSLSPCLKSEL_48_MHZ 1 +#define HCFG_FSLSPCLKSEL_6_MHZ 2 + +#define HFIR HSOTG_REG(0x0404) +#define HFIR_FRINT_MASK (0xffff << 0) +#define HFIR_FRINT_SHIFT 0 +#define HFIR_RLDCTRL BIT(16) + +#define HFNUM HSOTG_REG(0x0408) +#define HFNUM_FRREM_MASK (0xffff << 16) +#define HFNUM_FRREM_SHIFT 16 +#define HFNUM_FRNUM_MASK (0xffff << 0) +#define HFNUM_FRNUM_SHIFT 0 +#define HFNUM_MAX_FRNUM 0x3fff + +#define HPTXSTS HSOTG_REG(0x0410) +#define TXSTS_QTOP_ODD BIT(31) +#define TXSTS_QTOP_CHNEP_MASK (0xf << 27) +#define TXSTS_QTOP_CHNEP_SHIFT 27 +#define TXSTS_QTOP_TOKEN_MASK (0x3 << 25) +#define TXSTS_QTOP_TOKEN_SHIFT 25 +#define TXSTS_QTOP_TERMINATE BIT(24) +#define TXSTS_QSPCAVAIL_MASK (0xff << 16) +#define TXSTS_QSPCAVAIL_SHIFT 16 +#define TXSTS_FSPCAVAIL_MASK (0xffff << 0) +#define TXSTS_FSPCAVAIL_SHIFT 0 + +#define HAINT HSOTG_REG(0x0414) +#define HAINTMSK HSOTG_REG(0x0418) +#define HFLBADDR HSOTG_REG(0x041c) + +#define HPRT0 HSOTG_REG(0x0440) +#define HPRT0_SPD_MASK (0x3 << 17) +#define HPRT0_SPD_SHIFT 17 +#define HPRT0_SPD_HIGH_SPEED 0 +#define HPRT0_SPD_FULL_SPEED 1 +#define HPRT0_SPD_LOW_SPEED 2 +#define HPRT0_TSTCTL_MASK (0xf << 13) +#define HPRT0_TSTCTL_SHIFT 13 +#define HPRT0_PWR BIT(12) +#define HPRT0_LNSTS_MASK (0x3 << 10) +#define HPRT0_LNSTS_SHIFT 10 +#define HPRT0_RST BIT(8) +#define HPRT0_SUSP BIT(7) +#define HPRT0_RES BIT(6) +#define HPRT0_OVRCURRCHG BIT(5) +#define HPRT0_OVRCURRACT BIT(4) +#define HPRT0_ENACHG BIT(3) +#define HPRT0_ENA BIT(2) +#define HPRT0_CONNDET BIT(1) +#define HPRT0_CONNSTS BIT(0) + +#define HCCHAR(_ch) HSOTG_REG(0x0500 + 0x20 * (_ch)) +#define HCCHAR_CHENA BIT(31) +#define HCCHAR_CHDIS BIT(30) +#define HCCHAR_ODDFRM BIT(29) +#define HCCHAR_DEVADDR_MASK (0x7f << 22) +#define HCCHAR_DEVADDR_SHIFT 22 +#define HCCHAR_MULTICNT_MASK (0x3 << 20) +#define HCCHAR_MULTICNT_SHIFT 20 +#define HCCHAR_EPTYPE_MASK (0x3 << 18) +#define HCCHAR_EPTYPE_SHIFT 18 +#define HCCHAR_LSPDDEV BIT(17) +#define HCCHAR_EPDIR BIT(15) +#define HCCHAR_EPNUM_MASK (0xf << 11) +#define HCCHAR_EPNUM_SHIFT 11 +#define HCCHAR_MPS_MASK (0x7ff << 0) +#define HCCHAR_MPS_SHIFT 0 + +#define HCSPLT(_ch) HSOTG_REG(0x0504 + 0x20 * (_ch)) +#define HCSPLT_SPLTENA BIT(31) +#define HCSPLT_COMPSPLT BIT(16) +#define HCSPLT_XACTPOS_MASK (0x3 << 14) +#define HCSPLT_XACTPOS_SHIFT 14 +#define HCSPLT_XACTPOS_MID 0 +#define HCSPLT_XACTPOS_END 1 +#define HCSPLT_XACTPOS_BEGIN 2 +#define HCSPLT_XACTPOS_ALL 3 +#define HCSPLT_HUBADDR_MASK (0x7f << 7) +#define HCSPLT_HUBADDR_SHIFT 7 +#define HCSPLT_PRTADDR_MASK (0x7f << 0) +#define HCSPLT_PRTADDR_SHIFT 0 + +#define HCINT(_ch) HSOTG_REG(0x0508 + 0x20 * (_ch)) +#define HCINTMSK(_ch) HSOTG_REG(0x050c + 0x20 * (_ch)) +#define HCINTMSK_RESERVED14_31 (0x3ffff << 14) +#define HCINTMSK_FRM_LIST_ROLL BIT(13) +#define HCINTMSK_XCS_XACT BIT(12) +#define HCINTMSK_BNA BIT(11) +#define HCINTMSK_DATATGLERR BIT(10) +#define HCINTMSK_FRMOVRUN BIT(9) +#define HCINTMSK_BBLERR BIT(8) +#define HCINTMSK_XACTERR BIT(7) +#define HCINTMSK_NYET BIT(6) +#define HCINTMSK_ACK BIT(5) +#define HCINTMSK_NAK BIT(4) +#define HCINTMSK_STALL BIT(3) +#define HCINTMSK_AHBERR BIT(2) +#define HCINTMSK_CHHLTD BIT(1) +#define HCINTMSK_XFERCOMPL BIT(0) + +#define HCTSIZ(_ch) HSOTG_REG(0x0510 + 0x20 * (_ch)) +#define TSIZ_DOPNG BIT(31) +#define TSIZ_SC_MC_PID_MASK (0x3 << 29) +#define TSIZ_SC_MC_PID_SHIFT 29 +#define TSIZ_SC_MC_PID_DATA0 0 +#define TSIZ_SC_MC_PID_DATA2 1 +#define TSIZ_SC_MC_PID_DATA1 2 +#define TSIZ_SC_MC_PID_MDATA 3 +#define TSIZ_SC_MC_PID_SETUP 3 +#define TSIZ_PKTCNT_MASK (0x3ff << 19) +#define TSIZ_PKTCNT_SHIFT 19 +#define TSIZ_NTD_MASK (0xff << 8) +#define TSIZ_NTD_SHIFT 8 +#define TSIZ_SCHINFO_MASK (0xff << 0) +#define TSIZ_SCHINFO_SHIFT 0 +#define TSIZ_XFERSIZE_MASK (0x7ffff << 0) +#define TSIZ_XFERSIZE_SHIFT 0 + +#define HCDMA(_ch) HSOTG_REG(0x0514 + 0x20 * (_ch)) + +#define HCDMAB(_ch) HSOTG_REG(0x051c + 0x20 * (_ch)) + +#define HCFIFO(_ch) HSOTG_REG(0x1000 + 0x1000 * (_ch)) + +/** + * struct dwc2_dma_desc - DMA descriptor structure, + * used for both host and gadget modes + * + * @status: DMA descriptor status quadlet + * @buf: DMA descriptor data buffer pointer + * + * DMA Descriptor structure contains two quadlets: + * Status quadlet and Data buffer pointer. + */ +struct dwc2_dma_desc { + uint32_t status; + uint32_t buf; +} __packed; + +/* Host Mode DMA descriptor status quadlet */ + +#define HOST_DMA_A BIT(31) +#define HOST_DMA_STS_MASK (0x3 << 28) +#define HOST_DMA_STS_SHIFT 28 +#define HOST_DMA_STS_PKTERR BIT(28) +#define HOST_DMA_EOL BIT(26) +#define HOST_DMA_IOC BIT(25) +#define HOST_DMA_SUP BIT(24) +#define HOST_DMA_ALT_QTD BIT(23) +#define HOST_DMA_QTD_OFFSET_MASK (0x3f << 17) +#define HOST_DMA_QTD_OFFSET_SHIFT 17 +#define HOST_DMA_ISOC_NBYTES_MASK (0xfff << 0) +#define HOST_DMA_ISOC_NBYTES_SHIFT 0 +#define HOST_DMA_NBYTES_MASK (0x1ffff << 0) +#define HOST_DMA_NBYTES_SHIFT 0 +#define HOST_DMA_NBYTES_LIMIT 131071 + +/* Device Mode DMA descriptor status quadlet */ + +#define DEV_DMA_BUFF_STS_MASK (0x3 << 30) +#define DEV_DMA_BUFF_STS_SHIFT 30 +#define DEV_DMA_BUFF_STS_HREADY 0 +#define DEV_DMA_BUFF_STS_DMABUSY 1 +#define DEV_DMA_BUFF_STS_DMADONE 2 +#define DEV_DMA_BUFF_STS_HBUSY 3 +#define DEV_DMA_STS_MASK (0x3 << 28) +#define DEV_DMA_STS_SHIFT 28 +#define DEV_DMA_STS_SUCC 0 +#define DEV_DMA_STS_BUFF_FLUSH 1 +#define DEV_DMA_STS_BUFF_ERR 3 +#define DEV_DMA_L BIT(27) +#define DEV_DMA_SHORT BIT(26) +#define DEV_DMA_IOC BIT(25) +#define DEV_DMA_SR BIT(24) +#define DEV_DMA_MTRF BIT(23) +#define DEV_DMA_ISOC_PID_MASK (0x3 << 23) +#define DEV_DMA_ISOC_PID_SHIFT 23 +#define DEV_DMA_ISOC_PID_DATA0 0 +#define DEV_DMA_ISOC_PID_DATA2 1 +#define DEV_DMA_ISOC_PID_DATA1 2 +#define DEV_DMA_ISOC_PID_MDATA 3 +#define DEV_DMA_ISOC_FRNUM_MASK (0x7ff << 12) +#define DEV_DMA_ISOC_FRNUM_SHIFT 12 +#define DEV_DMA_ISOC_TX_NBYTES_MASK (0xfff << 0) +#define DEV_DMA_ISOC_TX_NBYTES_LIMIT 0xfff +#define DEV_DMA_ISOC_RX_NBYTES_MASK (0x7ff << 0) +#define DEV_DMA_ISOC_RX_NBYTES_LIMIT 0x7ff +#define DEV_DMA_ISOC_NBYTES_SHIFT 0 +#define DEV_DMA_NBYTES_MASK (0xffff << 0) +#define DEV_DMA_NBYTES_SHIFT 0 +#define DEV_DMA_NBYTES_LIMIT 0xffff + +#define MAX_DMA_DESC_NUM_GENERIC 64 +#define MAX_DMA_DESC_NUM_HS_ISOC 256 + +#endif /* __DWC2_HW_H__ */ --=20 2.17.1 From nobody Fri May 3 21:45:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org 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SzgMfqp1bmPQgAJmsUvDFBo= X-Google-Smtp-Source: ADFU+vuUJJ/smFU+T4fto9PT3C8dv6Cn6iXbTstUcHQ5CaoTBYhr4psElpF7SFtCCzk68H+BR/U6XA== X-Received: by 2002:a62:3487:: with SMTP id b129mr21314547pfa.150.1584916124050; Sun, 22 Mar 2020 15:28:44 -0700 (PDT) From: Paul Zimmerman To: kraxel@redhat.com Subject: [PATCH 3/6] dwc-hsotg USB host controller state definitions Date: Sun, 22 Mar 2020 15:27:23 -0700 Message-Id: <20200322222726.10244-4-pauldzim@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200322222726.10244-1-pauldzim@gmail.com> References: <20200322222726.10244-1-pauldzim@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, stefanha@gmail.com, qemu-devel@nongnu.org, Paul Zimmerman , jsnow@redhat.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add the dwc-hsotg (dwc2) USB host controller state definitions. Mostly based on hw/usb/hcd-ehci.h. Signed-off-by: Paul Zimmerman --- hw/usb/hcd-dwc2.h | 180 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 180 insertions(+) create mode 100644 hw/usb/hcd-dwc2.h diff --git a/hw/usb/hcd-dwc2.h b/hw/usb/hcd-dwc2.h new file mode 100644 index 0000000000..c5f5037b91 --- /dev/null +++ b/hw/usb/hcd-dwc2.h @@ -0,0 +1,180 @@ +/* + * dwc-hsotg (dwc2) USB host controller state definitions + * + * Based on hw/usb/hcd-ehci.h + * + * Copyright (c) 2020 Paul Zimmerman + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef HW_USB_DWC2_H +#define HW_USB_DWC2_H + +#include "qemu/timer.h" +#include "hw/irq.h" +#include "hw/sysbus.h" +#include "hw/usb.h" +#include "sysemu/dma.h" + +#define DWC2_MMIO_SIZE 0x11000 + +#define NB_PORTS 1 /* Number of downstream ports */ +#define NB_CHAN 8 /* Number of host channels */ +#define MAX_XFER_SIZE 65536 /* Max transfer size expected in HCTSIZ */ + +typedef struct DWC2Packet DWC2Packet; +typedef struct DWC2State DWC2State; + +enum async_state { + DWC2_ASYNC_NONE =3D 0, + DWC2_ASYNC_INITIALIZED, + DWC2_ASYNC_INFLIGHT, + DWC2_ASYNC_FINISHED, +}; + +struct DWC2Packet { + USBPacket packet; + USBDevice *dev; + USBEndpoint *ep; + uint32_t index; + uint32_t epnum; + uint32_t mps; + uint32_t pid; + uint32_t pcnt; + uint32_t len; + bool small; + bool needs_service; + enum async_state async; +}; + +struct DWC2State { + SysBusDevice parent_obj; + USBBus bus; + DeviceState *device; + qemu_irq irq; + MemoryRegion *dma_mr; + AddressSpace *as; + AddressSpace dma_as; + MemoryRegion mem; + MemoryRegion mem_glbreg; + MemoryRegion mem_fszreg; + MemoryRegion mem_hreg0; + MemoryRegion mem_hreg1; + MemoryRegion mem_pcgreg; + MemoryRegion mem_hreg2; + uint16_t glbregbase; + uint16_t fszregbase; + uint16_t hreg0base; + uint16_t hreg1base; + uint16_t pcgregbase; + uint16_t hreg2base; + uint16_t portnr; + + union { + uint32_t glbreg[0x70/sizeof(uint32_t)]; + struct { + uint32_t gotgctl; /* 00 */ + uint32_t gotgint; /* 04 */ + uint32_t gahbcfg; /* 08 */ + uint32_t gusbcfg; /* 0c */ + uint32_t grstctl; /* 10 */ + uint32_t gintsts; /* 14 */ + uint32_t gintmsk; /* 18 */ + uint32_t grxstsr; /* 1c */ + uint32_t grxstsp; /* 20 */ + uint32_t grxfsiz; /* 24 */ + uint32_t gnptxfsiz; /* 28 */ + uint32_t gnptxsts; /* 2c */ + uint32_t gi2cctl; /* 30 */ + uint32_t gpvndctl; /* 34 */ + uint32_t ggpio; /* 38 */ + uint32_t guid; /* 3c */ + uint32_t gsnpsid; /* 40 */ + uint32_t ghwcfg1; /* 44 */ + uint32_t ghwcfg2; /* 48 */ + uint32_t ghwcfg3; /* 4c */ + uint32_t ghwcfg4; /* 50 */ + uint32_t glpmcfg; /* 54 */ + uint32_t gpwrdn; /* 58 */ + uint32_t gdfifocfg; /* 5c */ + uint32_t gadpctl; /* 60 */ + uint32_t grefclk; /* 64 */ + uint32_t gintmsk2; /* 68 */ + uint32_t gintsts2; /* 6c */ + }; + }; + + union { + uint32_t fszreg[0x4/sizeof(uint32_t)]; + struct { + uint32_t hptxfsiz; /* 100 */ + }; + }; + + union { + uint32_t hreg0[0x44/sizeof(uint32_t)]; + struct { + uint32_t hcfg; /* 400 */ + uint32_t hfir; /* 404 */ + uint32_t hfnum; /* 408 */ + uint32_t rsvd0; /* 40c */ + uint32_t hptxsts; /* 410 */ + uint32_t haint; /* 414 */ + uint32_t haintmsk; /* 418 */ + uint32_t hflbaddr; /* 41c */ + uint32_t rsvd1[8]; /* 420-43c */ + uint32_t hprt0; /* 440 */ + }; + }; + + uint32_t hreg1[0x20*NB_CHAN/sizeof(uint32_t)]; +#define hcchar(_ch) hreg1[((_ch) << 3) + 0] /* 500, 520, ... */ +#define hcsplt(_ch) hreg1[((_ch) << 3) + 1] /* 504, 524, ... */ +#define hcint(_ch) hreg1[((_ch) << 3) + 2] /* 508, 528, ... */ +#define hcintmsk(_ch) hreg1[((_ch) << 3) + 3] /* 50c, 52c, ... */ +#define hctsiz(_ch) hreg1[((_ch) << 3) + 4] /* 510, 530, ... */ +#define hcdma(_ch) hreg1[((_ch) << 3) + 5] /* 514, 534, ... */ +#define hcdmab(_ch) hreg1[((_ch) << 3) + 7] /* 51c, 53c, ... */ + + union { + uint32_t pcgreg[0x8/sizeof(uint32_t)]; + struct { + uint32_t pcgctl; /* e00 */ + uint32_t pcgcctl1; /* e04 */ + }; + }; + + /* TODO - implement FIFO registers for slave mode */ + + /* + * Internal state + */ + QEMUTimer *eof_timer; + QEMUTimer *frame_timer; + QEMUBH *async_bh; + int64_t sof_time; + int64_t usb_frame_time; + int64_t usb_bit_time; + uint16_t frame_number; + uint16_t fsmps; + uint16_t fi; + uint16_t next_chan; + bool working; + USBPort ports[NB_PORTS]; + DWC2Packet packet[NB_CHAN]; /* one packet per channel = */ + uint8_t usb_buf[NB_CHAN][MAX_XFER_SIZE]; /* one buffer per channel = */ +}; + +#define TYPE_DWC2_USB "dwc2-usb" +#define DWC2_USB(obj) OBJECT_CHECK(DWC2State, (obj), TYPE_DWC2_USB) + +#endif --=20 2.17.1 From nobody Fri May 3 21:45:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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X-Received-From: 2607:f8b0:4864:20::443 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, stefanha@gmail.com, qemu-devel@nongnu.org, Paul Zimmerman , jsnow@redhat.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Add the dwc-hsotg (dwc2) USB host controller emulation code. Based on hw/usb/hcd-ehci.c and hw/usb/hcd-ohci.c. Note that to use this with the dwc-otg driver in the Raspbian kernel, you must pass the option "dwc_otg.fiq_fsm_enable=3D0" on the kernel command line. I have used some on-line sources of information while developing this emulation, including: http://www.capital-micro.com/PDF/CME-M7_Family_User_Guide_EN.pdf has a pretty complete description of the controller starting on page 370. https://sourceforge.net/p/wive-ng/wive-ng-mt/ci/master/tree/docs/DataSheets= /RT3050_5x_V2.0_081408_0902.pdf has a description of the controller registers starting on page 130. Signed-off-by: Paul Zimmerman --- hw/usb/hcd-dwc2.c | 1353 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 1353 insertions(+) create mode 100644 hw/usb/hcd-dwc2.c diff --git a/hw/usb/hcd-dwc2.c b/hw/usb/hcd-dwc2.c new file mode 100644 index 0000000000..fd33190611 --- /dev/null +++ b/hw/usb/hcd-dwc2.c @@ -0,0 +1,1353 @@ +/* + * dwc-hsotg (dwc2) USB host controller emulation + * + * Based on hw/usb/hcd-ehci.c and hw/usb/hcd-ohci.c + * + * Copyright (c) 2020 Paul Zimmerman + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "hw/usb/dwc2-regs.h" +#include "hw/usb/hcd-dwc2.h" +#include "qemu/error-report.h" +#include "qemu/main-loop.h" + +//#define DWC2_DEBUG 1 + +#ifdef DWC2_DEBUG +#define DPRINTF(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__) +#else +#define DPRINTF(fmt, ...) do {} while(0) +#endif + +#define DWC2_DO_SOFS 1 + +#define USB_HZ_FS 12000000 +#define USB_HZ_HS 96000000 + +/* nifty macros from Arnon's EHCI version */ +#define get_field(data, field) \ + (((data) & field##_MASK) >> field##_SHIFT) + +#define set_field(data, newval, field) do { \ + uint32_t val =3D *data; \ + val &=3D ~ field##_MASK; \ + val |=3D ((newval) << field##_SHIFT) & field##_MASK; \ + *data =3D val; \ +} while (0) + +#define get_bit(data, bitmask) \ + (!!((data) & bitmask)) + +/* update irq line */ +static inline void dwc2_update_irq(DWC2State *s) +{ + static int oldlevel; + int level =3D 0; + + if ((s->gintsts & s->gintmsk) && (s->gahbcfg & GAHBCFG_GLBL_INTR_EN)) + level =3D 1; + if (level !=3D oldlevel) { + /*DPRINTF("dwc2_update_irq, sts 0x%08x msk 0x%08x level %d\n", + s->gintsts, s->gintmsk, level);*/ + oldlevel =3D level; + qemu_set_irq(s->irq, level); + } +} + +/* flag interrupt condition */ +static inline void dwc2_raise_global_irq(DWC2State *s, uint32_t intr) +{ + /*DPRINTF("dwc2_raise_global_irq, 0x%08x\n", intr);*/ + s->gintsts |=3D intr; + dwc2_update_irq(s); +} + +static inline void dwc2_lower_global_irq(DWC2State *s, uint32_t intr) +{ + /*DPRINTF("dwc2_lower_global_irq, 0x%08x\n", intr);*/ + s->gintsts &=3D ~intr; + dwc2_update_irq(s); +} + +static inline void dwc2_raise_host_irq(DWC2State *s, uint32_t intr) +{ + /*DPRINTF("dwc2_raise_host_irq, 0x%04x\n", intr);*/ + s->haint |=3D intr; + s->haint &=3D 0xffff; + if (s->haint & s->haintmsk) { + dwc2_raise_global_irq(s, GINTSTS_HCHINT); + } +} + +static inline void dwc2_lower_host_irq(DWC2State *s, uint32_t intr) +{ + /*DPRINTF("dwc2_lower_host_irq, 0x%04x\n", intr);*/ + s->haint &=3D ~intr; + if (!(s->haint & s->haintmsk)) { + dwc2_lower_global_irq(s, GINTSTS_HCHINT); + } +} + +static inline void dwc2_update_hc_irq(DWC2State *s, int index) +{ + uint32_t intr =3D 1 << (index >> 3); + + /*DPRINTF("dwc2_update_hc_irq, hcint%d 0x%04x hcintmsk%d 0x%04x\n", + index >> 3, s->hreg1[index + 2], index >> 3, s->hreg1[index + = 3]);*/ + if (s->hreg1[index + 2] & s->hreg1[index + 3]) { + dwc2_raise_host_irq(s, intr); + } else { + dwc2_lower_host_irq(s, intr); + } +} + +/* set a timer for EOF */ +static void dwc2_eof_timer(DWC2State *s) +{ +#ifdef DWC2_DO_SOFS + timer_mod(s->eof_timer, s->sof_time + s->usb_frame_time); +#endif +} + +#ifdef DWC2_DO_SOFS +/* Set a timer for EOF and generate a SOF event */ +static void dwc2_sof(DWC2State *s) +{ + s->sof_time +=3D s->usb_frame_time; + dwc2_eof_timer(s); + dwc2_raise_global_irq(s, GINTSTS_SOF); +} + +/* Do frame processing on frame boundary */ +static void dwc2_frame_boundary(void *opaque) +{ + DWC2State *s =3D opaque; + + /* Frame boundary, so do EOF stuff here */ + + /* Increment frame number */ + s->frame_number =3D (s->frame_number + 1) & 0xffff; + s->hfnum =3D (s->hfnum & ~HFNUM_FRNUM_MASK) | + (s->frame_number & HFNUM_MAX_FRNUM); + + /* Do SOF stuff here */ + dwc2_sof(s); +} +#endif + +/* Start sending SOF tokens across the USB bus, lists are processed in + * next frame + */ +static int dwc2_bus_start(DWC2State *s) +{ + /* Delay the first SOF event by one frame time as + * linux driver is not ready to receive it and + * can meet some race conditions + */ + + s->sof_time =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + dwc2_eof_timer(s); + + return 1; +} + +/* Stop sending SOF tokens on the bus */ +static void dwc2_bus_stop(DWC2State *s) +{ +#ifdef DWC2_DO_SOFS + timer_del(s->eof_timer); +#endif +} + +static USBDevice *dwc2_find_device(DWC2State *s, uint8_t addr) +{ + USBDevice *dev; + USBPort *port; + int i; + + DPRINTF("dwc2_find_device\n"); + for (i =3D 0; i < NB_PORTS; i++) { + port =3D &s->ports[i]; + if (!(s->hprt0 & HPRT0_ENA)) { + DPRINTF("Port %d not enabled\n", i); + continue; + } + dev =3D usb_find_device(port, addr); + if (dev !=3D NULL) { + DPRINTF("found device\n"); + return dev; + } + } + DPRINTF("device NOT found\n"); + return NULL; +} + +static const char *pstatus[] =3D { + "USB_RET_SUCCESS", "USB_RET_NODEV", "USB_RET_NAK", "USB_RET_STALL", + "USB_RET_BABBLE", "USB_RET_IOERROR", "USB_RET_ASYNC", + "USB_RET_ADD_TO_QUEUE", "USB_RET_REMOVE_FROM_QUEUE" +}; + +static uint32_t pintr[] =3D { + HCINTMSK_XFERCOMPL, HCINTMSK_XACTERR, HCINTMSK_NAK, HCINTMSK_STALL, + HCINTMSK_BBLERR, HCINTMSK_XACTERR, HCINTMSK_XACTERR, HCINTMSK_XACTERR, + HCINTMSK_XACTERR +}; + +#ifdef DWC2_DEBUG +static const char *types[] =3D { + "Ctrl", "Isoc", "Bulk", "Intr" +}; + +static const char *dirs[] =3D { + "Out", "In" +}; +#endif + +static void dwc2_handle_packet(DWC2State *s, USBDevice *dev, USBEndpoint *= ep, + uint32_t index, bool send) { + DWC2Packet *p; + uint32_t hcchar =3D s->hreg1[index]; + uint32_t hctsiz =3D s->hreg1[index + 4]; + uint32_t hcdma =3D s->hreg1[index + 5]; + uint32_t chan, epnum, epdir, eptype, mps, pid, pcnt, len, tlen, intr = =3D 0; + uint32_t tpcnt, stsidx, actual =3D 0; + int i; + bool done =3D false; + + epnum =3D get_field(hcchar, HCCHAR_EPNUM); + epdir =3D get_bit(hcchar, HCCHAR_EPDIR); + eptype =3D get_field(hcchar, HCCHAR_EPTYPE); + mps =3D get_field(hcchar, HCCHAR_MPS); + pid =3D get_field(hctsiz, TSIZ_SC_MC_PID); + pcnt =3D get_field(hctsiz, TSIZ_PKTCNT); + len =3D get_field(hctsiz, TSIZ_XFERSIZE); + assert(len <=3D MAX_XFER_SIZE); + chan =3D index >> 3; + p =3D &s->packet[chan]; + + DPRINTF("dwc2_handle_packet," + " ch %d dev %p pkt %p ep %d type %s dir %s mps %d len %d pcnt = %d\n", + chan, dev, &p->packet, epnum, types[eptype], dirs[epdir], mps,= len, + pcnt); + + if (eptype =3D=3D USB_ENDPOINT_XFER_CONTROL && pid =3D=3D TSIZ_SC_MC_P= ID_SETUP) { + pid =3D USB_TOKEN_SETUP; + } else { + pid =3D epdir ? USB_TOKEN_IN : USB_TOKEN_OUT; + } + + tlen =3D len; + if (p->small) { + if (tlen > mps) { + tlen =3D mps; + } + } + + if (send) { + if (pid !=3D USB_TOKEN_IN) { + DPRINTF("calling dma_memory_read, len %u\n", tlen); + if (dma_memory_read(&s->dma_as, hcdma, + s->usb_buf[chan], tlen) !=3D MEMTX_OK) { + fprintf(stderr, "dma_memory_read failed\n"); + } + if (tlen > 0) { + for (i =3D 0; i < 8; i++) + DPRINTF(" %02x", s->usb_buf[chan][i]); + DPRINTF("\n"); + } + } + + usb_packet_init(&p->packet); + usb_packet_setup(&p->packet, pid, ep, 0, hcdma, + pid !=3D USB_TOKEN_IN, true); + usb_packet_addbuf(&p->packet, s->usb_buf[chan], tlen); + p->async =3D DWC2_ASYNC_NONE; + usb_handle_packet(dev, &p->packet); + } + + stsidx =3D -p->packet.status; + assert(stsidx < sizeof(pstatus) / sizeof(*pstatus)); + DPRINTF("packet status %s len %d\n", pstatus[stsidx], + p->packet.actual_length); + if (p->packet.status !=3D USB_RET_SUCCESS && + p->packet.status !=3D USB_RET_NAK && + p->packet.status !=3D USB_RET_STALL) { + fprintf(stderr, "dwc2_handle_packet: packet status %s\n", + pstatus[stsidx]); + } + + if (p->packet.status =3D=3D USB_RET_ASYNC) { + usb_device_flush_ep_queue(dev, ep); + assert(p->async !=3D DWC2_ASYNC_INFLIGHT); + p->dev =3D dev; + p->ep =3D ep; + p->index =3D index; + p->epnum =3D epnum; + p->mps =3D mps; + p->pid =3D pid; + p->pcnt =3D pcnt; + p->len =3D tlen; + p->needs_service =3D false; + p->async =3D DWC2_ASYNC_INFLIGHT; + return; + } + + if (p->packet.status =3D=3D USB_RET_SUCCESS) { + actual =3D p->packet.actual_length; + if (pid =3D=3D USB_TOKEN_IN) { + DPRINTF("calling dma_memory_write, len %u\n", actual); + if (dma_memory_write(&s->dma_as, hcdma, s->usb_buf[chan], + actual) !=3D MEMTX_OK) { + fprintf(stderr, "dma_memory_write failed\n"); + } + if (actual > 0) { + for (i =3D 0; i < 8; i++) + DPRINTF(" %02x", s->usb_buf[chan][i]); + DPRINTF("\n"); + } + } + + tpcnt =3D actual / mps; + if (actual % mps) { + tpcnt++; + if (pid =3D=3D USB_TOKEN_IN) + done =3D true; + } + + pcnt -=3D tpcnt < pcnt ? tpcnt : pcnt; + set_field(&hctsiz, pcnt, TSIZ_PKTCNT); + len -=3D actual < len ? actual : len; + set_field(&hctsiz, len, TSIZ_XFERSIZE); + s->hreg1[index + 4] =3D hctsiz; + + hcdma +=3D actual; + s->hreg1[index + 5] =3D hcdma; + + if (!pcnt || len =3D=3D 0 || actual =3D=3D 0) { + done =3D true; + } + } else { + intr |=3D pintr[stsidx]; + if (p->packet.status =3D=3D USB_RET_NAK && + (eptype =3D=3D USB_ENDPOINT_XFER_CONTROL || + eptype =3D=3D USB_ENDPOINT_XFER_BULK)) { + /* for ctrl/bulk, automatically retry on NAK, + but send the interrupt anyway */ + intr &=3D ~HCINTMSK_RESERVED14_31; + s->hreg1[index + 2] |=3D intr; + } else { + intr |=3D HCINTMSK_CHHLTD; + done =3D true; + } + } + + usb_packet_cleanup(&p->packet); + + if (done) { + hcchar &=3D ~HCCHAR_CHENA; + s->hreg1[index] =3D hcchar; + if (!(intr & HCINTMSK_CHHLTD)) { + intr |=3D HCINTMSK_CHHLTD | HCINTMSK_XFERCOMPL; + } + intr &=3D ~HCINTMSK_RESERVED14_31; + s->hreg1[index + 2] |=3D intr; + p->needs_service =3D false; + DPRINTF("done %s len %d actual %d pcnt %d\n", pstatus[stsidx], len= , actual, pcnt); + dwc2_update_hc_irq(s, index); + return; + } + + p->dev =3D dev; + p->ep =3D ep; + p->index =3D index; + p->epnum =3D epnum; + p->mps =3D mps; + p->pid =3D pid; + p->pcnt =3D pcnt; + p->len =3D tlen; + p->needs_service =3D true; + DPRINTF("cont %s len %d actual %d pcnt %d\n", pstatus[stsidx], len, ac= tual, pcnt); +} + +/* Attach or detach a device on root hub */ + +static void dwc2_attach(USBPort *port) +{ + DWC2State *s =3D port->opaque; + int hispd =3D 0; + + DPRINTF("dwc2_attach, port %p\n", port); + assert(port->index < NB_PORTS); + + if (!port->dev || !port->dev->attached) + return; + + s->hprt0 &=3D ~HPRT0_SPD_MASK; + + switch (port->dev->speed) { + case USB_SPEED_LOW: + DPRINTF("low-speed device attached\n"); + s->hprt0 |=3D HPRT0_SPD_LOW_SPEED << HPRT0_SPD_SHIFT; + break; + case USB_SPEED_FULL: + DPRINTF("full-speed device attached\n"); + s->hprt0 |=3D HPRT0_SPD_FULL_SPEED << HPRT0_SPD_SHIFT; + break; + case USB_SPEED_HIGH: + DPRINTF("high-speed device attached\n"); + s->hprt0 |=3D HPRT0_SPD_HIGH_SPEED << HPRT0_SPD_SHIFT; + hispd =3D 1; + break; + } + + if (hispd) { + s->usb_frame_time =3D NANOSECONDS_PER_SECOND / 8000; /* 125= 000 */ + if (NANOSECONDS_PER_SECOND >=3D USB_HZ_HS) { + s->usb_bit_time =3D NANOSECONDS_PER_SECOND / USB_HZ_HS; /* 10.= 4 */ + } else { + s->usb_bit_time =3D 1; + } + } else { + s->usb_frame_time =3D NANOSECONDS_PER_SECOND / 1000; /* 100= 0000 */ + if (NANOSECONDS_PER_SECOND >=3D USB_HZ_FS) { + s->usb_bit_time =3D NANOSECONDS_PER_SECOND / USB_HZ_FS; /* 83.= 3 */ + } else { + s->usb_bit_time =3D 1; + } + } + + s->fi =3D 11999; + s->hprt0 |=3D HPRT0_CONNDET | HPRT0_CONNSTS; + + dwc2_bus_start(s); + dwc2_raise_global_irq(s, GINTSTS_PRTINT); +} + +static void dwc2_detach(USBPort *port) +{ + DWC2State *s =3D port->opaque; + + DPRINTF("dwc2_detach, port %p\n", port); + assert(port->index < NB_PORTS); + + dwc2_bus_stop(s); + + s->hprt0 &=3D ~(HPRT0_SPD_MASK | HPRT0_SUSP | HPRT0_ENA | HPRT0_CONNST= S); + s->hprt0 |=3D HPRT0_CONNDET | HPRT0_ENACHG; + + dwc2_raise_global_irq(s, GINTSTS_PRTINT); +} + +static void dwc2_child_detach(USBPort *port, USBDevice *child) +{ + DPRINTF("dwc2_child_detach, port %p child %p\n", port, child); + assert(port->index < NB_PORTS); +} + +static void dwc2_wakeup(USBPort *port) +{ + DWC2State *s =3D port->opaque; + + DPRINTF("dwc2_wakeup, port %p\n", port); + assert(port->index < NB_PORTS); + + if (s->hprt0 & HPRT0_SUSP) { + s->hprt0 |=3D HPRT0_RES; + dwc2_raise_global_irq(s, GINTSTS_PRTINT); + } + + qemu_bh_schedule(s->async_bh); +} + +static void dwc2_async_complete_packet(USBPort *port, USBPacket *packet) +{ + DWC2State *s =3D port->opaque; + DWC2Packet *p; + + DPRINTF("dwc2_async_complete_packet, port %p packet %p\n", port, packe= t); + assert(port->index < NB_PORTS); + + p =3D container_of(packet, DWC2Packet, packet); + DPRINTF("ch %d dev %p epnum %d\n", p->index >> 3, p->dev, p->epnum); + assert(p->async =3D=3D DWC2_ASYNC_INFLIGHT); + + if (packet->status =3D=3D USB_RET_REMOVE_FROM_QUEUE) { + usb_packet_cleanup(packet); + return; + } + + dwc2_handle_packet(s, p->dev, p->ep, p->index, false); + + p->async =3D DWC2_ASYNC_FINISHED; + qemu_bh_schedule(s->async_bh); +} + +static USBPortOps dwc2_port_ops =3D { + .attach =3D dwc2_attach, + .detach =3D dwc2_detach, + .child_detach =3D dwc2_child_detach, + .wakeup =3D dwc2_wakeup, + .complete =3D dwc2_async_complete_packet, +}; + +static uint32_t dwc2_get_frame_remaining(DWC2State *s) +{ + uint32_t fr =3D 0; + int64_t tks; + + tks =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - s->sof_time; + if (tks < 0) { + tks =3D 0; + } + + /* avoid muldiv if possible */ + if (tks >=3D s->usb_frame_time || tks < s->usb_bit_time) { + goto out; + } + + /* tks =3D number of ns since SOF, divided by 83 (fs) or 10 (hs) */ + tks =3D tks / s->usb_bit_time; + if (tks >=3D (int64_t)s->fi) { + goto out; + } + + /* remaining =3D frame interval minus tks */ + fr =3D (uint32_t)((int64_t)s->fi - tks); + +out: + return fr; +} + +static void dwc2_work_bh(void *opaque) +{ + DWC2State *s =3D opaque; + DWC2Packet *p; + int64_t t_now, expire_time; + int chan; + bool done =3D false, need_timer =3D false; + + DPRINTF("dwc2_work_bh\n"); + if (s->working) { + return; + } + s->working =3D true; + + t_now =3D qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + chan =3D s->next_chan; + + while (true) { + p =3D &s->packet[chan]; + if (p->needs_service) { + DPRINTF("start %d servicing ch %d dev %p epnum %d\n", + s->next_chan, chan, p->dev, p->epnum); + dwc2_handle_packet(s, p->dev, p->ep, p->index, true); + need_timer =3D true; + done =3D true; + } + if (++chan =3D=3D NB_CHAN) { + chan =3D 0; + } + if (done) { + s->next_chan =3D chan; + DPRINTF("next %d\n", chan); + break; + } + if (chan =3D=3D s->next_chan) { + break; + } + } + + if (need_timer) { + expire_time =3D t_now + NANOSECONDS_PER_SECOND / 4000; + timer_mod(s->frame_timer, expire_time); + } + s->working =3D false; +} + +static void dwc2_enable_chan(DWC2State *s, uint32_t index) +{ + USBDevice *dev; + USBEndpoint *ep; + uint32_t hcchar; + uint32_t hctsiz; + uint32_t devadr, epnum, epdir, eptype, pid, len; + DWC2Packet *p; + + assert((index >> 3) < NB_CHAN); + p =3D &s->packet[index >> 3]; + hcchar =3D s->hreg1[index]; + hctsiz =3D s->hreg1[index + 4]; + devadr =3D get_field(hcchar, HCCHAR_DEVADDR); + epnum =3D get_field(hcchar, HCCHAR_EPNUM); + epdir =3D get_bit(hcchar, HCCHAR_EPDIR); + eptype =3D get_field(hcchar, HCCHAR_EPTYPE); + pid =3D get_field(hctsiz, TSIZ_SC_MC_PID); + len =3D get_field(hctsiz, TSIZ_XFERSIZE); + + dev =3D dwc2_find_device(s, devadr); + + DPRINTF("dwc2_enable_chan, ch %d dev %p pkt %p epnum %d\n", + index >> 3, dev, &p->packet, epnum); + if (dev =3D=3D NULL) { + fprintf(stderr, "no device found\n"); + return; + } + + if (eptype =3D=3D USB_ENDPOINT_XFER_CONTROL && pid =3D=3D TSIZ_SC_MC_P= ID_SETUP) { + pid =3D USB_TOKEN_SETUP; + } else { + pid =3D epdir ? USB_TOKEN_IN : USB_TOKEN_OUT; + } + + ep =3D usb_ep_get(dev, pid, epnum); + + /* Hack: Networking doesn't like us delivering large transfers, it kind + * of works but the latency is horrible. So if the tansfer is <=3D the= mtu + * size, we take that as a hint that this might be a network transfer, + * and do the transfer packet-by-packet. + */ + if (len > 1536) { + p->small =3D false; + } else { + p->small =3D true; + } + + dwc2_handle_packet(s, dev, ep, index, true); + qemu_bh_schedule(s->async_bh); +} + +#ifdef DWC2_DEBUG +static const char *glbregnm[] =3D { + "GOTGCTL ", "GOTGINT ", "GAHBCFG ", "GUSBCFG ", "GRSTCTL ", "GINT= STS ", + "GINTMSK ", "GRXSTSR ", "GRXSTSP ", "GRXFSIZ ", "GNPTXFSIZ", "GNPT= XSTS ", + "GI2CCTL ", "GPVNDCTL ", "GGPIO ", "GUID ", "GSNPSID ", "GHWC= FG1 ", + "GHWCFG2 ", "GHWCFG3 ", "GHWCFG4 ", "GLPMCFG ", "GPWRDN ", "GDFI= FOCFG", + "GADPCTL ", "GREFCLK ", "GINTMSK2 ", "GINTSTS2 " +}; +#endif + +static uint64_t dwc2_glbreg_read(void *ptr, hwaddr addr, unsigned size) +{ + DWC2State *s =3D ptr; + uint32_t reg =3D s->glbregbase + addr; + uint32_t val; + + assert(reg <=3D GINTSTS2); + val =3D s->glbreg[addr >> 2]; + + switch (reg) { + case GRSTCTL: + /* clear any self-clearing bits that were set */ + val &=3D ~(GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH | GRSTCTL_IN_TKNQ_FLS= H | + GRSTCTL_FRMCNTRRST | GRSTCTL_HSFTRST | GRSTCTL_CSFTRST); + s->glbreg[addr >> 2] =3D val; + break; + default: + break; + } + + if (reg !=3D GAHBCFG && reg !=3D GINTSTS && reg !=3D GINTMSK && reg != =3D GSNPSID) { + DPRINTF("dwc2_glbreg_read 0x%04lx %s val 0x%08x\n", + addr, glbregnm[addr >> 2], val); + } + + return val; +} + +static void dwc2_glbreg_write(void *ptr, hwaddr addr, uint64_t val, + unsigned size) +{ + DWC2State *s =3D ptr; + uint32_t reg =3D s->glbregbase + addr; + uint32_t *mmio; + uint32_t old; + int iflg =3D 0; + + assert(reg <=3D GINTSTS2); + mmio =3D &s->glbreg[addr >> 2]; + old =3D *mmio; + + if (reg !=3D GINTSTS && reg !=3D GINTMSK) { + DPRINTF("dwc2_glbreg_write 0x%04lx %s val 0x%08lx old 0x%08x ", + addr, glbregnm[addr >> 2], val, old); + } + + switch (reg) { + case GOTGCTL: + /* don't allow setting of read-only bits */ + val &=3D ~(GOTGCTL_MULT_VALID_BC_MASK | GOTGCTL_BSESVLD | + GOTGCTL_ASESVLD | GOTGCTL_DBNC_SHORT | GOTGCTL_CONID_B | + GOTGCTL_HSTNEGSCS | GOTGCTL_SESREQSCS); + /* don't allow clearing of read-only bits */ + val |=3D old & (GOTGCTL_MULT_VALID_BC_MASK | GOTGCTL_BSESVLD | + GOTGCTL_ASESVLD | GOTGCTL_DBNC_SHORT | GOTGCTL_CONID= _B | + GOTGCTL_HSTNEGSCS | GOTGCTL_SESREQSCS); + break; + case GAHBCFG: + if ((val & GAHBCFG_GLBL_INTR_EN) && !(old & GAHBCFG_GLBL_INTR_EN))= { + iflg =3D 1; + } + break; + case GRSTCTL: + val |=3D GRSTCTL_AHBIDLE; + val &=3D ~GRSTCTL_DMAREQ; + if (!(old & GRSTCTL_TXFFLSH) && (val & GRSTCTL_TXFFLSH)) { + /* TODO - TX fifo flush */ + } + if (!(old & GRSTCTL_RXFFLSH) && (val & GRSTCTL_RXFFLSH)) { + /* TODO - RX fifo flush */ + } + if (!(old & GRSTCTL_IN_TKNQ_FLSH) && (val & GRSTCTL_IN_TKNQ_FLSH))= { + /* TODO - device IN token queue flush */ + } + if (!(old & GRSTCTL_FRMCNTRRST) && (val & GRSTCTL_FRMCNTRRST)) { + /* TODO - host frame counter reset */ + } + if (!(old & GRSTCTL_HSFTRST) && (val & GRSTCTL_HSFTRST)) { + /* TODO - ? soft reset */ + } + if (!(old & GRSTCTL_CSFTRST) && (val & GRSTCTL_CSFTRST)) { + /* TODO - core soft reset */ + } + /* don't allow clearing of self-clearing bits */ + val |=3D old & (GRSTCTL_TXFFLSH | GRSTCTL_RXFFLSH | + GRSTCTL_IN_TKNQ_FLSH | GRSTCTL_FRMCNTRRST | + GRSTCTL_HSFTRST | GRSTCTL_CSFTRST); + break; + case GINTSTS: + /* clear the write-1-to-clear bits */ + val |=3D ~old; + val =3D ~val; + /* don't allow clearing of read-only bits */ + val |=3D old & (GINTSTS_PTXFEMP | GINTSTS_HCHINT | GINTSTS_PRTINT | + GINTSTS_OEPINT | GINTSTS_IEPINT | GINTSTS_GOUTNAKEFF= | + GINTSTS_GINNAKEFF | GINTSTS_NPTXFEMP | GINTSTS_RXFLV= L | + GINTSTS_OTGINT | GINTSTS_CURMODE_HOST); + iflg =3D 1; + break; + case GINTMSK: + iflg =3D 1; + break; + default: + break; + } + + val &=3D 0xffffffff; + if (reg !=3D GINTSTS && reg !=3D GINTMSK) { + DPRINTF("result 0x%08lx\n", val); + } + *mmio =3D val; + if (iflg) { + dwc2_update_irq(s); + } +} + +static uint64_t dwc2_fszreg_read(void *ptr, hwaddr addr, unsigned size) +{ + DWC2State *s =3D ptr; + uint32_t reg =3D s->fszregbase + addr; + uint32_t val; + + assert(reg <=3D HPTXFSIZ); + val =3D s->fszreg[addr >> 2]; + + DPRINTF("dwc2_fszreg_read 0x%04lx HPTXFSIZ val 0x%08x\n", + addr, val); + return val; +} + +static void dwc2_fszreg_write(void *ptr, hwaddr addr, uint64_t val, + unsigned size) +{ + DWC2State *s =3D ptr; + uint32_t reg =3D s->fszregbase + addr; + uint32_t *mmio; +#ifdef DWC2_DEBUG + uint32_t old; +#endif + + assert(reg <=3D HPTXFSIZ); + mmio =3D &s->fszreg[addr >> 2]; +#ifdef DWC2_DEBUG + old =3D *mmio; +#endif + + DPRINTF("dwc2_fszreg_write 0x%04lx HPTXFSIZ val 0x%08lx old 0x%08x ", + addr, val, old); + val &=3D 0xffffffff; + DPRINTF("result 0x%lx\n", val); + *mmio =3D val; +} + +#ifdef DWC2_DEBUG +static const char *hreg0nm[] =3D { + "HCFG ", "HFIR ", "HFNUM ", " ", "HPTXSTS ", "HAIN= T ", + "HAINTMSK ", "HFLBADDR ", " ", " ", " ", " ", + " ", " ", " ", " ", "HPRT0 " +}; +#endif + +static uint64_t dwc2_hreg0_read(void *ptr, hwaddr addr, unsigned size) +{ + DWC2State *s =3D ptr; + uint32_t reg =3D s->hreg0base + addr; + uint32_t val; + + assert(reg <=3D HPRT0); + val =3D s->hreg0[addr >> 2]; + + switch (reg) { + case HFNUM: + val =3D (dwc2_get_frame_remaining(s) << HFNUM_FRREM_SHIFT) | + ((s->frame_number & HFNUM_MAX_FRNUM) << HFNUM_FRNUM_SHIFT); + break; + default: + break; + } + + if (reg !=3D HFNUM) { + DPRINTF("dwc2_hreg0_read 0x%04lx %s val 0x%08x\n", + addr, hreg0nm[addr >> 2], val); + } + return val; +} + +static void dwc2_hreg0_write(void *ptr, hwaddr addr, uint64_t val, + unsigned size) +{ + DWC2State *s =3D ptr; + uint32_t reg =3D s->hreg0base + addr; + USBDevice *dev =3D s->ports[0].dev; + uint32_t *mmio; + uint32_t tval, told, old; + int prst =3D 0; + int iflg =3D 0; + + assert(reg <=3D HPRT0); + mmio =3D &s->hreg0[addr >> 2]; + old =3D *mmio; + + DPRINTF("dwc2_hreg0_write 0x%04lx %s val 0x%08lx old 0x%08x ", + addr, hreg0nm[addr >> 2], val, old); + + switch (reg) { + case HFIR: + break; + case HFNUM: + case HPTXSTS: + case HAINT: + DPRINTF("**write to read-only register**\n"); + return; + case HAINTMSK: + val &=3D 0xffff; + break; + case HPRT0: + /* don't allow clearing of read-only bits */ + val |=3D old & (HPRT0_SPD_MASK | HPRT0_LNSTS_MASK | HPRT0_OVRCURRA= CT | + HPRT0_CONNSTS); + /* don't allow clearing of self-clearing bits */ + val |=3D old & (HPRT0_SUSP | HPRT0_RES); + /* don't allow setting of self-setting bits */ + if (!(old & HPRT0_ENA) && (val & HPRT0_ENA)) { + val &=3D ~HPRT0_ENA; + } + /* clear the write-1-to-clear bits */ + tval =3D val & (HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_ENA | HPRT= 0_CONNDET); + told =3D old & (HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_ENA | HPRT= 0_CONNDET); + tval |=3D ~told; + tval =3D ~tval; + tval &=3D (HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_ENA | HPRT0_CON= NDET); + val &=3D ~(HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_ENA | HPRT0_CON= NDET); + val |=3D tval; + if (!(val & HPRT0_RST) && (old & HPRT0_RST)) { + if (dev && dev->attached) { + val |=3D HPRT0_ENA | HPRT0_ENACHG; + prst =3D 1; + } + } + if (val & (HPRT0_OVRCURRCHG | HPRT0_ENACHG | HPRT0_CONNDET)) { + iflg =3D 1; + } else { + iflg =3D -1; + } + break; + default: + break; + } + + if (prst) { + DPRINTF("call usb_port_reset\n"); + usb_port_reset(&s->ports[0]); + val &=3D ~HPRT0_CONNDET; + } + val &=3D 0xffffffff; + DPRINTF("result 0x%08lx\n", val); + *mmio =3D val; + if (iflg) { + if (iflg > 0) { + DPRINTF("enable PRTINT\n"); + dwc2_raise_global_irq(s, GINTSTS_PRTINT); + } else { + DPRINTF("disable PRTINT\n"); + dwc2_lower_global_irq(s, GINTSTS_PRTINT); + } + } +} + +#ifdef DWC2_DEBUG +static const char *hreg1nm[] =3D { + "HCCHAR ", "HCSPLT ", "HCINT ", "HCINTMSK", "HCTSIZ ", "HCDMA ", + " ", "HCDMAB " +}; +#endif + +static uint64_t dwc2_hreg1_read(void *ptr, hwaddr addr, unsigned size) +{ + DWC2State *s =3D ptr; + uint32_t reg =3D s->hreg1base + addr; + uint32_t val; + + assert(reg <=3D HCDMAB(NB_CHAN - 1)); + val =3D s->hreg1[addr >> 2]; + + DPRINTF("dwc2_hreg1_read 0x%04lx %s%ld val 0x%08x\n", + addr, hreg1nm[(addr >> 2) & 7], addr >> 5, val); + assert(s->hreg1base + (addr & 0x1c) <=3D HCDMAB(NB_CHAN)); + return val; +} + +static void dwc2_hreg1_write(void *ptr, hwaddr addr, uint64_t val, + unsigned size) +{ + DWC2State *s =3D ptr; + uint32_t reg =3D s->hreg1base + addr; + uint32_t *mmio; + uint32_t old; + int iflg =3D 0; + int enflg =3D 0; + int disflg =3D 0; + + assert(reg <=3D HCDMAB(NB_CHAN - 1)); + mmio =3D &s->hreg1[addr >> 2]; + old =3D *mmio; + + DPRINTF("dwc2_hreg1_write 0x%04lx %s%ld val 0x%08lx old 0x%08x ", + addr, hreg1nm[(addr >> 2) & 7], addr >> 5, val, old); + + switch (s->hreg1base + (addr & 0x1c)) { + case HCCHAR(0): + if ((val & HCCHAR_CHDIS) && !(old & HCCHAR_CHDIS)) { + val &=3D ~(HCCHAR_CHENA | HCCHAR_CHDIS); + disflg =3D 1; + } else { + val |=3D old & HCCHAR_CHDIS; + if ((val & HCCHAR_CHENA) && !(old & HCCHAR_CHENA)) { + val &=3D ~HCCHAR_CHDIS; + enflg =3D 1; + } else { + val |=3D old & HCCHAR_CHENA; + } + } + break; + case HCINT(0): + /* clear the write-1-to-clear bits */ + val |=3D ~old; + val =3D ~val; + val &=3D ~HCINTMSK_RESERVED14_31; + iflg =3D 1; + break; + case HCINTMSK(0): + val &=3D ~HCINTMSK_RESERVED14_31; + iflg =3D 1; + break; + case HCDMAB(0): + DPRINTF("**write to read-only register**\n"); + return; + default: + break; + } + + val &=3D 0xffffffff; + DPRINTF("result 0x%08lx\n", val); + *mmio =3D val; + if (disflg) { + /* set ChHltd in HCINT */ + s->hreg1[((addr >> 2) & ~7) + 2] |=3D HCINTMSK_CHHLTD; + iflg =3D 1; + } + if (enflg) { + dwc2_enable_chan(s, (addr >> 2) & ~7); + } + if (iflg) { + dwc2_update_hc_irq(s, (addr >> 2) & ~7); + } +} + +#ifdef DWC2_DEBUG +static const char *pcgregnm[] =3D { + "PCGCTL ", "PCGCCTL1 " +}; +#endif + +static uint64_t dwc2_pcgreg_read(void *ptr, hwaddr addr, unsigned size) +{ + DWC2State *s =3D ptr; + uint32_t reg =3D s->pcgregbase + addr; + uint32_t val; + + assert(reg <=3D PCGCCTL1); + val =3D s->pcgreg[addr >> 2]; + + DPRINTF("dwc2_pcgreg_read 0x%04lx %s val 0x%08x\n", + addr, pcgregnm[addr >> 2], val); + return val; +} + +static void dwc2_pcgreg_write(void *ptr, hwaddr addr, uint64_t val, + unsigned size) +{ + DWC2State *s =3D ptr; + uint32_t reg =3D s->pcgregbase + addr; + uint32_t *mmio; +#ifdef DWC2_DEBUG + uint32_t old; +#endif + + assert(reg <=3D PCGCCTL1); + mmio =3D &s->pcgreg[addr >> 2]; +#ifdef DWC2_DEBUG + old =3D *mmio; +#endif + + DPRINTF("dwc2_pcgreg_write 0x%04lx %s val 0x%08lx old 0x%08x ", + addr, pcgregnm[addr >> 2], val, old); + val &=3D 0xffffffff; + DPRINTF("result 0x%08lx\n", val); + *mmio =3D val; +} + +static uint64_t dwc2_hreg2_read(void *ptr, hwaddr addr, unsigned size) +{ + /* TODO - implement FIFOs to support slave mode */ + DPRINTF("dwc2_hreg2_read 0x%04lx FIFO%ld val 0x%08x\n", + addr, addr >> 12, 0); + return 0; +} + +static void dwc2_hreg2_write(void *ptr, hwaddr addr, uint64_t val, + unsigned size) +{ + /* TODO - implement FIFOs to support slave mode */ + DPRINTF("dwc2_hreg2_write 0x%04lx FIFO%ld val 0x%08lx ", + addr, addr >> 12, val); + val &=3D 0xffffffff; + DPRINTF("result 0x%08lx\n", val); +} + +static const MemoryRegionOps dwc2_mmio_glbreg_ops =3D { + .read =3D dwc2_glbreg_read, + .write =3D dwc2_glbreg_write, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static const MemoryRegionOps dwc2_mmio_fszreg_ops =3D { + .read =3D dwc2_fszreg_read, + .write =3D dwc2_fszreg_write, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static const MemoryRegionOps dwc2_mmio_hreg0_ops =3D { + .read =3D dwc2_hreg0_read, + .write =3D dwc2_hreg0_write, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static const MemoryRegionOps dwc2_mmio_hreg1_ops =3D { + .read =3D dwc2_hreg1_read, + .write =3D dwc2_hreg1_write, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static const MemoryRegionOps dwc2_mmio_pcgreg_ops =3D { + .read =3D dwc2_pcgreg_read, + .write =3D dwc2_pcgreg_write, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static const MemoryRegionOps dwc2_mmio_hreg2_ops =3D { + .read =3D dwc2_hreg2_read, + .write =3D dwc2_hreg2_write, + .valid.min_access_size =3D 4, + .valid.max_access_size =3D 4, + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static void dwc2_wakeup_endpoint(USBBus *bus, USBEndpoint *ep, + unsigned int stream) +{ + DWC2State *s =3D container_of(bus, DWC2State, bus); + + /* TODO - do something here? */ + qemu_bh_schedule(s->async_bh); +} + +static USBBusOps dwc2_bus_ops =3D { + .wakeup_endpoint =3D dwc2_wakeup_endpoint, +}; + +static void dwc2_work_timer(void *opaque) +{ + DWC2State *s =3D opaque; + + DPRINTF("dwc2_work_timer\n"); + qemu_bh_schedule(s->async_bh); +} + +/* host controller initialization */ +static void dwc2_reset(DWC2State *s) +{ + USBDevice *devs[NB_PORTS]; + int i; + + DPRINTF("dwc2_reset, s %p\n", s); + timer_del(s->frame_timer); + qemu_bh_cancel(s->async_bh); + + for (i =3D 0; i < NB_PORTS; i++) { + devs[i] =3D s->ports[i].dev; + if (devs[i] && devs[i]->attached) { + usb_detach(&s->ports[i]); + } + } + + dwc2_bus_stop(s); + + s->gotgctl =3D GOTGCTL_BSESVLD | GOTGCTL_ASESVLD | GOTGCTL_CONID_B; + s->gotgint =3D 0; + s->gahbcfg =3D 0; + s->gusbcfg =3D 5 << GUSBCFG_USBTRDTIM_SHIFT; + s->grstctl =3D GRSTCTL_AHBIDLE; + s->gintsts =3D GINTSTS_CONIDSTSCHNG | GINTSTS_PTXFEMP | GINTSTS_NPTXFE= MP | + GINTSTS_CURMODE_HOST; + s->gintmsk =3D 0; + s->grxstsr =3D 0; + s->grxstsp =3D 0; + s->grxfsiz =3D 1024; + s->gnptxfsiz =3D 1024 << FIFOSIZE_DEPTH_SHIFT; + s->gnptxsts =3D (4 << FIFOSIZE_DEPTH_SHIFT) | 1024; + s->gi2cctl =3D GI2CCTL_I2CDATSE0 | GI2CCTL_ACK; + s->gpvndctl =3D 0; + s->ggpio =3D 0; + s->guid =3D 0; + s->gsnpsid =3D 0x4f54294a; + s->ghwcfg1 =3D 0; + s->ghwcfg2 =3D (8 << GHWCFG2_DEV_TOKEN_Q_DEPTH_SHIFT) | + (4 << GHWCFG2_HOST_PERIO_TX_Q_DEPTH_SHIFT) | + (4 << GHWCFG2_NONPERIO_TX_Q_DEPTH_SHIFT) | + GHWCFG2_DYNAMIC_FIFO | + GHWCFG2_PERIO_EP_SUPPORTED | + ((NB_CHAN - 1) << GHWCFG2_NUM_HOST_CHAN_SHIFT) | + (GHWCFG2_INT_DMA_ARCH << GHWCFG2_ARCHITECTURE_SHIFT) | + (GHWCFG2_OP_MODE_NO_SRP_CAPABLE_HOST << GHWCFG2_OP_MODE_S= HIFT); + s->ghwcfg3 =3D (4096 << GHWCFG3_DFIFO_DEPTH_SHIFT) | + (4 << GHWCFG3_PACKET_SIZE_CNTR_WIDTH_SHIFT) | + (4 << GHWCFG3_XFER_SIZE_CNTR_WIDTH_SHIFT); + s->ghwcfg4 =3D 0; + s->glpmcfg =3D 0; + s->gpwrdn =3D GPWRDN_PWRDNRSTN; + s->gdfifocfg =3D 0; + s->gadpctl =3D 0; + s->grefclk =3D 0; + s->gintmsk2 =3D 0; + s->gintsts2 =3D 0; + + s->hptxfsiz =3D 500 << FIFOSIZE_DEPTH_SHIFT; + + s->hcfg =3D 2 << HCFG_RESVALID_SHIFT; + s->hfir =3D 60000; + s->hfnum =3D 0x3fff; + s->hptxsts =3D (16 << TXSTS_QSPCAVAIL_SHIFT) | 32768; + s->haint =3D 0; + s->haintmsk =3D 0; + s->hprt0 =3D 0; + + memset(s->hreg1, 0, sizeof(s->hreg1)); + memset(s->pcgreg, 0, sizeof(s->pcgreg)); + + s->sof_time =3D 0; + s->fsmps =3D 0x2778; + s->fi =3D 11999; + s->frame_number =3D 0; + + for (i =3D 0; i < NB_CHAN; i++) { + s->packet[i].needs_service =3D false; + } + + dwc2_update_irq(s); + + for (i =3D 0; i < NB_PORTS; i++) { + s->hprt0 =3D HPRT0_PWR; + if (devs[i] && devs[i]->attached) { + usb_attach(&s->ports[i]); + usb_device_reset(devs[i]); + } + } +} + +static void dwc2_realize(DWC2State *s, DeviceState *dev, Error **errp) +{ + Object *obj; + Error *err =3D NULL; + int i; + + DPRINTF("dwc2_realize, s %p dev %p\n", s, dev); + if (s->portnr > NB_PORTS) { + error_setg(errp, "Too many ports! Max port number is %d", + NB_PORTS); + return; + } + + obj =3D object_property_get_link(OBJECT(dev), "dma-mr", &err); + if (err || obj =3D=3D NULL) { + error_setg(errp, "dwc2: required dma-mr link not found: %s", + error_get_pretty(err)); + return; + } + + s->dma_mr =3D MEMORY_REGION(obj); + address_space_init(&s->dma_as, s->dma_mr, NULL); + + usb_bus_new(&s->bus, sizeof(s->bus), &dwc2_bus_ops, dev); + for (i =3D 0; i < s->portnr; i++) { + usb_register_port(&s->bus, &s->ports[i], s, i, &dwc2_port_ops, + USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL | + USB_SPEED_MASK_HIGH); + s->ports[i].dev =3D 0; + } + + s->frame_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, dwc2_work_timer, s= ); + s->async_bh =3D qemu_bh_new(dwc2_work_bh, s); + s->working =3D false; + s->next_chan =3D 0; + s->device =3D dev; +} + +static void dwc2_init(DWC2State *s, DeviceState *dev) +{ + DPRINTF("dwc2_init, s %p dev %p\n", s, dev); + + s->usb_frame_time =3D NANOSECONDS_PER_SECOND / 1000; /* 10000= 00 */ + if (NANOSECONDS_PER_SECOND >=3D USB_HZ_FS) { + s->usb_bit_time =3D NANOSECONDS_PER_SECOND / USB_HZ_FS; /* 83.3 = */ + } else { + s->usb_bit_time =3D 1; + } + + s->fi =3D 11999; + + memory_region_init(&s->mem, OBJECT(dev), "dwc2", DWC2_MMIO_SIZE); + memory_region_init_io(&s->mem_glbreg, OBJECT(dev), &dwc2_mmio_glbreg_o= ps, s, + "global", 0x70); + memory_region_init_io(&s->mem_fszreg, OBJECT(dev), &dwc2_mmio_fszreg_o= ps, s, + "hptxfsiz", 0x4); + memory_region_init_io(&s->mem_hreg0, OBJECT(dev), &dwc2_mmio_hreg0_ops= , s, + "host", 0x44); + memory_region_init_io(&s->mem_hreg1, OBJECT(dev), &dwc2_mmio_hreg1_ops= , s, + "host channels", 0x20 * NB_CHAN); + memory_region_init_io(&s->mem_pcgreg, OBJECT(dev), &dwc2_mmio_pcgreg_o= ps, s, + "power/clock", 0x8); + memory_region_init_io(&s->mem_hreg2, OBJECT(dev), &dwc2_mmio_hreg2_ops= , s, + "host fifos", NB_CHAN * 0x1000); + + memory_region_add_subregion(&s->mem, s->glbregbase, &s->mem_glbreg); + memory_region_add_subregion(&s->mem, s->fszregbase, &s->mem_fszreg); + memory_region_add_subregion(&s->mem, s->hreg0base, &s->mem_hreg0); + memory_region_add_subregion(&s->mem, s->hreg1base, &s->mem_hreg1); + memory_region_add_subregion(&s->mem, s->pcgregbase, &s->mem_pcgreg); + memory_region_add_subregion(&s->mem, s->hreg2base, &s->mem_hreg2); + +#ifdef DWC2_DO_SOFS + s->eof_timer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, + dwc2_frame_boundary, s); +#endif +} + +static void dwc2_sysbus_reset(DeviceState *dev) +{ + SysBusDevice *d =3D SYS_BUS_DEVICE(dev); + DWC2State *s =3D DWC2_USB(d); + + DPRINTF("dwc2_sysbus_reset, dev %p d %p s %p\n", dev, d, s); + dwc2_reset(s); +} + +static void dwc2_sysbus_realize(DeviceState *dev, Error **errp) +{ + SysBusDevice *d =3D SYS_BUS_DEVICE(dev); + DWC2State *s =3D DWC2_USB(dev); + + DPRINTF("dwc2_sysbus_realize, dev %p d %p s %p\n", dev, d, s); + s->glbregbase =3D 0; + s->fszregbase =3D 0x0100; + s->hreg0base =3D 0x0400; + s->hreg1base =3D 0x0500; + s->pcgregbase =3D 0x0e00; + s->hreg2base =3D 0x1000; + s->portnr =3D NB_PORTS; + s->as =3D &address_space_memory; + + DPRINTF("0x%x 0x%x 0x%x 0x%x 0x%x 0x%x\n", s->glbregbase, s->fszregbas= e, + s->hreg0base, s->hreg1base, s->pcgregbase, s->hreg2base); + dwc2_realize(s, dev, errp); + dwc2_init(s, dev); + sysbus_init_irq(d, &s->irq); + sysbus_init_mmio(d, &s->mem); +} + +static void dwc2_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + DPRINTF("dwc2_class_init, class %p dc %p\n", klass, dc); + dc->realize =3D dwc2_sysbus_realize; + dc->reset =3D dwc2_sysbus_reset; + set_bit(DEVICE_CATEGORY_USB, dc->categories); +} + +static const TypeInfo dwc2_usb_type_info =3D { + .name =3D TYPE_DWC2_USB, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(DWC2State), + .class_init =3D dwc2_class_init, +}; + +static void dwc2_usb_register_types(void) +{ + DPRINTF("dwc2_usb_register_types\n"); + type_register_static(&dwc2_usb_type_info); +} + +type_init(dwc2_usb_register_types) --=20 2.17.1 From nobody Fri May 3 21:45:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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X-Received-From: 2607:f8b0:4864:20::544 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, stefanha@gmail.com, qemu-devel@nongnu.org, Paul Zimmerman , jsnow@redhat.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" The dwc-hsotg (dwc2) USB host depends on a short packet to indicate the end of an IN transfer. The usb-storage driver currently doesn't provide this, so fix it. Signed-off-by: Paul Zimmerman --- hw/usb/dev-storage.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/hw/usb/dev-storage.c b/hw/usb/dev-storage.c index 5c4b57b06b..ae3c550042 100644 --- a/hw/usb/dev-storage.c +++ b/hw/usb/dev-storage.c @@ -229,6 +229,9 @@ static void usb_msd_copy_data(MSDState *s, USBPacket *p) usb_packet_copy(p, scsi_req_get_buf(s->req) + s->scsi_off, len); s->scsi_len -=3D len; s->scsi_off +=3D len; + if (len > s->data_len) { + len =3D s->data_len; + } s->data_len -=3D len; if (s->scsi_len =3D=3D 0 || s->data_len =3D=3D 0) { scsi_req_continue(s->req); @@ -303,6 +306,9 @@ static void usb_msd_command_complete(SCSIRequest *req, = uint32_t status, size_t r if (s->data_len) { int len =3D (p->iov.size - p->actual_length); usb_packet_skip(p, len); + if (len > s->data_len) { + len =3D s->data_len; + } s->data_len -=3D len; } if (s->data_len =3D=3D 0) { @@ -469,6 +475,9 @@ static void usb_msd_handle_data(USBDevice *dev, USBPack= et *p) int len =3D p->iov.size - p->actual_length; if (len) { usb_packet_skip(p, len); + if (len > s->data_len) { + len =3D s->data_len; + } s->data_len -=3D len; if (s->data_len =3D=3D 0) { s->mode =3D USB_MSDM_CSW; @@ -528,13 +537,17 @@ static void usb_msd_handle_data(USBDevice *dev, USBPa= cket *p) int len =3D p->iov.size - p->actual_length; if (len) { usb_packet_skip(p, len); + if (len > s->data_len) { + len =3D s->data_len; + } s->data_len -=3D len; if (s->data_len =3D=3D 0) { s->mode =3D USB_MSDM_CSW; } } } - if (p->actual_length < p->iov.size) { + if (p->actual_length < p->iov.size && (p->short_not_ok || + s->scsi_len >=3D p->ep->max_packet_size)) { DPRINTF("Deferring packet %p [wait data-in]\n", p); s->packet =3D p; p->status =3D USB_RET_ASYNC; --=20 2.17.1 From nobody Fri May 3 21:45:02 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; 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h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Vxb2BeSPk/Bmh9uLAezVoaXmCjxCb8Nm9qZIiQVVzXg=; b=qn/y3vfyQnYgMGnjKTCLypO0NpPtXBfvd/pNLDFEKOfM5T/XL+tv8xhJeh+a/o+XDx 79yId2eEj8FaifvWhmSSrBdKL/H79yvgDksQAKhTrbrO8Uex3KaoUmMiJV/o7dq8gzEX JkVXOR5Web1PqTdcpsUqxEJ3I3k8G87sYvcvbGKltXDVY/IMQSLzjeLu6tblgxHRamFf /EdvA4EPlH2+/gro9iEEzeBvG++ixeKVdK2ugZZOW5P3E/zSSjW6TSp7XA/QetHINdD9 V+8jNOusJDzIBMghIi/pYoogIiYisRjYzka2uefWhOYvpwhM7y2Zu7FXKPSCxyLafgEi cEBQ== X-Gm-Message-State: ANhLgQ2L2pf+7TMwVWTWIk0NXhWLKqlEQ7jn1J6BpZgPZcgWqkfwnYxz kV2GkpuNRsfdok0gh0+SPeQ= X-Google-Smtp-Source: ADFU+vsB7eziAwR7qguk7cXZKccP0DuxMDYBea7rbRjjulP2wfM8+ochWUKMtj0oXX+i7x/B+ptEig== X-Received: by 2002:a17:90b:3683:: with SMTP id mj3mr21426132pjb.153.1584916137232; Sun, 22 Mar 2020 15:28:57 -0700 (PDT) From: Paul Zimmerman To: kraxel@redhat.com Subject: [PATCH 6/6] Wire in the dwc-hsotg USB host controller emulation Date: Sun, 22 Mar 2020 15:27:26 -0700 Message-Id: <20200322222726.10244-7-pauldzim@gmail.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20200322222726.10244-1-pauldzim@gmail.com> References: <20200322222726.10244-1-pauldzim@gmail.com> X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1041 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, stefanha@gmail.com, qemu-devel@nongnu.org, Paul Zimmerman , jsnow@redhat.com, f4bug@amsat.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Wire the dwc-hsotg (dwc2) emulation into Qemu Signed-off-by: Paul Zimmerman --- hw/arm/bcm2835_peripherals.c | 21 ++++++++++++++++++++- hw/usb/Kconfig | 5 +++++ hw/usb/Makefile.objs | 1 + include/hw/arm/bcm2835_peripherals.h | 3 ++- 4 files changed, 28 insertions(+), 2 deletions(-) diff --git a/hw/arm/bcm2835_peripherals.c b/hw/arm/bcm2835_peripherals.c index dd7e6883cb..932d084a50 100644 --- a/hw/arm/bcm2835_peripherals.c +++ b/hw/arm/bcm2835_peripherals.c @@ -127,6 +127,13 @@ static void bcm2835_peripherals_init(Object *obj) sysbus_init_child_obj(obj, "mphi", &s->mphi, sizeof(s->mphi), TYPE_BCM2835_MPHI); =20 + /* DWC2 */ + sysbus_init_child_obj(obj, "dwc2", &s->dwc2, sizeof(s->dwc2), + TYPE_DWC2_USB); + + object_property_add_const_link(OBJECT(&s->dwc2), "dma-mr", + OBJECT(&s->gpu_bus_mr), &error_abort); + object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhci", OBJECT(&s->sdhci.sdbus), &error_abort); object_property_add_const_link(OBJECT(&s->gpio), "sdbus-sdhost", @@ -384,6 +391,19 @@ static void bcm2835_peripherals_realize(DeviceState *d= ev, Error **errp) qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, INTERRUPT_HOSTPORT)); =20 + /* DWC2 */ + object_property_set_bool(OBJECT(&s->dwc2), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + + memory_region_add_subregion(&s->peri_mr, USB_OTG_OFFSET, + sysbus_mmio_get_region(SYS_BUS_DEVICE(&s->dwc2), 0)); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->dwc2), 0, + qdev_get_gpio_in_named(DEVICE(&s->ic), BCM2835_IC_GPU_IRQ, + INTERRUPT_USB)); + create_unimp(s, &s->armtmr, "bcm2835-sp804", ARMCTRL_TIMER0_1_OFFSET, = 0x40); create_unimp(s, &s->cprman, "bcm2835-cprman", CPRMAN_OFFSET, 0x1000); create_unimp(s, &s->a2w, "bcm2835-a2w", A2W_OFFSET, 0x1000); @@ -397,7 +417,6 @@ static void bcm2835_peripherals_realize(DeviceState *de= v, Error **errp) create_unimp(s, &s->otp, "bcm2835-otp", OTP_OFFSET, 0x80); create_unimp(s, &s->dbus, "bcm2835-dbus", DBUS_OFFSET, 0x8000); create_unimp(s, &s->ave0, "bcm2835-ave0", AVE0_OFFSET, 0x8000); - create_unimp(s, &s->dwc2, "dwc-usb2", USB_OTG_OFFSET, 0x1000); create_unimp(s, &s->sdramc, "bcm2835-sdramc", SDRAMC_OFFSET, 0x100); } =20 diff --git a/hw/usb/Kconfig b/hw/usb/Kconfig index 464348ba14..d4d8c37c28 100644 --- a/hw/usb/Kconfig +++ b/hw/usb/Kconfig @@ -46,6 +46,11 @@ config USB_MUSB bool select USB =20 +config USB_DWC2 + bool + default y + select USB + config TUSB6010 bool select USB_MUSB diff --git a/hw/usb/Makefile.objs b/hw/usb/Makefile.objs index 66835e5bf7..fa5c3fa1b8 100644 --- a/hw/usb/Makefile.objs +++ b/hw/usb/Makefile.objs @@ -12,6 +12,7 @@ common-obj-$(CONFIG_USB_EHCI_SYSBUS) +=3D hcd-ehci-sysbus= .o common-obj-$(CONFIG_USB_XHCI) +=3D hcd-xhci.o common-obj-$(CONFIG_USB_XHCI_NEC) +=3D hcd-xhci-nec.o common-obj-$(CONFIG_USB_MUSB) +=3D hcd-musb.o +common-obj-$(CONFIG_USB_DWC2) +=3D hcd-dwc2.o =20 common-obj-$(CONFIG_TUSB6010) +=3D tusb6010.o common-obj-$(CONFIG_IMX) +=3D chipidea.o diff --git a/include/hw/arm/bcm2835_peripherals.h b/include/hw/arm/bcm2835_= peripherals.h index 77958ca60e..0841d54614 100644 --- a/include/hw/arm/bcm2835_peripherals.h +++ b/include/hw/arm/bcm2835_peripherals.h @@ -26,6 +26,7 @@ #include "hw/sd/bcm2835_sdhost.h" #include "hw/gpio/bcm2835_gpio.h" #include "hw/timer/bcm2835_systmr.h" +#include "hw/usb/hcd-dwc2.h" #include "hw/misc/unimp.h" =20 #define TYPE_BCM2835_PERIPHERALS "bcm2835-peripherals" @@ -66,7 +67,7 @@ typedef struct BCM2835PeripheralState { UnimplementedDeviceState ave0; UnimplementedDeviceState bscsl; UnimplementedDeviceState smi; - UnimplementedDeviceState dwc2; + DWC2State dwc2; UnimplementedDeviceState sdramc; } BCM2835PeripheralState; =20 --=20 2.17.1