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X-Received-From: 2607:f8b0:4864:20::641 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Andrey Smirnov , qemu-devel@nongnu.org, Jean-Christophe Dubois , qemu-arm@nongnu.org, Peter Chubb , Guenter Roeck Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Implement full support for the watchdog in i.MX systems. Pretimeout support is optional because the watchdog hardware on i.MX31 does not support pretimeouts. Signed-off-by: Guenter Roeck --- v2: Fixup of CONFIG_WDT_IMX -> CONFIG_WDT_IMX2 moved to patch 1/8 hw/watchdog/wdt_imx2.c | 196 +++++++++++++++++++++++++++++++-- include/hw/watchdog/wdt_imx2.h | 49 ++++++++- 2 files changed, 231 insertions(+), 14 deletions(-) diff --git a/hw/watchdog/wdt_imx2.c b/hw/watchdog/wdt_imx2.c index ad1ef02e9e..f5339f3590 100644 --- a/hw/watchdog/wdt_imx2.c +++ b/hw/watchdog/wdt_imx2.c @@ -13,24 +13,157 @@ #include "qemu/bitops.h" #include "qemu/module.h" #include "sysemu/watchdog.h" +#include "migration/vmstate.h" +#include "hw/qdev-properties.h" =20 #include "hw/watchdog/wdt_imx2.h" =20 -#define IMX2_WDT_WCR_WDA BIT(5) /* -> External Reset WDOG_B */ -#define IMX2_WDT_WCR_SRS BIT(4) /* -> Software Reset Signal */ +static void imx2_wdt_interrupt(void *opaque) +{ + IMX2WdtState *s =3D IMX2_WDT(opaque); + + s->wicr |=3D IMX2_WDT_WICR_WTIS; + qemu_set_irq(s->irq, 1); +} =20 -static uint64_t imx2_wdt_read(void *opaque, hwaddr addr, - unsigned int size) +static void imx2_wdt_expired(void *opaque) { + IMX2WdtState *s =3D IMX2_WDT(opaque); + + s->wrsr =3D IMX2_WDT_WRSR_TOUT; + + /* Perform watchdog action if watchdog is enabled */ + if (s->wcr & IMX2_WDT_WCR_WDE) { + watchdog_perform_action(); + } +} + +static void imx2_wdt_reset(DeviceState *dev) +{ + IMX2WdtState *s =3D IMX2_WDT(dev); + + s->wcr =3D IMX2_WDT_WCR_WDA | IMX2_WDT_WCR_SRS; + s->wsr =3D 0; + s->wrsr &=3D ~(IMX2_WDT_WRSR_TOUT | IMX2_WDT_WRSR_SFTW); + s->wicr =3D 4; + s->wmcr =3D IMX2_WDT_WMCR_PDE; +} + +static uint64_t imx2_wdt_read(void *opaque, hwaddr addr, unsigned int size) +{ + IMX2WdtState *s =3D IMX2_WDT(opaque); + + switch (addr) { + case IMX2_WDT_WCR: + return s->wcr; + case IMX2_WDT_WSR: + return s->wsr; + case IMX2_WDT_WRSR: + return s->wrsr; + case IMX2_WDT_WICR: + return s->wicr; + case IMX2_WDT_WMCR: + return s->wmcr; + } return 0; } =20 +static void imx_wdt2_update_itimer(IMX2WdtState *s, bool start) +{ + bool running =3D (s->wcr & IMX2_WDT_WCR_WDE) && (s->wcr & IMX2_WDT_WCR= _WT); + bool enabled =3D s->wicr & IMX2_WDT_WICR_WIE; + + ptimer_transaction_begin(s->itimer); + if (start || !enabled) { + ptimer_stop(s->itimer); + } + if (running && enabled) { + int count =3D ptimer_get_count(s->timer); + int pretimeout =3D s->wicr & IMX2_WDT_WICR_WICT; + + /* + * Only (re-)start pretimeout timer if its counter value is larger + * than 0. Otherwise it will fire right away and we'll get an + * interrupt loop. + */ + if (count > pretimeout) { + ptimer_set_count(s->itimer, count - pretimeout); + if (start) { + ptimer_run(s->itimer, 1); + } + } + } + ptimer_transaction_commit(s->itimer); +} + +static void imx_wdt2_update_timer(IMX2WdtState *s, bool start) +{ + ptimer_transaction_begin(s->timer); + if (start) { + ptimer_stop(s->timer); + } + if ((s->wcr & IMX2_WDT_WCR_WDE) && (s->wcr & IMX2_WDT_WCR_WT)) { + int count =3D (s->wcr & IMX2_WDT_WCR_WT) >> 8; + + ptimer_set_count(s->timer, count); + if (start) { + ptimer_run(s->timer, 1); + } + } + ptimer_transaction_commit(s->timer); + if (s->pretimeout_support) { + imx_wdt2_update_itimer(s, start); + } +} + static void imx2_wdt_write(void *opaque, hwaddr addr, uint64_t value, unsigned int size) { - if (addr =3D=3D IMX2_WDT_WCR && - (~value & (IMX2_WDT_WCR_WDA | IMX2_WDT_WCR_SRS))) { - watchdog_perform_action(); + IMX2WdtState *s =3D IMX2_WDT(opaque); + + switch (addr) { + case IMX2_WDT_WCR: + s->wcr =3D value; + if (!(value & IMX2_WDT_WCR_SRS)) { + s->wrsr =3D IMX2_WDT_WRSR_SFTW; + } + if (!(value & (IMX2_WDT_WCR_WDA | IMX2_WDT_WCR_SRS)) || + (!(value & IMX2_WDT_WCR_WT) && (value & IMX2_WDT_WCR_WDE))) { + watchdog_perform_action(); + } + s->wcr |=3D IMX2_WDT_WCR_SRS; + imx_wdt2_update_timer(s, true); + break; + case IMX2_WDT_WSR: + if (s->wsr =3D=3D IMX2_WDT_SEQ1 && value =3D=3D IMX2_WDT_SEQ2) { + imx_wdt2_update_timer(s, false); + } + s->wsr =3D value; + break; + case IMX2_WDT_WRSR: + break; + case IMX2_WDT_WICR: + if (!s->pretimeout_support) { + return; + } + /* The pretimeout value is write-once */ + if (s->pretimeout_locked) { + value &=3D ~IMX2_WDT_WICR_WICT; + s->wicr &=3D (IMX2_WDT_WICR_WTIS | IMX2_WDT_WICR_WICT); + } else { + s->wicr &=3D IMX2_WDT_WICR_WTIS; + } + s->wicr |=3D value & (IMX2_WDT_WICR_WIE | IMX2_WDT_WICR_WICT); + if (value & IMX2_WDT_WICR_WTIS) { + s->wicr &=3D ~IMX2_WDT_WICR_WTIS; + qemu_set_irq(s->irq, 0); + } + imx_wdt2_update_itimer(s, true); + s->pretimeout_locked =3D true; + break; + case IMX2_WDT_WMCR: + s->wmcr =3D value & IMX2_WDT_WMCR_PDE; + break; } } =20 @@ -45,28 +178,67 @@ static const MemoryRegionOps imx2_wdt_ops =3D { * real device but in practice there is no reason for a guest * to access this device unaligned. */ - .min_access_size =3D 4, - .max_access_size =3D 4, + .min_access_size =3D 2, + .max_access_size =3D 2, .unaligned =3D false, }, }; =20 +static const VMStateDescription vmstate_imx2_wdt =3D { + .name =3D "imx2.wdt", + .fields =3D (VMStateField[]) { + VMSTATE_PTIMER(timer, IMX2WdtState), + VMSTATE_PTIMER(itimer, IMX2WdtState), + VMSTATE_BOOL(pretimeout_locked, IMX2WdtState), + VMSTATE_UINT16(wcr, IMX2WdtState), + VMSTATE_UINT16(wsr, IMX2WdtState), + VMSTATE_UINT16(wrsr, IMX2WdtState), + VMSTATE_UINT16(wmcr, IMX2WdtState), + VMSTATE_UINT16(wicr, IMX2WdtState), + VMSTATE_END_OF_LIST() + } +}; + static void imx2_wdt_realize(DeviceState *dev, Error **errp) { IMX2WdtState *s =3D IMX2_WDT(dev); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(dev); =20 memory_region_init_io(&s->mmio, OBJECT(dev), &imx2_wdt_ops, s, - TYPE_IMX2_WDT".mmio", - IMX2_WDT_REG_NUM * sizeof(uint16_t)); - sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); + TYPE_IMX2_WDT, + IMX2_WDT_MMIO_SIZE); + sysbus_init_mmio(sbd, &s->mmio); + sysbus_init_irq(sbd, &s->irq); + + s->timer =3D ptimer_init(imx2_wdt_expired, s, PTIMER_POLICY_DEFAULT); + ptimer_transaction_begin(s->timer); + ptimer_set_freq(s->timer, 2); + ptimer_set_limit(s->timer, 0xff, 1); + ptimer_transaction_commit(s->timer); + if (s->pretimeout_support) { + s->itimer =3D ptimer_init(imx2_wdt_interrupt, s, PTIMER_POLICY_DEF= AULT); + ptimer_transaction_begin(s->itimer); + ptimer_set_freq(s->itimer, 2); + ptimer_set_limit(s->itimer, 0xff, 1); + ptimer_transaction_commit(s->itimer); + } } =20 +static Property imx2_wdt_properties[] =3D { + DEFINE_PROP_BOOL("pretimeout-support", IMX2WdtState, pretimeout_suppor= t, + false), +}; + static void imx2_wdt_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); =20 + device_class_set_props(dc, imx2_wdt_properties); dc->realize =3D imx2_wdt_realize; + dc->reset =3D imx2_wdt_reset; + dc->vmsd =3D &vmstate_imx2_wdt; + dc->desc =3D "i.MX watchdog timer"; set_bit(DEVICE_CATEGORY_MISC, dc->categories); } =20 diff --git a/include/hw/watchdog/wdt_imx2.h b/include/hw/watchdog/wdt_imx2.h index b91b002528..bed7aa6835 100644 --- a/include/hw/watchdog/wdt_imx2.h +++ b/include/hw/watchdog/wdt_imx2.h @@ -12,22 +12,67 @@ #ifndef IMX2_WDT_H #define IMX2_WDT_H =20 +#include "qemu/bitops.h" #include "hw/sysbus.h" +#include "hw/irq.h" +#include "hw/ptimer.h" =20 #define TYPE_IMX2_WDT "imx2.wdt" #define IMX2_WDT(obj) OBJECT_CHECK(IMX2WdtState, (obj), TYPE_IMX2_WDT) =20 enum IMX2WdtRegisters { - IMX2_WDT_WCR =3D 0x0000, - IMX2_WDT_REG_NUM =3D 0x0008 / sizeof(uint16_t) + 1, + IMX2_WDT_WCR =3D 0x0000, /* Control Register */ + IMX2_WDT_WSR =3D 0x0002, /* Service Register */ + IMX2_WDT_WRSR =3D 0x0004, /* Reset Status Register */ + IMX2_WDT_WICR =3D 0x0006, /* Interrupt Control Register */ + IMX2_WDT_WMCR =3D 0x0008, /* Misc Register */ }; =20 +#define IMX2_WDT_MMIO_SIZE 0x000a + +/* Control Register definitions */ +#define IMX2_WDT_WCR_WT (0xFF << 8) /* Watchdog Timeout Field */ +#define IMX2_WDT_WCR_WDA BIT(5) /* WDOG Assertion */ +#define IMX2_WDT_WCR_SRS BIT(4) /* Software Reset Signal */ +#define IMX2_WDT_WCR_WDT BIT(3) /* WDOG Timeout Assertion */ +#define IMX2_WDT_WCR_WDE BIT(2) /* Watchdog Enable */ +#define IMX2_WDT_WCR_WDZST BIT(0) /* Watchdog Timer Suspend */ + +/* Service Register definitions */ +#define IMX2_WDT_SEQ1 0x5555 /* service sequence 1 */ +#define IMX2_WDT_SEQ2 0xAAAA /* service sequence 2 */ + +/* Reset Status Register definitions */ +#define IMX2_WDT_WRSR_TOUT BIT(1) /* Reset due to Timeout */ +#define IMX2_WDT_WRSR_SFTW BIT(0) /* Reset due to Timeout */ + +/* Interrupt Control Register definitions */ +#define IMX2_WDT_WICR_WIE BIT(15) /* Interrupt Enable */ +#define IMX2_WDT_WICR_WTIS BIT(14) /* Interrupt Status */ +#define IMX2_WDT_WICR_WICT 0xff /* Interrupt Timeout */ + +/* Misc Control Register definitions */ +#define IMX2_WDT_WMCR_PDE BIT(0) /* Power-Down Enable */ =20 typedef struct IMX2WdtState { /* */ SysBusDevice parent_obj; =20 + /*< public >*/ MemoryRegion mmio; + qemu_irq irq; + + struct ptimer_state *timer; + struct ptimer_state *itimer; + + bool pretimeout_support; + bool pretimeout_locked; + + uint16_t wcr; + uint16_t wsr; + uint16_t wrsr; + uint16_t wicr; + uint16_t wmcr; } IMX2WdtState; =20 #endif /* IMX2_WDT_H */ --=20 2.17.1