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[83.59.163.96]) by smtp.gmail.com with ESMTPSA id b202sm4618697wmd.15.2020.03.17.09.36.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Mar 2020 09:36:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EjpfhtrhWhEHFpW93EzAMWeGfbH4KcOFutrDPiv0B0w=; b=heMko0AfFF4eMjLvWbKPOjUdCoIKWKY53Eevtp1i1Y0jqJL1ilFShn5QOXlmxt26ka kflSDKu+H5Tw9ldo5MCjsHeiS2DT8fEDS/3JMP3MguQx5dh6c/Csm0Tq0T4MKmkp6htZ CyDxeUbH+mvsH0wyAOCB1gt3fVQnDDx3qByB5R/gBmdb14EUosik70rL7GAqENLEl3Ki FX+RmvD9/pLPkrjwtep39/77c5Oqjd0XB/RrKWM5XH5mZ1bm8xeewNJHrt/SM2ltmhoW u2yRtwm4SSCFxvS46QQOcGgfffrChWBEvnV0tmFvKjN8jJ0RLx38U39a2sendo+msyu4 atkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=EjpfhtrhWhEHFpW93EzAMWeGfbH4KcOFutrDPiv0B0w=; b=XZns+obEbe612UNihB92JqbuZA+kzz3PnYlZTVIFBIWqBZOQd82N3DoGb+pIH21OQV vxxr1L/FHJkPF8iMnM5/xOINbpb3TdOOyhu7jzpDguGntqSP4vcdFR7z3eUAoje0cQI+ CIX3+VgwDfoRtgtsABew7Gke1noaon/96tJnKiybHv0owg2UH0K8taUzne6vlpP24rvf krv8fgO/QJqyP7NBMfvrI9wc5yeLSsBk5/b12DjtTwZ/ryERSHhtyicOHQhCxBr2hYdB 7MSUAKwHgCGP+AcCOjp/8+DUco5l+lOsoKWjHTmBL975WJ9mk7NrK5wIqFcRoH1v7j+w za6w== X-Gm-Message-State: ANhLgQ0LXxOusiO0hAi8Wg+pACrJ2m15k/eooUzKYC9Ph6A5bwrKcdQf 8cT6GQ7KMEXoaoXrIyuQMp9eZFhm X-Google-Smtp-Source: ADFU+vtNyzxj02eip5vQ1x4AKdtoUXqqZfybVm/8LBNKuVof/79U+3UI7zYkVisVren9pNfnOTnr5g== X-Received: by 2002:adf:f94f:: with SMTP id q15mr6893335wrr.65.1584462979719; Tue, 17 Mar 2020 09:36:19 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 01/13] hw/registerfields.h: Add 8bit and 16bit register macros Date: Tue, 17 Mar 2020 17:36:04 +0100 Message-Id: <20200317163616.30027-2-f4bug@amsat.org> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200317163616.30027-1-f4bug@amsat.org> References: <20200317163616.30027-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato , Alistair Francis , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Yoshinori Sato Some RX peripheral use 8bit and 16bit registers. Add the 8bit and 16bit APIs. Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Signed-off-by: Yoshinori Sato Signed-off-by: Richard Henderson Message-Id: <20200224141923.82118-4-ysato@users.sourceforge.jp> Acked-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/registerfields.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h index 2659a58737..0407edb7ec 100644 --- a/include/hw/registerfields.h +++ b/include/hw/registerfields.h @@ -22,6 +22,14 @@ enum { A_ ## reg =3D (addr) }; = \ enum { R_ ## reg =3D (addr) / 4 }; =20 +#define REG8(reg, addr) \ + enum { A_ ## reg =3D (addr) }; = \ + enum { R_ ## reg =3D (addr) }; + +#define REG16(reg, addr) \ + enum { A_ ## reg =3D (addr) }; = \ + enum { R_ ## reg =3D (addr) / 2 }; + /* Define SHIFT, LENGTH and MASK constants for a field within a register */ =20 /* This macro will define R_FOO_BAR_MASK, R_FOO_BAR_SHIFT and R_FOO_BAR_LE= NGTH @@ -34,6 +42,12 @@ MAKE_64BIT_MASK(shift, length)}; =20 /* Extract a field from a register */ +#define FIELD_EX8(storage, reg, field) \ + extract8((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH) +#define FIELD_EX16(storage, reg, field) \ + extract16((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH) #define FIELD_EX32(storage, reg, field) \ extract32((storage), R_ ## reg ## _ ## field ## _SHIFT, \ R_ ## reg ## _ ## field ## _LENGTH) @@ -49,6 +63,22 @@ * Assigning values larger then the target field will result in * compilation warnings. */ +#define FIELD_DP8(storage, reg, field, val) ({ \ + struct { \ + unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \ + } v =3D { .v =3D val }; = \ + uint8_t d; \ + d =3D deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, = \ + R_ ## reg ## _ ## field ## _LENGTH, v.v); \ + d; }) +#define FIELD_DP16(storage, reg, field, val) ({ \ + struct { \ + unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \ + } v =3D { .v =3D val }; = \ + uint16_t d; \ + d =3D deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, = \ + R_ ## reg ## _ ## field ## _LENGTH, v.v); \ + d; }) #define FIELD_DP32(storage, reg, field, val) ({ \ struct { \ unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \ --=20 2.21.1