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[83.59.163.96]) by smtp.gmail.com with ESMTPSA id b202sm4618697wmd.15.2020.03.17.09.36.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Mar 2020 09:36:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EjpfhtrhWhEHFpW93EzAMWeGfbH4KcOFutrDPiv0B0w=; b=heMko0AfFF4eMjLvWbKPOjUdCoIKWKY53Eevtp1i1Y0jqJL1ilFShn5QOXlmxt26ka kflSDKu+H5Tw9ldo5MCjsHeiS2DT8fEDS/3JMP3MguQx5dh6c/Csm0Tq0T4MKmkp6htZ CyDxeUbH+mvsH0wyAOCB1gt3fVQnDDx3qByB5R/gBmdb14EUosik70rL7GAqENLEl3Ki FX+RmvD9/pLPkrjwtep39/77c5Oqjd0XB/RrKWM5XH5mZ1bm8xeewNJHrt/SM2ltmhoW u2yRtwm4SSCFxvS46QQOcGgfffrChWBEvnV0tmFvKjN8jJ0RLx38U39a2sendo+msyu4 atkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=EjpfhtrhWhEHFpW93EzAMWeGfbH4KcOFutrDPiv0B0w=; b=XZns+obEbe612UNihB92JqbuZA+kzz3PnYlZTVIFBIWqBZOQd82N3DoGb+pIH21OQV vxxr1L/FHJkPF8iMnM5/xOINbpb3TdOOyhu7jzpDguGntqSP4vcdFR7z3eUAoje0cQI+ CIX3+VgwDfoRtgtsABew7Gke1noaon/96tJnKiybHv0owg2UH0K8taUzne6vlpP24rvf krv8fgO/QJqyP7NBMfvrI9wc5yeLSsBk5/b12DjtTwZ/ryERSHhtyicOHQhCxBr2hYdB 7MSUAKwHgCGP+AcCOjp/8+DUco5l+lOsoKWjHTmBL975WJ9mk7NrK5wIqFcRoH1v7j+w za6w== X-Gm-Message-State: ANhLgQ0LXxOusiO0hAi8Wg+pACrJ2m15k/eooUzKYC9Ph6A5bwrKcdQf 8cT6GQ7KMEXoaoXrIyuQMp9eZFhm X-Google-Smtp-Source: ADFU+vtNyzxj02eip5vQ1x4AKdtoUXqqZfybVm/8LBNKuVof/79U+3UI7zYkVisVren9pNfnOTnr5g== X-Received: by 2002:adf:f94f:: with SMTP id q15mr6893335wrr.65.1584462979719; Tue, 17 Mar 2020 09:36:19 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 01/13] hw/registerfields.h: Add 8bit and 16bit register macros Date: Tue, 17 Mar 2020 17:36:04 +0100 Message-Id: <20200317163616.30027-2-f4bug@amsat.org> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200317163616.30027-1-f4bug@amsat.org> References: <20200317163616.30027-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::441 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato , Alistair Francis , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Yoshinori Sato Some RX peripheral use 8bit and 16bit registers. Add the 8bit and 16bit APIs. Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Tested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Signed-off-by: Yoshinori Sato Signed-off-by: Richard Henderson Message-Id: <20200224141923.82118-4-ysato@users.sourceforge.jp> Acked-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/hw/registerfields.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/include/hw/registerfields.h b/include/hw/registerfields.h index 2659a58737..0407edb7ec 100644 --- a/include/hw/registerfields.h +++ b/include/hw/registerfields.h @@ -22,6 +22,14 @@ enum { A_ ## reg =3D (addr) }; = \ enum { R_ ## reg =3D (addr) / 4 }; =20 +#define REG8(reg, addr) \ + enum { A_ ## reg =3D (addr) }; = \ + enum { R_ ## reg =3D (addr) }; + +#define REG16(reg, addr) \ + enum { A_ ## reg =3D (addr) }; = \ + enum { R_ ## reg =3D (addr) / 2 }; + /* Define SHIFT, LENGTH and MASK constants for a field within a register */ =20 /* This macro will define R_FOO_BAR_MASK, R_FOO_BAR_SHIFT and R_FOO_BAR_LE= NGTH @@ -34,6 +42,12 @@ MAKE_64BIT_MASK(shift, length)}; =20 /* Extract a field from a register */ +#define FIELD_EX8(storage, reg, field) \ + extract8((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH) +#define FIELD_EX16(storage, reg, field) \ + extract16((storage), R_ ## reg ## _ ## field ## _SHIFT, \ + R_ ## reg ## _ ## field ## _LENGTH) #define FIELD_EX32(storage, reg, field) \ extract32((storage), R_ ## reg ## _ ## field ## _SHIFT, \ R_ ## reg ## _ ## field ## _LENGTH) @@ -49,6 +63,22 @@ * Assigning values larger then the target field will result in * compilation warnings. */ +#define FIELD_DP8(storage, reg, field, val) ({ \ + struct { \ + unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \ + } v =3D { .v =3D val }; = \ + uint8_t d; \ + d =3D deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, = \ + R_ ## reg ## _ ## field ## _LENGTH, v.v); \ + d; }) +#define FIELD_DP16(storage, reg, field, val) ({ \ + struct { \ + unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \ + } v =3D { .v =3D val }; = \ + uint16_t d; \ + d =3D deposit32((storage), R_ ## reg ## _ ## field ## _SHIFT, = \ + R_ ## reg ## _ ## field ## _LENGTH, v.v); \ + d; }) #define FIELD_DP32(storage, reg, field, val) ({ \ struct { \ unsigned int v:R_ ## reg ## _ ## field ## _LENGTH; \ --=20 2.21.1 From nobody Sun May 5 08:48:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1584463856; cv=none; d=zohomail.com; s=zohoarc; b=BBZT3HYmdv6zVrhGJEjgaEiBMFuXMw+xloV8QgLpW1BHwLW2XwwPqrOifS8L4qgqb5zKtoN3B/Q8YnjcKUK9L0TEJqMj32sS0Ksuec8ccbzfnHpR4Hify4y7IzyHLNMeLNUqMSo6SHTdr/CtZ1g0Nq3R0W9FB6HUhhwNP8E3sxM= ARC-Message-Signature: i=1; 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[83.59.163.96]) by smtp.gmail.com with ESMTPSA id b202sm4618697wmd.15.2020.03.17.09.36.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Mar 2020 09:36:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sjkBQghb6dsOn8Obc8m8iZPN9+qM1PmqISTfmTmQMJM=; b=YwxPg0iHsCSPaktGuzy8ylRnnQUt3CH0dXDHXHjuLRbkmSWNDVTyATTcl5UpbYp6N7 OCtDHSZHMZLxVGbII/g0jBz8CHS0tnYCNRwv3TKEdQMAGrasO5naUJNOaqwIEvM4xPKI kNXGTrOIM2DJYg6gHTcR/w0p6+Kxspw+uzgk9SJasK1sv/gliqpfMXDQA+edb9XF6SUI OU9ZrAPaJsK+4ta+TT6A+UsMbX4CbNTC+JB0pppUL0Iso3Qnma71E3LEN+jEmoUpsvD9 guOsRmCpEZLS2ggCEfCuvbhs3R29DU6CvrOGQT+HTupsXe2gVkwgUrM+W9Gsn0bsLF0J AD2g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=sjkBQghb6dsOn8Obc8m8iZPN9+qM1PmqISTfmTmQMJM=; b=VcujB3N/iFB6vl4RP0VtMmXVNiupZ+Udr7taLWvKI6yDQHUWd8m2Is8GIfEwfmoXm/ rfPqjX3jMz+ruSNeKa+hDWFPOBoCGszjvJqvs8da7EKC8tSlwFdyDPX2X0UrqyBwxsxB BaRQiAe27a7uqqU8BxFOodYxu2Ai7jLhAsMAdRY+yV4CKtlNJXVJR3YS80XNgcYdC4tq /cPUz0YgUSM3nqiUYjGDZqYvruEmIChIqqo8S7IaIomQd6lSBUFP1vdtTkZnZbvqJ7Gc yf9Wm8xmhsLDVHvNs1y8XoHdUyAjKyGPgcEBYBYsbZipZCg8aNytB+cYi4fcESOg4/0m BH7g== X-Gm-Message-State: ANhLgQ2HQEBVdXD9IqDoi70FM2QRPXC9YUfzw/dVDXvfrj8gw2l458nn 4JvI3ClWpBHmvk70RJJul4CQM3DM X-Google-Smtp-Source: ADFU+vt1kb+mvLjU9MyOiu/k6dNA3MohKQtf/Fly/dw/SBdGtR8qUOo69BcgMOKlfKmLSrZ0D4fWrA== X-Received: by 2002:a5d:5342:: with SMTP id t2mr7084621wrv.104.1584462980975; Tue, 17 Mar 2020 09:36:20 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 02/13] MAINTAINERS: Add entry for the Renesas RX architecture Date: Tue, 17 Mar 2020 17:36:05 +0100 Message-Id: <20200317163616.30027-3-f4bug@amsat.org> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200317163616.30027-1-f4bug@amsat.org> References: <20200317163616.30027-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::434 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yoshinori Sato , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Yoshinori Sato Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Yoshinori Sato Signed-off-by: Richard Henderson Message-Id: <20200224141923.82118-2-ysato@users.sourceforge.jp> Acked-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- MAINTAINERS | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 32867bc636..3463533aee 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -276,6 +276,11 @@ F: include/hw/riscv/ F: linux-user/host/riscv32/ F: linux-user/host/riscv64/ =20 +RENESAS RX CPUs +M: Yoshinori Sato +S: Maintained +F: target/rx/ + S390 TCG CPUs M: Richard Henderson M: David Hildenbrand --=20 2.21.1 From nobody Sun May 5 08:48:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1584463949; cv=none; d=zohomail.com; s=zohoarc; b=cRkMdwUfiAiZJOFn9fMK09OkatVDFvtLOgWs5pH3un1syvTwBQn89sd+RBSqG2hZxZclrf7llctuL8iDdmC7w/likgVrl4gCjnnlQR6SmhWBjtOIUOpgONCte1rxUg7VdSyvetPvkz/47F/Wa+aK8meQeNFJE5FBvBQfDfiFhHA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1584463949; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=NItFYL8c54YYDddOlQi5GBmfNL8EWnzRmo0PxaX26Jw=; b=YUYhIpnspbXdV4QAbB+KlYTQQlk7ISCYcbTGZYS7YyfK3xmohVEjub7gSWEf5KaTNqaFbebi7780YdI6mT/HkU7up8jaiKqP6za4KZffR8CVyDbHirgK+K9/HbB73lkNx9CXVbGN5MRL676a0o+4aE/UkKhJ3uFTUdY/Ltafb/0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1584463949930804.6238903102608; Tue, 17 Mar 2020 09:52:29 -0700 (PDT) Received: from localhost ([::1]:36882 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jEFS8-0001mg-6S for importer@patchew.org; Tue, 17 Mar 2020 12:52:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36001) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jEFCm-0003y2-VC for qemu-devel@nongnu.org; Tue, 17 Mar 2020 12:36:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jEFCc-00033q-OM for qemu-devel@nongnu.org; Tue, 17 Mar 2020 12:36:36 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:36766) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1jEFCc-0002ua-66 for qemu-devel@nongnu.org; Tue, 17 Mar 2020 12:36:26 -0400 Received: by mail-wm1-x331.google.com with SMTP id g62so22780791wme.1 for ; Tue, 17 Mar 2020 09:36:26 -0700 (PDT) Received: from x1w.redhat.com (96.red-83-59-163.dynamicip.rima-tde.net. [83.59.163.96]) by smtp.gmail.com with ESMTPSA id b202sm4618697wmd.15.2020.03.17.09.36.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Mar 2020 09:36:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NItFYL8c54YYDddOlQi5GBmfNL8EWnzRmo0PxaX26Jw=; b=SispohgcpITD348AsBDCywRpN9DhGtbO/q1sggCMp0jQcDeZkbH+XOVtxreCKEBAXZ yjz4CJJFNRJHV7d/RQNnZMVlq/VLJOCAO7Q7GM+O+2WOoEPemXlvjX2O297VAG2WVcjy AP3n9KdjbYtMvQtwuqnakq67kx8U6we21+YPGfoVYyS2vr0GLIbbniYecAMKSaMlZUJ2 sMKawTn9CJqqAtafPdY28rjt7qyGNBRKbX8G/7iKuZagTUveUnLr6YtzqfoFbcQtmEqj VTNTkKNYJZ4DI/nXXUdysc9mXeJq2+hocgwVgp7xmD4uw7CyCGWfVhTkxt0d7a3gtbjY 9JDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=NItFYL8c54YYDddOlQi5GBmfNL8EWnzRmo0PxaX26Jw=; b=gnwTmxl8yWfYW+yB5/kdFzdF9J+U/20gr2PL/oLzMlRPDAxuFp0Z9jptFzZmuIqnF5 D7d2r+zpdGyGjV+Q8Jgm3I+x9/QFUl1KYXsvpetCo1J8YZPF5hzZwnewKMLwuip8IwYL A/kjxeBKRT3SGoa25oOyi72updB2Ow8aDrqjOszTI8K4vWrGXXBeO/fwO5rNUM9VZFVE LbaXJaDO2nJH06L9X1+qA06F6z+k5Wib1QgOZXFGAy4UFNFMQ02FYDcI27IUwa8tylDo Kt6botmN522A8yd2pby4FdpFYDfgtEMjPL9Yww2dElPXM2qLbCPxi2WZC7rq5qKVrAWd 5Evw== X-Gm-Message-State: ANhLgQ15r2qXJOnJVzLw0pOxoz3Oe4FQh4iX8YsomiLmis2b+Q3b9jzA 7X9JbcJ88yNgs0rhaDIcdeIf/46V X-Google-Smtp-Source: ADFU+vv1dRd462ZgA7/LvX0NpuTMNdYo/Shf79FRWEeEa7Jb90J/90KV1N9A3q3YiwZx26Y8ZzkPyA== X-Received: by 2002:a1c:7214:: with SMTP id n20mr178665wmc.24.1584462982416; Tue, 17 Mar 2020 09:36:22 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 03/13] target/rx: TCG translation Date: Tue, 17 Mar 2020 17:36:06 +0100 Message-Id: <20200317163616.30027-4-f4bug@amsat.org> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200317163616.30027-1-f4bug@amsat.org> References: <20200317163616.30027-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::331 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yoshinori Sato , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Yoshinori Sato This part only supported RXv1 instructions. Instruction manual: https://www.renesas.com/us/en/doc/products/mpumcu/doc/rx_family/r01us0032= ej0120_rxsm.pdf Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Yoshinori Sato Signed-off-by: Richard Henderson Message-Id: <20200224141923.82118-5-ysato@users.sourceforge.jp> Acked-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/rx/insns.decode | 621 ++++++++++ target/rx/translate.c | 2432 +++++++++++++++++++++++++++++++++++++++ target/rx/Makefile.objs | 12 + 3 files changed, 3065 insertions(+) create mode 100644 target/rx/insns.decode create mode 100644 target/rx/translate.c create mode 100644 target/rx/Makefile.objs diff --git a/target/rx/insns.decode b/target/rx/insns.decode new file mode 100644 index 0000000000..232a61fc8e --- /dev/null +++ b/target/rx/insns.decode @@ -0,0 +1,621 @@ +# +# Renesas RX instruction decode definitions. +# +# Copyright (c) 2019 Richard Henderson +# Copyright (c) 2019 Yoshinori Sato +# +# This library is free software; you can redistribute it and/or +# modify it under the terms of the GNU Lesser General Public +# License as published by the Free Software Foundation; either +# version 2 of the License, or (at your option) any later version. +# +# This library is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU +# Lesser General Public License for more details. +# +# You should have received a copy of the GNU Lesser General Public +# License along with this library; if not, see . +# + +&bcnd cd dsp sz +&jdsp dsp sz +&jreg rs +&rr rd rs +&ri rd imm +&rrr rd rs rs2 +&rri rd imm rs2 +&rm rd rs ld mi +&mi rs ld mi imm +&mr rs ld mi rs2 +&mcnd ld sz rd cd +######## +%b1_bdsp 24:3 !function=3Dbdsp_s + +@b1_bcnd_s .... cd:1 ... &bcnd dsp=3D%b1_bdsp sz=3D1 +@b1_bra_s .... .... &jdsp dsp=3D%b1_bdsp sz=3D1 + +%b2_r_0 16:4 +%b2_li_2 18:2 !function=3Dli +%b2_li_8 24:2 !function=3Dli +%b2_dsp5_3 23:4 19:1 + +@b2_rds .... .... .... rd:4 &rr rs=3D%b2_r_0 +@b2_rds_li .... .... .... rd:4 &rri rs2=3D%b2_r_0 imm=3D%b2_li_8 +@b2_rds_uimm4 .... .... imm:4 rd:4 &rri rs2=3D%b2_r_0 +@b2_rs2_uimm4 .... .... imm:4 rs2:4 &rri rd=3D0 +@b2_rds_imm5 .... ... imm:5 rd:4 &rri rs2=3D%b2_r_0 +@b2_rd_rs_li .... .... rs2:4 rd:4 &rri imm=3D%b2_li_8 +@b2_rd_ld_ub .... .. ld:2 rs:4 rd:4 &rm mi=3D4 +@b2_ld_imm3 .... .. ld:2 rs:4 . imm:3 &mi mi=3D4 +@b2_bcnd_b .... cd:4 dsp:s8 &bcnd sz=3D2 +@b2_bra_b .... .... dsp:s8 &jdsp sz=3D2 + +######## + +%b3_r_0 8:4 +%b3_li_10 18:2 !function=3Dli +%b3_dsp5_8 23:1 16:4 +%b3_bdsp 8:s8 16:8 + +@b3_rd_rs .... .... .... .... rs:4 rd:4 &rr +@b3_rs_rd .... .... .... .... rd:4 rs:4 &rr +@b3_rd_li .... .... .... .... .... rd:4 \ + &rri rs2=3D%b3_r_0 imm=3D%b3_li_10 +@b3_rd_ld .... .... mi:2 .... ld:2 rs:4 rd:4 &rm +@b3_rd_ld_ub .... .... .... .. ld:2 rs:4 rd:4 &rm mi=3D4 +@b3_rd_ld_ul .... .... .... .. ld:2 rs:4 rd:4 &rm mi=3D2 +@b3_rd_rs_rs2 .... .... .... rd:4 rs:4 rs2:4 &rrr +@b3_rds_imm5 .... .... ....... imm:5 rd:4 &rri rs2=3D%b3_r_0 +@b3_rd_rs_imm5 .... .... ... imm:5 rs2:4 rd:4 &rri +@b3_bcnd_w .... ... cd:1 .... .... .... .... &bcnd dsp=3D%b3_bdsp sz=3D3 +@b3_bra_w .... .... .... .... .... .... &jdsp dsp=3D%b3_bdsp sz=3D3 +@b3_ld_rd_rs .... .... .... .. ld:2 rs:4 rd:4 &rm mi=3D0 +@b3_sz_ld_rd_cd .... .... .... sz:2 ld:2 rd:4 cd:4 &mcnd + +######## + +%b4_li_18 18:2 !function=3Dli +%b4_dsp_16 0:s8 8:8 +%b4_bdsp 0:s8 8:8 16:8 + +@b4_rd_ldmi .... .... mi:2 .... ld:2 .... .... rs:4 rd:4 &rm +@b4_bra_a .... .... .... .... .... .... .... .... \ + &jdsp dsp=3D%b4_bdsp sz=3D4 +######## +# ABS rd +ABS_rr 0111 1110 0010 .... @b2_rds +# ABS rs, rd +ABS_rr 1111 1100 0000 1111 .... .... @b3_rd_rs + +# ADC #imm, rd +ADC_ir 1111 1101 0111 ..00 0010 .... @b3_rd_li +# ADC rs, rd +ADC_rr 1111 1100 0000 1011 .... .... @b3_rd_rs +# ADC dsp[rs].l, rd +# Note only mi=3D=3D2 allowed. +ADC_mr 0000 0110 ..10 00.. 0000 0010 .... .... @b4_rd_ldmi + +# ADD #uimm4, rd +ADD_irr 0110 0010 .... .... @b2_rds_uimm4 +# ADD #imm, rs, rd +ADD_irr 0111 00.. .... .... @b2_rd_rs_li +# ADD dsp[rs].ub, rd +# ADD rs, rd +ADD_mr 0100 10.. .... .... @b2_rd_ld_ub +# ADD dsp[rs], rd +ADD_mr 0000 0110 ..00 10.. .... .... @b3_rd_ld +# ADD rs, rs2, rd +ADD_rrr 1111 1111 0010 .... .... .... @b3_rd_rs_rs2 + +# AND #uimm4, rd +AND_ir 0110 0100 .... .... @b2_rds_uimm4 +# AND #imm, rd +AND_ir 0111 01.. 0010 .... @b2_rds_li +# AND dsp[rs].ub, rd +# AND rs, rd +AND_mr 0101 00.. .... .... @b2_rd_ld_ub +# AND dsp[rs], rd +AND_mr 0000 0110 ..01 00.. .... .... @b3_rd_ld +# AND rs, rs2, rd +AND_rrr 1111 1111 0100 .... .... .... @b3_rd_rs_rs2 + +# BCLR #imm, dsp[rd] +BCLR_im 1111 00.. .... 1... @b2_ld_imm3 +# BCLR #imm, rs +BCLR_ir 0111 101. .... .... @b2_rds_imm5 +# BCLR rs, rd +# BCLR rs, dsp[rd] +{ + BCLR_rr 1111 1100 0110 0111 .... .... @b3_rs_rd + BCLR_rm 1111 1100 0110 01.. .... .... @b3_rd_ld_ub +} + +# BCnd.s dsp +BCnd 0001 .... @b1_bcnd_s +# BRA.b dsp +# BCnd.b dsp +{ + BRA 0010 1110 .... .... @b2_bra_b + BCnd 0010 .... .... .... @b2_bcnd_b +} + +# BCnd.w dsp +BCnd 0011 101 . .... .... .... .... @b3_bcnd_w + +# BNOT #imm, dsp[rd] +# BMCnd #imm, dsp[rd] +{ + BNOT_im 1111 1100 111 imm:3 ld:2 rs:4 1111 + BMCnd_im 1111 1100 111 imm:3 ld:2 rd:4 cd:4 +} + +# BNOT #imm, rd +# BMCnd #imm, rd +{ + BNOT_ir 1111 1101 111 imm:5 1111 rd:4 + BMCnd_ir 1111 1101 111 imm:5 cd:4 rd:4 +} + +# BNOT rs, rd +# BNOT rs, dsp[rd] +{ + BNOT_rr 1111 1100 0110 1111 .... .... @b3_rs_rd + BNOT_rm 1111 1100 0110 11.. .... .... @b3_rd_ld_ub +} + +# BRA.s dsp +BRA 0000 1 ... @b1_bra_s +# BRA.w dsp +BRA 0011 1000 .... .... .... .... @b3_bra_w +# BRA.a dsp +BRA 0000 0100 .... .... .... .... .... .... @b4_bra_a +# BRA.l rs +BRA_l 0111 1111 0100 rd:4 + +BRK 0000 0000 + +# BSET #imm, dsp[rd] +BSET_im 1111 00.. .... 0... @b2_ld_imm3 +# BSET #imm, rd +BSET_ir 0111 100. .... .... @b2_rds_imm5 +# BSET rs, rd +# BSET rs, dsp[rd] +{ + BSET_rr 1111 1100 0110 0011 .... .... @b3_rs_rd + BSET_rm 1111 1100 0110 00.. .... .... @b3_rd_ld_ub +} + +# BSR.w dsp +BSR 0011 1001 .... .... .... .... @b3_bra_w +# BSR.a dsp +BSR 0000 0101 .... .... .... .... .... .... @b4_bra_a +# BSR.l rs +BSR_l 0111 1111 0101 rd:4 + +# BSET #imm, dsp[rd] +BTST_im 1111 01.. .... 0... @b2_ld_imm3 +# BSET #imm, rd +BTST_ir 0111 110. .... .... @b2_rds_imm5 +# BSET rs, rd +# BSET rs, dsp[rd] +{ + BTST_rr 1111 1100 0110 1011 .... .... @b3_rs_rd + BTST_rm 1111 1100 0110 10.. .... .... @b3_rd_ld_ub +} + +# CLRSPW psw +CLRPSW 0111 1111 1011 cb:4 + +# CMP #uimm4, rs2 +CMP_ir 0110 0001 .... .... @b2_rs2_uimm4 +# CMP #uimm8, rs2 +CMP_ir 0111 0101 0101 rs2:4 imm:8 &rri rd=3D0 +# CMP #imm, rs2 +CMP_ir 0111 01.. 0000 rs2:4 &rri imm=3D%b2_li_8 rd=3D0 +# CMP dsp[rs].ub, rs2 +# CMP rs, rs2 +CMP_mr 0100 01.. .... .... @b2_rd_ld_ub +# CMP dsp[rs], rs2 +CMP_mr 0000 0110 ..00 01.. .... .... @b3_rd_ld + +# DIV #imm, rd +DIV_ir 1111 1101 0111 ..00 1000 .... @b3_rd_li +# DIV dsp[rs].ub, rd +# DIV rs, rd +DIV_mr 1111 1100 0010 00.. .... .... @b3_rd_ld_ub +# DIV dsp[rs], rd +DIV_mr 0000 0110 ..10 00.. 0000 1000 .... .... @b4_rd_ldmi + +# DIVU #imm, rd +DIVU_ir 1111 1101 0111 ..00 1001 .... @b3_rd_li +# DIVU dsp[rs].ub, rd +# DIVU rs, rd +DIVU_mr 1111 1100 0010 01.. .... .... @b3_rd_ld_ub +# DIVU dsp[rs], rd +DIVU_mr 0000 0110 ..10 00.. 0000 1001 .... .... @b4_rd_ldmi + +# EMUL #imm, rd +EMUL_ir 1111 1101 0111 ..00 0110 .... @b3_rd_li +# EMUL dsp[rs].ub, rd +# EMUL rs, rd +EMUL_mr 1111 1100 0001 10.. .... .... @b3_rd_ld_ub +# EMUL dsp[rs], rd +EMUL_mr 0000 0110 ..10 00.. 0000 0110 .... .... @b4_rd_ldmi + +# EMULU #imm, rd +EMULU_ir 1111 1101 0111 ..00 0111 .... @b3_rd_li +# EMULU dsp[rs].ub, rd +# EMULU rs, rd +EMULU_mr 1111 1100 0001 11.. .... .... @b3_rd_ld_ub +# EMULU dsp[rs], rd +EMULU_mr 0000 0110 ..10 00.. 0000 0111 .... .... @b4_rd_ldmi + +# FADD #imm, rd +FADD_ir 1111 1101 0111 0010 0010 rd:4 +# FADD rs, rd +# FADD dsp[rs], rd +FADD_mr 1111 1100 1000 10.. .... .... @b3_rd_ld_ul + +# FCMP #imm, rd +FCMP_ir 1111 1101 0111 0010 0001 rd:4 +# FCMP rs, rd +# FCMP dsp[rs], rd +FCMP_mr 1111 1100 1000 01.. .... .... @b3_rd_ld_ul + +# FDIV #imm, rd +FDIV_ir 1111 1101 0111 0010 0100 rd:4 +# FDIV rs, rd +# FDIV dsp[rs], rd +FDIV_mr 1111 1100 1001 00.. .... .... @b3_rd_ld_ul + +# FMUL #imm, rd +FMUL_ir 1111 1101 0111 0010 0011 rd:4 +# FMUL rs, rd +# FMUL dsp[rs], rd +FMUL_mr 1111 1100 1000 11.. .... .... @b3_rd_ld_ul + +# FSUB #imm, rd +FSUB_ir 1111 1101 0111 0010 0000 rd:4 +# FSUB rs, rd +# FSUB dsp[rs], rd +FSUB_mr 1111 1100 1000 00.. .... .... @b3_rd_ld_ul + +# FTOI rs, rd +# FTOI dsp[rs], rd +FTOI 1111 1100 1001 01.. .... .... @b3_rd_ld_ul + +# INT #uimm8 +INT 0111 0101 0110 0000 imm:8 + +# ITOF dsp[rs].ub, rd +# ITOF rs, rd +ITOF 1111 1100 0100 01.. .... .... @b3_rd_ld_ub +# ITOF dsp[rs], rd +ITOF 0000 0110 ..10 00.. 0001 0001 .... .... @b4_rd_ldmi + +# JMP rs +JMP 0111 1111 0000 rs:4 &jreg +# JSR rs +JSR 0111 1111 0001 rs:4 &jreg + +# MACHI rs, rs2 +MACHI 1111 1101 0000 0100 rs:4 rs2:4 +# MACLO rs, rs2 +MACLO 1111 1101 0000 0101 rs:4 rs2:4 + +# MAX #imm, rd +MAX_ir 1111 1101 0111 ..00 0100 .... @b3_rd_li +# MAX dsp[rs].ub, rd +# MAX rs, rd +MAX_mr 1111 1100 0001 00.. .... .... @b3_rd_ld_ub +# MAX dsp[rs], rd +MAX_mr 0000 0110 ..10 00.. 0000 0100 .... .... @b4_rd_ldmi + +# MIN #imm, rd +MIN_ir 1111 1101 0111 ..00 0101 .... @b3_rd_li +# MIN dsp[rs].ub, rd +# MIN rs, rd +MIN_mr 1111 1100 0001 01.. .... .... @b3_rd_ld_ub +# MIN dsp[rs], rd +MIN_mr 0000 0110 ..10 00.. 0000 0101 .... .... @b4_rd_ldmi + +# MOV.b rs, dsp5[rd] +MOV_rm 1000 0 .... rd:3 . rs:3 dsp=3D%b2_dsp5_3 sz=3D0 +# MOV.w rs, dsp5[rd] +MOV_rm 1001 0 .... rd:3 . rs:3 dsp=3D%b2_dsp5_3 sz=3D1 +# MOV.l rs, dsp5[rd] +MOV_rm 1010 0 .... rd:3 . rs:3 dsp=3D%b2_dsp5_3 sz=3D2 +# MOV.b dsp5[rs], rd +MOV_mr 1000 1 .... rs:3 . rd:3 dsp=3D%b2_dsp5_3 sz=3D0 +# MOV.w dsp5[rs], rd +MOV_mr 1001 1 .... rs:3 . rd:3 dsp=3D%b2_dsp5_3 sz=3D1 +# MOV.l dsp5[rs], rd +MOV_mr 1010 1 .... rs:3 . rd:3 dsp=3D%b2_dsp5_3 sz=3D2 +# MOV.l #uimm4, rd +MOV_ir 0110 0110 imm:4 rd:4 +# MOV.b #imm8, dsp5[rd] +MOV_im 0011 1100 . rd:3 .... imm:8 sz=3D0 dsp=3D%b3_dsp5_8 +# MOV.w #imm8, dsp5[rd] +MOV_im 0011 1101 . rd:3 .... imm:8 sz=3D1 dsp=3D%b3_dsp5_8 +# MOV.l #imm8, dsp5[rd] +MOV_im 0011 1110 . rd:3 .... imm:8 sz=3D2 dsp=3D%b3_dsp5_8 +# MOV.l #imm8, rd +MOV_ir 0111 0101 0100 rd:4 imm:8 +# MOV.l #mm8, rd +MOV_ir 1111 1011 rd:4 .. 10 imm=3D%b2_li_2 +# MOV. #imm, [rd] +MOV_im 1111 1000 rd:4 .. sz:2 dsp=3D0 imm=3D%b2_li_2 +# MOV. #imm, dsp8[rd] +MOV_im 1111 1001 rd:4 .. sz:2 dsp:8 imm=3D%b3_li_10 +# MOV. #imm, dsp16[rd] +MOV_im 1111 1010 rd:4 .. sz:2 .... .... .... .... \ + imm=3D%b4_li_18 dsp=3D%b4_dsp_16 +# MOV. [ri,rb], rd +MOV_ar 1111 1110 01 sz:2 ri:4 rb:4 rd:4 +# MOV. rs, [ri,rb] +MOV_ra 1111 1110 00 sz:2 ri:4 rb:4 rs:4 +# Note ldd=3D3 and lds=3D3 indicate register src or dst +# MOV.b rs, rd +# MOV.b rs, dsp[rd] +# MOV.b dsp[rs], rd +# MOV.b dsp[rs], dsp[rd] +MOV_mm 1100 ldd:2 lds:2 rs:4 rd:4 sz=3D0 +# MOV.w rs, rd +# MOV.w rs, dsp[rd] +# MOV.w dsp[rs], rd +# MOV.w dsp[rs], dsp[rd] +MOV_mm 1101 ldd:2 lds:2 rs:4 rd:4 sz=3D1 +# MOV.l rs, rd +# MOV.l rs, dsp[rd] +# MOV.l dsp[rs], rd +# MOV.l dsp[rs], dsp[rd] +MOV_mm 1110 ldd:2 lds:2 rs:4 rd:4 sz=3D2 +# MOV.l rs, [rd+] +# MOV.l rs, [-rd] +MOV_rp 1111 1101 0010 0 ad:1 sz:2 rd:4 rs:4 +# MOV.l [rs+], rd +# MOV.l [-rs], rd +MOV_pr 1111 1101 0010 1 ad:1 sz:2 rd:4 rs:4 + +# MOVU. dsp5[rs], rd +MOVU_mr 1011 sz:1 ... . rs:3 . rd:3 dsp=3D%b2_dsp5_3 +# MOVU. [rs], rd +MOVU_mr 0101 1 sz:1 00 rs:4 rd:4 dsp=3D0 +# MOVU. dsp8[rs], rd +MOVU_mr 0101 1 sz:1 01 rs:4 rd:4 dsp:8 +# MOVU. dsp16[rs], rd +MOVU_mr 0101 1 sz:1 10 rs:4 rd:4 .... .... .... .... dsp=3D%b4_dsp_16 +# MOVU. rs, rd +MOVU_rr 0101 1 sz:1 11 rs:4 rd:4 +# MOVU. [ri, rb], rd +MOVU_ar 1111 1110 110 sz:1 ri:4 rb:4 rd:4 +# MOVU. [rs+], rd +MOVU_pr 1111 1101 0011 1 ad:1 0 sz:1 rd:4 rs:4 + +# MUL #uimm4, rd +MUL_ir 0110 0011 .... .... @b2_rds_uimm4 +# MUL #imm4, rd +MUL_ir 0111 01.. 0001 .... @b2_rds_li +# MUL dsp[rs].ub, rd +# MUL rs, rd +MUL_mr 0100 11.. .... .... @b2_rd_ld_ub +# MUL dsp[rs], rd +MUL_mr 0000 0110 ..00 11.. .... .... @b3_rd_ld +# MOV rs, rs2, rd +MUL_rrr 1111 1111 0011 .... .... .... @b3_rd_rs_rs2 + +# MULHI rs, rs2 +MULHI 1111 1101 0000 0000 rs:4 rs2:4 +# MULLO rs, rs2 +MULLO 1111 1101 0000 0001 rs:4 rs2:4 + +# MVFACHI rd +MVFACHI 1111 1101 0001 1111 0000 rd:4 +# MVFACMI rd +MVFACMI 1111 1101 0001 1111 0010 rd:4 + +# MVFC cr, rd +MVFC 1111 1101 0110 1010 cr:4 rd:4 + +# MVTACHI rs +MVTACHI 1111 1101 0001 0111 0000 rs:4 +# MVTACLO rs +MVTACLO 1111 1101 0001 0111 0001 rs:4 + +# MVTC #imm, cr +MVTC_i 1111 1101 0111 ..11 0000 cr:4 imm=3D%b3_li_10 +# MVTC rs, cr +MVTC_r 1111 1101 0110 1000 rs:4 cr:4 + +# MVTIPL #imm +MVTIPL 0111 0101 0111 0000 0000 imm:4 + +# NEG rd +NEG_rr 0111 1110 0001 .... @b2_rds +# NEG rs, rd +NEG_rr 1111 1100 0000 0111 .... .... @b3_rd_rs + +NOP 0000 0011 + +# NOT rd +NOT_rr 0111 1110 0000 .... @b2_rds +# NOT rs, rd +NOT_rr 1111 1100 0011 1011 .... .... @b3_rd_rs + +# OR #uimm4, rd +OR_ir 0110 0101 .... .... @b2_rds_uimm4 +# OR #imm, rd +OR_ir 0111 01.. 0011 .... @b2_rds_li +# OR dsp[rs].ub, rd +# OR rs, rd +OR_mr 0101 01.. .... .... @b2_rd_ld_ub +# OR dsp[rs], rd +OR_mr 0000 0110 .. 0101 .. .... .... @b3_rd_ld +# OR rs, rs2, rd +OR_rrr 1111 1111 0101 .... .... .... @b3_rd_rs_rs2 + +# POP cr +POPC 0111 1110 1110 cr:4 +# POP rd-rd2 +POPM 0110 1111 rd:4 rd2:4 + +# POP rd +# PUSH. rs +{ + POP 0111 1110 1011 rd:4 + PUSH_r 0111 1110 10 sz:2 rs:4 +} +# PUSH. dsp[rs] +PUSH_m 1111 01 ld:2 rs:4 10 sz:2 +# PUSH cr +PUSHC 0111 1110 1100 cr:4 +# PUSHM rs-rs2 +PUSHM 0110 1110 rs:4 rs2:4 + +# RACW #imm +RACW 1111 1101 0001 1000 000 imm:1 0000 + +# REVL rs,rd +REVL 1111 1101 0110 0111 .... .... @b3_rd_rs +# REVW rs,rd +REVW 1111 1101 0110 0101 .... .... @b3_rd_rs + +# SMOVF +# RPMA. +{ + SMOVF 0111 1111 1000 1111 + RMPA 0111 1111 1000 11 sz:2 +} + +# ROLC rd +ROLC 0111 1110 0101 .... @b2_rds +# RORC rd +RORC 0111 1110 0100 .... @b2_rds + +# ROTL #imm, rd +ROTL_ir 1111 1101 0110 111. .... .... @b3_rds_imm5 +# ROTL rs, rd +ROTL_rr 1111 1101 0110 0110 .... .... @b3_rd_rs + +# ROTR #imm, rd +ROTR_ir 1111 1101 0110 110. .... .... @b3_rds_imm5 +# ROTR #imm, rd +ROTR_rr 1111 1101 0110 0100 .... .... @b3_rd_rs + +# ROUND rs,rd +# ROUND dsp[rs],rd +ROUND 1111 1100 1001 10 .. .... .... @b3_ld_rd_rs + +RTE 0111 1111 1001 0101 + +RTFI 0111 1111 1001 0100 + +RTS 0000 0010 + +# RTSD #imm +RTSD_i 0110 0111 imm:8 +# RTSD #imm, rd-rd2 +RTSD_irr 0011 1111 rd:4 rd2:4 imm:8 + +# SAT rd +SAT 0111 1110 0011 .... @b2_rds +# SATR +SATR 0111 1111 1001 0011 + +# SBB rs, rd +SBB_rr 1111 1100 0000 0011 .... .... @b3_rd_rs +# SBB dsp[rs].l, rd +# Note only mi=3D=3D2 allowed. +SBB_mr 0000 0110 ..10 00.. 0000 0000 .... .... @b4_rd_ldmi + +# SCCnd dsp[rd] +# SCCnd rd +SCCnd 1111 1100 1101 .... .... .... @b3_sz_ld_rd_cd + +# SETPSW psw +SETPSW 0111 1111 1010 cb:4 + +# SHAR #imm, rd +SHAR_irr 0110 101. .... .... @b2_rds_imm5 +# SHAR #imm, rs, rd +SHAR_irr 1111 1101 101. .... .... .... @b3_rd_rs_imm5 +# SHAR rs, rd +SHAR_rr 1111 1101 0110 0001 .... .... @b3_rd_rs + +# SHLL #imm, rd +SHLL_irr 0110 110. .... .... @b2_rds_imm5 +# SHLL #imm, rs, rd +SHLL_irr 1111 1101 110. .... .... .... @b3_rd_rs_imm5 +# SHLL rs, rd +SHLL_rr 1111 1101 0110 0010 .... .... @b3_rd_rs + +# SHLR #imm, rd +SHLR_irr 0110 100. .... .... @b2_rds_imm5 +# SHLR #imm, rs, rd +SHLR_irr 1111 1101 100. .... .... .... @b3_rd_rs_imm5 +# SHLR rs, rd +SHLR_rr 1111 1101 0110 0000 .... .... @b3_rd_rs + +# SMOVB +# SSTR. +{ + SMOVB 0111 1111 1000 1011 + SSTR 0111 1111 1000 10 sz:2 +} + +# STNZ #imm, rd +STNZ 1111 1101 0111 ..00 1111 .... @b3_rd_li +# STZ #imm, rd +STZ 1111 1101 0111 ..00 1110 .... @b3_rd_li + +# SUB #uimm4, rd +SUB_ir 0110 0000 .... .... @b2_rds_uimm4 +# SUB dsp[rs].ub, rd +# SUB rs, rd +SUB_mr 0100 00.. .... .... @b2_rd_ld_ub +# SUB dsp[rs], rd +SUB_mr 0000 0110 ..00 00.. .... .... @b3_rd_ld +# SUB rs, rs2, rd +SUB_rrr 1111 1111 0000 .... .... .... @b3_rd_rs_rs2 + +# SCMPU +# SUNTIL. +{ + SCMPU 0111 1111 1000 0011 + SUNTIL 0111 1111 1000 00 sz:2 +} + +# SMOVU +# SWHILE. +{ + SMOVU 0111 1111 1000 0111 + SWHILE 0111 1111 1000 01 sz:2 +} + +# TST #imm, rd +TST_ir 1111 1101 0111 ..00 1100 .... @b3_rd_li +# TST dsp[rs].ub, rd +# TST rs, rd +TST_mr 1111 1100 0011 00.. .... .... @b3_rd_ld_ub +# TST dsp[rs], rd +TST_mr 0000 0110 ..10 00.. 0000 1100 .... .... @b4_rd_ldmi + +WAIT 0111 1111 1001 0110 + +# XCHG rs, rd +# XCHG dsp[rs].ub, rd +{ + XCHG_rr 1111 1100 0100 0011 .... .... @b3_rd_rs + XCHG_mr 1111 1100 0100 00.. .... .... @b3_rd_ld_ub +} +# XCHG dsp[rs], rd +XCHG_mr 0000 0110 ..10 00.. 0001 0000 .... .... @b4_rd_ldmi + +# XOR #imm, rd +XOR_ir 1111 1101 0111 ..00 1101 .... @b3_rd_li +# XOR dsp[rs].ub, rd +# XOR rs, rd +XOR_mr 1111 1100 0011 01.. .... .... @b3_rd_ld_ub +# XOR dsp[rs], rd +XOR_mr 0000 0110 ..10 00.. 0000 1101 .... .... @b4_rd_ldmi diff --git a/target/rx/translate.c b/target/rx/translate.c new file mode 100644 index 0000000000..6b52424d0f --- /dev/null +++ b/target/rx/translate.c @@ -0,0 +1,2432 @@ +/* + * RX translation + * + * Copyright (c) 2019 Yoshinori Sato + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/bswap.h" +#include "qemu/qemu-print.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "tcg/tcg-op.h" +#include "exec/cpu_ldst.h" +#include "exec/helper-proto.h" +#include "exec/helper-gen.h" +#include "exec/translator.h" +#include "trace-tcg.h" +#include "exec/log.h" + +typedef struct DisasContext { + DisasContextBase base; + CPURXState *env; + uint32_t pc; +} DisasContext; + +typedef struct DisasCompare { + TCGv value; + TCGv temp; + TCGCond cond; +} DisasCompare; + +const char rx_crname[][6] =3D { + "psw", "pc", "usp", "fpsw", "", "", "", "", + "bpsw", "bpc", "isp", "fintv", "intb", "", "", "", +}; + +/* Target-specific values for dc->base.is_jmp. */ +#define DISAS_JUMP DISAS_TARGET_0 +#define DISAS_UPDATE DISAS_TARGET_1 +#define DISAS_EXIT DISAS_TARGET_2 + +/* global register indexes */ +static TCGv cpu_regs[16]; +static TCGv cpu_psw_o, cpu_psw_s, cpu_psw_z, cpu_psw_c; +static TCGv cpu_psw_i, cpu_psw_pm, cpu_psw_u, cpu_psw_ipl; +static TCGv cpu_usp, cpu_fpsw, cpu_bpsw, cpu_bpc, cpu_isp; +static TCGv cpu_fintv, cpu_intb, cpu_pc; +static TCGv_i64 cpu_acc; + +#define cpu_sp cpu_regs[0] + +#include "exec/gen-icount.h" + +/* decoder helper */ +static uint32_t decode_load_bytes(DisasContext *ctx, uint32_t insn, + int i, int n) +{ + while (++i <=3D n) { + uint8_t b =3D cpu_ldub_code(ctx->env, ctx->base.pc_next++); + insn |=3D b << (32 - i * 8); + } + return insn; +} + +static uint32_t li(DisasContext *ctx, int sz) +{ + int32_t tmp, addr; + CPURXState *env =3D ctx->env; + addr =3D ctx->base.pc_next; + + tcg_debug_assert(sz < 4); + switch (sz) { + case 1: + ctx->base.pc_next +=3D 1; + return cpu_ldsb_code(env, addr); + case 2: + ctx->base.pc_next +=3D 2; + return cpu_ldsw_code(env, addr); + case 3: + ctx->base.pc_next +=3D 3; + tmp =3D cpu_ldsb_code(env, addr + 2) << 16; + tmp |=3D cpu_lduw_code(env, addr) & 0xffff; + return tmp; + case 0: + ctx->base.pc_next +=3D 4; + return cpu_ldl_code(env, addr); + } + return 0; +} + +static int bdsp_s(DisasContext *ctx, int d) +{ + /* + * 0 -> 8 + * 1 -> 9 + * 2 -> 10 + * 3 -> 3 + * : + * 7 -> 7 + */ + if (d < 3) { + d +=3D 8; + } + return d; +} + +/* Include the auto-generated decoder. */ +#include "decode.inc.c" + +void rx_cpu_dump_state(CPUState *cs, FILE *f, int flags) +{ + RXCPU *cpu =3D RXCPU(cs); + CPURXState *env =3D &cpu->env; + int i; + uint32_t psw; + + psw =3D rx_cpu_pack_psw(env); + qemu_fprintf(f, "pc=3D0x%08x psw=3D0x%08x\n", + env->pc, psw); + for (i =3D 0; i < 16; i +=3D 4) { + qemu_fprintf(f, "r%d=3D0x%08x r%d=3D0x%08x r%d=3D0x%08x r%d=3D0x%0= 8x\n", + i, env->regs[i], i + 1, env->regs[i + 1], + i + 2, env->regs[i + 2], i + 3, env->regs[i + 3]); + } +} + +static bool use_goto_tb(DisasContext *dc, target_ulong dest) +{ + if (unlikely(dc->base.singlestep_enabled)) { + return false; + } else { + return true; + } +} + +static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest) +{ + if (use_goto_tb(dc, dest)) { + tcg_gen_goto_tb(n); + tcg_gen_movi_i32(cpu_pc, dest); + tcg_gen_exit_tb(dc->base.tb, n); + } else { + tcg_gen_movi_i32(cpu_pc, dest); + if (dc->base.singlestep_enabled) { + gen_helper_debug(cpu_env); + } else { + tcg_gen_lookup_and_goto_ptr(); + } + } + dc->base.is_jmp =3D DISAS_NORETURN; +} + +/* generic load wrapper */ +static inline void rx_gen_ld(unsigned int size, TCGv reg, TCGv mem) +{ + tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_SIGN | MO_TE); +} + +/* unsigned load wrapper */ +static inline void rx_gen_ldu(unsigned int size, TCGv reg, TCGv mem) +{ + tcg_gen_qemu_ld_i32(reg, mem, 0, size | MO_TE); +} + +/* generic store wrapper */ +static inline void rx_gen_st(unsigned int size, TCGv reg, TCGv mem) +{ + tcg_gen_qemu_st_i32(reg, mem, 0, size | MO_TE); +} + +/* [ri, rb] */ +static inline void rx_gen_regindex(DisasContext *ctx, TCGv mem, + int size, int ri, int rb) +{ + tcg_gen_shli_i32(mem, cpu_regs[ri], size); + tcg_gen_add_i32(mem, mem, cpu_regs[rb]); +} + +/* dsp[reg] */ +static inline TCGv rx_index_addr(DisasContext *ctx, TCGv mem, + int ld, int size, int reg) +{ + uint32_t dsp; + + tcg_debug_assert(ld < 3); + switch (ld) { + case 0: + return cpu_regs[reg]; + case 1: + dsp =3D cpu_ldub_code(ctx->env, ctx->base.pc_next) << size; + tcg_gen_addi_i32(mem, cpu_regs[reg], dsp); + ctx->base.pc_next +=3D 1; + return mem; + case 2: + dsp =3D cpu_lduw_code(ctx->env, ctx->base.pc_next) << size; + tcg_gen_addi_i32(mem, cpu_regs[reg], dsp); + ctx->base.pc_next +=3D 2; + return mem; + } + return NULL; +} + +static inline MemOp mi_to_mop(unsigned mi) +{ + static const MemOp mop[5] =3D { MO_SB, MO_SW, MO_UL, MO_UW, MO_UB }; + tcg_debug_assert(mi < 5); + return mop[mi]; +} + +/* load source operand */ +static inline TCGv rx_load_source(DisasContext *ctx, TCGv mem, + int ld, int mi, int rs) +{ + TCGv addr; + MemOp mop; + if (ld < 3) { + mop =3D mi_to_mop(mi); + addr =3D rx_index_addr(ctx, mem, ld, mop & MO_SIZE, rs); + tcg_gen_qemu_ld_i32(mem, addr, 0, mop | MO_TE); + return mem; + } else { + return cpu_regs[rs]; + } +} + +/* Processor mode check */ +static int is_privileged(DisasContext *ctx, int is_exception) +{ + if (FIELD_EX32(ctx->base.tb->flags, PSW, PM)) { + if (is_exception) { + gen_helper_raise_privilege_violation(cpu_env); + } + return 0; + } else { + return 1; + } +} + +/* generate QEMU condition */ +static void psw_cond(DisasCompare *dc, uint32_t cond) +{ + tcg_debug_assert(cond < 16); + switch (cond) { + case 0: /* z */ + dc->cond =3D TCG_COND_EQ; + dc->value =3D cpu_psw_z; + break; + case 1: /* nz */ + dc->cond =3D TCG_COND_NE; + dc->value =3D cpu_psw_z; + break; + case 2: /* c */ + dc->cond =3D TCG_COND_NE; + dc->value =3D cpu_psw_c; + break; + case 3: /* nc */ + dc->cond =3D TCG_COND_EQ; + dc->value =3D cpu_psw_c; + break; + case 4: /* gtu (C& ~Z) =3D=3D 1 */ + case 5: /* leu (C& ~Z) =3D=3D 0 */ + tcg_gen_setcondi_i32(TCG_COND_NE, dc->temp, cpu_psw_z, 0); + tcg_gen_and_i32(dc->temp, dc->temp, cpu_psw_c); + dc->cond =3D (cond =3D=3D 4) ? TCG_COND_NE : TCG_COND_EQ; + dc->value =3D dc->temp; + break; + case 6: /* pz (S =3D=3D 0) */ + dc->cond =3D TCG_COND_GE; + dc->value =3D cpu_psw_s; + break; + case 7: /* n (S =3D=3D 1) */ + dc->cond =3D TCG_COND_LT; + dc->value =3D cpu_psw_s; + break; + case 8: /* ge (S^O)=3D=3D0 */ + case 9: /* lt (S^O)=3D=3D1 */ + tcg_gen_xor_i32(dc->temp, cpu_psw_o, cpu_psw_s); + dc->cond =3D (cond =3D=3D 8) ? TCG_COND_GE : TCG_COND_LT; + dc->value =3D dc->temp; + break; + case 10: /* gt ((S^O)|Z)=3D=3D0 */ + case 11: /* le ((S^O)|Z)=3D=3D1 */ + tcg_gen_xor_i32(dc->temp, cpu_psw_o, cpu_psw_s); + tcg_gen_sari_i32(dc->temp, dc->temp, 31); + tcg_gen_andc_i32(dc->temp, cpu_psw_z, dc->temp); + dc->cond =3D (cond =3D=3D 10) ? TCG_COND_NE : TCG_COND_EQ; + dc->value =3D dc->temp; + break; + case 12: /* o */ + dc->cond =3D TCG_COND_LT; + dc->value =3D cpu_psw_o; + break; + case 13: /* no */ + dc->cond =3D TCG_COND_GE; + dc->value =3D cpu_psw_o; + break; + case 14: /* always true */ + dc->cond =3D TCG_COND_ALWAYS; + dc->value =3D dc->temp; + break; + case 15: /* always false */ + dc->cond =3D TCG_COND_NEVER; + dc->value =3D dc->temp; + break; + } +} + +static void move_from_cr(TCGv ret, int cr, uint32_t pc) +{ + TCGv z =3D tcg_const_i32(0); + switch (cr) { + case 0: /* PSW */ + gen_helper_pack_psw(ret, cpu_env); + break; + case 1: /* PC */ + tcg_gen_movi_i32(ret, pc); + break; + case 2: /* USP */ + tcg_gen_movcond_i32(TCG_COND_NE, ret, + cpu_psw_u, z, cpu_sp, cpu_usp); + break; + case 3: /* FPSW */ + tcg_gen_mov_i32(ret, cpu_fpsw); + break; + case 8: /* BPSW */ + tcg_gen_mov_i32(ret, cpu_bpsw); + break; + case 9: /* BPC */ + tcg_gen_mov_i32(ret, cpu_bpc); + break; + case 10: /* ISP */ + tcg_gen_movcond_i32(TCG_COND_EQ, ret, + cpu_psw_u, z, cpu_sp, cpu_isp); + break; + case 11: /* FINTV */ + tcg_gen_mov_i32(ret, cpu_fintv); + break; + case 12: /* INTB */ + tcg_gen_mov_i32(ret, cpu_intb); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "Unimplement control register %d", = cr); + /* Unimplement registers return 0 */ + tcg_gen_movi_i32(ret, 0); + break; + } + tcg_temp_free(z); +} + +static void move_to_cr(DisasContext *ctx, TCGv val, int cr) +{ + TCGv z; + if (cr >=3D 8 && !is_privileged(ctx, 0)) { + /* Some control registers can only be written in privileged mode. = */ + qemu_log_mask(LOG_GUEST_ERROR, + "disallow control register write %s", rx_crname[cr]); + return; + } + z =3D tcg_const_i32(0); + switch (cr) { + case 0: /* PSW */ + gen_helper_set_psw(cpu_env, val); + break; + /* case 1: to PC not supported */ + case 2: /* USP */ + tcg_gen_mov_i32(cpu_usp, val); + tcg_gen_movcond_i32(TCG_COND_NE, cpu_sp, + cpu_psw_u, z, cpu_usp, cpu_sp); + break; + case 3: /* FPSW */ + gen_helper_set_fpsw(cpu_env, val); + break; + case 8: /* BPSW */ + tcg_gen_mov_i32(cpu_bpsw, val); + break; + case 9: /* BPC */ + tcg_gen_mov_i32(cpu_bpc, val); + break; + case 10: /* ISP */ + tcg_gen_mov_i32(cpu_isp, val); + /* if PSW.U is 0, copy isp to r0 */ + tcg_gen_movcond_i32(TCG_COND_EQ, cpu_sp, + cpu_psw_u, z, cpu_isp, cpu_sp); + break; + case 11: /* FINTV */ + tcg_gen_mov_i32(cpu_fintv, val); + break; + case 12: /* INTB */ + tcg_gen_mov_i32(cpu_intb, val); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "Unimplement control register %d", cr); + break; + } + tcg_temp_free(z); +} + +static void push(TCGv val) +{ + tcg_gen_subi_i32(cpu_sp, cpu_sp, 4); + rx_gen_st(MO_32, val, cpu_sp); +} + +static void pop(TCGv ret) +{ + rx_gen_ld(MO_32, ret, cpu_sp); + tcg_gen_addi_i32(cpu_sp, cpu_sp, 4); +} + +/* mov. rs,dsp5[rd] */ +static bool trans_MOV_rm(DisasContext *ctx, arg_MOV_rm *a) +{ + TCGv mem; + mem =3D tcg_temp_new(); + tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz); + rx_gen_st(a->sz, cpu_regs[a->rs], mem); + tcg_temp_free(mem); + return true; +} + +/* mov. dsp5[rs],rd */ +static bool trans_MOV_mr(DisasContext *ctx, arg_MOV_mr *a) +{ + TCGv mem; + mem =3D tcg_temp_new(); + tcg_gen_addi_i32(mem, cpu_regs[a->rs], a->dsp << a->sz); + rx_gen_ld(a->sz, cpu_regs[a->rd], mem); + tcg_temp_free(mem); + return true; +} + +/* mov.l #uimm4,rd */ +/* mov.l #uimm8,rd */ +/* mov.l #imm,rd */ +static bool trans_MOV_ir(DisasContext *ctx, arg_MOV_ir *a) +{ + tcg_gen_movi_i32(cpu_regs[a->rd], a->imm); + return true; +} + +/* mov. #uimm8,dsp[rd] */ +/* mov. #imm, dsp[rd] */ +static bool trans_MOV_im(DisasContext *ctx, arg_MOV_im *a) +{ + TCGv imm, mem; + imm =3D tcg_const_i32(a->imm); + mem =3D tcg_temp_new(); + tcg_gen_addi_i32(mem, cpu_regs[a->rd], a->dsp << a->sz); + rx_gen_st(a->sz, imm, mem); + tcg_temp_free(imm); + tcg_temp_free(mem); + return true; +} + +/* mov. [ri,rb],rd */ +static bool trans_MOV_ar(DisasContext *ctx, arg_MOV_ar *a) +{ + TCGv mem; + mem =3D tcg_temp_new(); + rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); + rx_gen_ld(a->sz, cpu_regs[a->rd], mem); + tcg_temp_free(mem); + return true; +} + +/* mov. rd,[ri,rb] */ +static bool trans_MOV_ra(DisasContext *ctx, arg_MOV_ra *a) +{ + TCGv mem; + mem =3D tcg_temp_new(); + rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); + rx_gen_st(a->sz, cpu_regs[a->rs], mem); + tcg_temp_free(mem); + return true; +} + +/* mov. dsp[rs],dsp[rd] */ +/* mov. rs,dsp[rd] */ +/* mov. dsp[rs],rd */ +/* mov. rs,rd */ +static bool trans_MOV_mm(DisasContext *ctx, arg_MOV_mm *a) +{ + static void (* const mov[])(TCGv ret, TCGv arg) =3D { + tcg_gen_ext8s_i32, tcg_gen_ext16s_i32, tcg_gen_mov_i32, + }; + TCGv tmp, mem, addr; + if (a->lds =3D=3D 3 && a->ldd =3D=3D 3) { + /* mov. rs,rd */ + mov[a->sz](cpu_regs[a->rd], cpu_regs[a->rs]); + return true; + } + + mem =3D tcg_temp_new(); + if (a->lds =3D=3D 3) { + /* mov. rs,dsp[rd] */ + addr =3D rx_index_addr(ctx, mem, a->ldd, a->sz, a->rs); + rx_gen_st(a->sz, cpu_regs[a->rd], addr); + } else if (a->ldd =3D=3D 3) { + /* mov. dsp[rs],rd */ + addr =3D rx_index_addr(ctx, mem, a->lds, a->sz, a->rs); + rx_gen_ld(a->sz, cpu_regs[a->rd], addr); + } else { + /* mov. dsp[rs],dsp[rd] */ + tmp =3D tcg_temp_new(); + addr =3D rx_index_addr(ctx, mem, a->lds, a->sz, a->rs); + rx_gen_ld(a->sz, tmp, addr); + addr =3D rx_index_addr(ctx, mem, a->ldd, a->sz, a->rd); + rx_gen_st(a->sz, tmp, addr); + tcg_temp_free(tmp); + } + tcg_temp_free(mem); + return true; +} + +/* mov. rs,[rd+] */ +/* mov. rs,[-rd] */ +static bool trans_MOV_rp(DisasContext *ctx, arg_MOV_rp *a) +{ + TCGv val; + val =3D tcg_temp_new(); + tcg_gen_mov_i32(val, cpu_regs[a->rs]); + if (a->ad =3D=3D 1) { + tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); + } + rx_gen_st(a->sz, val, cpu_regs[a->rd]); + if (a->ad =3D=3D 0) { + tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); + } + tcg_temp_free(val); + return true; +} + +/* mov. [rd+],rs */ +/* mov. [-rd],rs */ +static bool trans_MOV_pr(DisasContext *ctx, arg_MOV_pr *a) +{ + TCGv val; + val =3D tcg_temp_new(); + if (a->ad =3D=3D 1) { + tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); + } + rx_gen_ld(a->sz, val, cpu_regs[a->rd]); + if (a->ad =3D=3D 0) { + tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); + } + tcg_gen_mov_i32(cpu_regs[a->rs], val); + tcg_temp_free(val); + return true; +} + +/* movu. dsp5[rs],rd */ +/* movu. dsp[rs],rd */ +static bool trans_MOVU_mr(DisasContext *ctx, arg_MOVU_mr *a) +{ + TCGv mem; + mem =3D tcg_temp_new(); + tcg_gen_addi_i32(mem, cpu_regs[a->rs], a->dsp << a->sz); + rx_gen_ldu(a->sz, cpu_regs[a->rd], mem); + tcg_temp_free(mem); + return true; +} + +/* movu. rs,rd */ +static bool trans_MOVU_rr(DisasContext *ctx, arg_MOVU_rr *a) +{ + static void (* const ext[])(TCGv ret, TCGv arg) =3D { + tcg_gen_ext8u_i32, tcg_gen_ext16u_i32, + }; + ext[a->sz](cpu_regs[a->rd], cpu_regs[a->rs]); + return true; +} + +/* movu. [ri,rb],rd */ +static bool trans_MOVU_ar(DisasContext *ctx, arg_MOVU_ar *a) +{ + TCGv mem; + mem =3D tcg_temp_new(); + rx_gen_regindex(ctx, mem, a->sz, a->ri, a->rb); + rx_gen_ldu(a->sz, cpu_regs[a->rd], mem); + tcg_temp_free(mem); + return true; +} + +/* movu. [rd+],rs */ +/* mov. [-rd],rs */ +static bool trans_MOVU_pr(DisasContext *ctx, arg_MOVU_pr *a) +{ + TCGv val; + val =3D tcg_temp_new(); + if (a->ad =3D=3D 1) { + tcg_gen_subi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); + } + rx_gen_ldu(a->sz, val, cpu_regs[a->rd]); + if (a->ad =3D=3D 0) { + tcg_gen_addi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1 << a->sz); + } + tcg_gen_mov_i32(cpu_regs[a->rs], val); + tcg_temp_free(val); + return true; +} + + +/* pop rd */ +static bool trans_POP(DisasContext *ctx, arg_POP *a) +{ + /* mov.l [r0+], rd */ + arg_MOV_rp mov_a; + mov_a.rd =3D 0; + mov_a.rs =3D a->rd; + mov_a.ad =3D 0; + mov_a.sz =3D MO_32; + trans_MOV_pr(ctx, &mov_a); + return true; +} + +/* popc cr */ +static bool trans_POPC(DisasContext *ctx, arg_POPC *a) +{ + TCGv val; + val =3D tcg_temp_new(); + pop(val); + move_to_cr(ctx, val, a->cr); + if (a->cr =3D=3D 0 && is_privileged(ctx, 0)) { + /* PSW.I may be updated here. exit TB. */ + ctx->base.is_jmp =3D DISAS_UPDATE; + } + tcg_temp_free(val); + return true; +} + +/* popm rd-rd2 */ +static bool trans_POPM(DisasContext *ctx, arg_POPM *a) +{ + int r; + if (a->rd =3D=3D 0 || a->rd >=3D a->rd2) { + qemu_log_mask(LOG_GUEST_ERROR, + "Invalid register ranges r%d-r%d", a->rd, a->rd2); + } + r =3D a->rd; + while (r <=3D a->rd2 && r < 16) { + pop(cpu_regs[r++]); + } + return true; +} + + +/* push. rs */ +static bool trans_PUSH_r(DisasContext *ctx, arg_PUSH_r *a) +{ + TCGv val; + val =3D tcg_temp_new(); + tcg_gen_mov_i32(val, cpu_regs[a->rs]); + tcg_gen_subi_i32(cpu_sp, cpu_sp, 4); + rx_gen_st(a->sz, val, cpu_sp); + tcg_temp_free(val); + return true; +} + +/* push. dsp[rs] */ +static bool trans_PUSH_m(DisasContext *ctx, arg_PUSH_m *a) +{ + TCGv mem, val, addr; + mem =3D tcg_temp_new(); + val =3D tcg_temp_new(); + addr =3D rx_index_addr(ctx, mem, a->ld, a->sz, a->rs); + rx_gen_ld(a->sz, val, addr); + tcg_gen_subi_i32(cpu_sp, cpu_sp, 4); + rx_gen_st(a->sz, val, cpu_sp); + tcg_temp_free(mem); + tcg_temp_free(val); + return true; +} + +/* pushc rx */ +static bool trans_PUSHC(DisasContext *ctx, arg_PUSHC *a) +{ + TCGv val; + val =3D tcg_temp_new(); + move_from_cr(val, a->cr, ctx->pc); + push(val); + tcg_temp_free(val); + return true; +} + +/* pushm rs-rs2 */ +static bool trans_PUSHM(DisasContext *ctx, arg_PUSHM *a) +{ + int r; + + if (a->rs =3D=3D 0 || a->rs >=3D a->rs2) { + qemu_log_mask(LOG_GUEST_ERROR, + "Invalid register ranges r%d-r%d", a->rs, a->rs2); + } + r =3D a->rs2; + while (r >=3D a->rs && r >=3D 0) { + push(cpu_regs[r--]); + } + return true; +} + +/* xchg rs,rd */ +static bool trans_XCHG_rr(DisasContext *ctx, arg_XCHG_rr *a) +{ + TCGv tmp; + tmp =3D tcg_temp_new(); + tcg_gen_mov_i32(tmp, cpu_regs[a->rs]); + tcg_gen_mov_i32(cpu_regs[a->rs], cpu_regs[a->rd]); + tcg_gen_mov_i32(cpu_regs[a->rd], tmp); + tcg_temp_free(tmp); + return true; +} + +/* xchg dsp[rs].,rd */ +static bool trans_XCHG_mr(DisasContext *ctx, arg_XCHG_mr *a) +{ + TCGv mem, addr; + mem =3D tcg_temp_new(); + switch (a->mi) { + case 0: /* dsp[rs].b */ + case 1: /* dsp[rs].w */ + case 2: /* dsp[rs].l */ + addr =3D rx_index_addr(ctx, mem, a->ld, a->mi, a->rs); + break; + case 3: /* dsp[rs].uw */ + case 4: /* dsp[rs].ub */ + addr =3D rx_index_addr(ctx, mem, a->ld, 4 - a->mi, a->rs); + break; + default: + g_assert_not_reached(); + } + tcg_gen_atomic_xchg_i32(cpu_regs[a->rd], addr, cpu_regs[a->rd], + 0, mi_to_mop(a->mi)); + tcg_temp_free(mem); + return true; +} + +static inline void stcond(TCGCond cond, int rd, int imm) +{ + TCGv z; + TCGv _imm; + z =3D tcg_const_i32(0); + _imm =3D tcg_const_i32(imm); + tcg_gen_movcond_i32(cond, cpu_regs[rd], cpu_psw_z, z, + _imm, cpu_regs[rd]); + tcg_temp_free(z); + tcg_temp_free(_imm); +} + +/* stz #imm,rd */ +static bool trans_STZ(DisasContext *ctx, arg_STZ *a) +{ + stcond(TCG_COND_EQ, a->rd, a->imm); + return true; +} + +/* stnz #imm,rd */ +static bool trans_STNZ(DisasContext *ctx, arg_STNZ *a) +{ + stcond(TCG_COND_NE, a->rd, a->imm); + return true; +} + +/* sccnd. rd */ +/* sccnd. dsp:[rd] */ +static bool trans_SCCnd(DisasContext *ctx, arg_SCCnd *a) +{ + DisasCompare dc; + TCGv val, mem, addr; + dc.temp =3D tcg_temp_new(); + psw_cond(&dc, a->cd); + if (a->ld < 3) { + val =3D tcg_temp_new(); + mem =3D tcg_temp_new(); + tcg_gen_setcondi_i32(dc.cond, val, dc.value, 0); + addr =3D rx_index_addr(ctx, mem, a->sz, a->ld, a->rd); + rx_gen_st(a->sz, val, addr); + tcg_temp_free(val); + tcg_temp_free(mem); + } else { + tcg_gen_setcondi_i32(dc.cond, cpu_regs[a->rd], dc.value, 0); + } + tcg_temp_free(dc.temp); + return true; +} + +/* rtsd #imm */ +static bool trans_RTSD_i(DisasContext *ctx, arg_RTSD_i *a) +{ + tcg_gen_addi_i32(cpu_sp, cpu_sp, a->imm << 2); + pop(cpu_pc); + ctx->base.is_jmp =3D DISAS_JUMP; + return true; +} + +/* rtsd #imm, rd-rd2 */ +static bool trans_RTSD_irr(DisasContext *ctx, arg_RTSD_irr *a) +{ + int dst; + int adj; + + if (a->rd2 >=3D a->rd) { + adj =3D a->imm - (a->rd2 - a->rd + 1); + } else { + adj =3D a->imm - (15 - a->rd + 1); + } + + tcg_gen_addi_i32(cpu_sp, cpu_sp, adj << 2); + dst =3D a->rd; + while (dst <=3D a->rd2 && dst < 16) { + pop(cpu_regs[dst++]); + } + pop(cpu_pc); + ctx->base.is_jmp =3D DISAS_JUMP; + return true; +} + +typedef void (*op2fn)(TCGv ret, TCGv arg1); +typedef void (*op3fn)(TCGv ret, TCGv arg1, TCGv arg2); + +static inline void rx_gen_op_rr(op2fn opr, int dst, int src) +{ + opr(cpu_regs[dst], cpu_regs[src]); +} + +static inline void rx_gen_op_rrr(op3fn opr, int dst, int src, int src2) +{ + opr(cpu_regs[dst], cpu_regs[src], cpu_regs[src2]); +} + +static inline void rx_gen_op_irr(op3fn opr, int dst, int src, uint32_t src= 2) +{ + TCGv imm =3D tcg_const_i32(src2); + opr(cpu_regs[dst], cpu_regs[src], imm); + tcg_temp_free(imm); +} + +static inline void rx_gen_op_mr(op3fn opr, DisasContext *ctx, + int dst, int src, int ld, int mi) +{ + TCGv val, mem; + mem =3D tcg_temp_new(); + val =3D rx_load_source(ctx, mem, ld, mi, src); + opr(cpu_regs[dst], cpu_regs[dst], val); + tcg_temp_free(mem); +} + +static void rx_and(TCGv ret, TCGv arg1, TCGv arg2) +{ + tcg_gen_and_i32(cpu_psw_s, arg1, arg2); + tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); + tcg_gen_mov_i32(ret, cpu_psw_s); +} + +/* and #uimm:4, rd */ +/* and #imm, rd */ +static bool trans_AND_ir(DisasContext *ctx, arg_AND_ir *a) +{ + rx_gen_op_irr(rx_and, a->rd, a->rd, a->imm); + return true; +} + +/* and dsp[rs], rd */ +/* and rs,rd */ +static bool trans_AND_mr(DisasContext *ctx, arg_AND_mr *a) +{ + rx_gen_op_mr(rx_and, ctx, a->rd, a->rs, a->ld, a->mi); + return true; +} + +/* and rs,rs2,rd */ +static bool trans_AND_rrr(DisasContext *ctx, arg_AND_rrr *a) +{ + rx_gen_op_rrr(rx_and, a->rd, a->rs, a->rs2); + return true; +} + +static void rx_or(TCGv ret, TCGv arg1, TCGv arg2) +{ + tcg_gen_or_i32(cpu_psw_s, arg1, arg2); + tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); + tcg_gen_mov_i32(ret, cpu_psw_s); +} + +/* or #uimm:4, rd */ +/* or #imm, rd */ +static bool trans_OR_ir(DisasContext *ctx, arg_OR_ir *a) +{ + rx_gen_op_irr(rx_or, a->rd, a->rd, a->imm); + return true; +} + +/* or dsp[rs], rd */ +/* or rs,rd */ +static bool trans_OR_mr(DisasContext *ctx, arg_OR_mr *a) +{ + rx_gen_op_mr(rx_or, ctx, a->rd, a->rs, a->ld, a->mi); + return true; +} + +/* or rs,rs2,rd */ +static bool trans_OR_rrr(DisasContext *ctx, arg_OR_rrr *a) +{ + rx_gen_op_rrr(rx_or, a->rd, a->rs, a->rs2); + return true; +} + +static void rx_xor(TCGv ret, TCGv arg1, TCGv arg2) +{ + tcg_gen_xor_i32(cpu_psw_s, arg1, arg2); + tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); + tcg_gen_mov_i32(ret, cpu_psw_s); +} + +/* xor #imm, rd */ +static bool trans_XOR_ir(DisasContext *ctx, arg_XOR_ir *a) +{ + rx_gen_op_irr(rx_xor, a->rd, a->rd, a->imm); + return true; +} + +/* xor dsp[rs], rd */ +/* xor rs,rd */ +static bool trans_XOR_mr(DisasContext *ctx, arg_XOR_mr *a) +{ + rx_gen_op_mr(rx_xor, ctx, a->rd, a->rs, a->ld, a->mi); + return true; +} + +static void rx_tst(TCGv ret, TCGv arg1, TCGv arg2) +{ + tcg_gen_and_i32(cpu_psw_s, arg1, arg2); + tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); +} + +/* tst #imm, rd */ +static bool trans_TST_ir(DisasContext *ctx, arg_TST_ir *a) +{ + rx_gen_op_irr(rx_tst, a->rd, a->rd, a->imm); + return true; +} + +/* tst dsp[rs], rd */ +/* tst rs, rd */ +static bool trans_TST_mr(DisasContext *ctx, arg_TST_mr *a) +{ + rx_gen_op_mr(rx_tst, ctx, a->rd, a->rs, a->ld, a->mi); + return true; +} + +static void rx_not(TCGv ret, TCGv arg1) +{ + tcg_gen_not_i32(ret, arg1); + tcg_gen_mov_i32(cpu_psw_z, ret); + tcg_gen_mov_i32(cpu_psw_s, ret); +} + +/* not rd */ +/* not rs, rd */ +static bool trans_NOT_rr(DisasContext *ctx, arg_NOT_rr *a) +{ + rx_gen_op_rr(rx_not, a->rd, a->rs); + return true; +} + +static void rx_neg(TCGv ret, TCGv arg1) +{ + tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, arg1, 0x80000000); + tcg_gen_neg_i32(ret, arg1); + tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_c, ret, 0); + tcg_gen_mov_i32(cpu_psw_z, ret); + tcg_gen_mov_i32(cpu_psw_s, ret); +} + + +/* neg rd */ +/* neg rs, rd */ +static bool trans_NEG_rr(DisasContext *ctx, arg_NEG_rr *a) +{ + rx_gen_op_rr(rx_neg, a->rd, a->rs); + return true; +} + +/* ret =3D arg1 + arg2 + psw_c */ +static void rx_adc(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv z; + z =3D tcg_const_i32(0); + tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, cpu_psw_c, z); + tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, cpu_psw_s, cpu_psw_c, arg2, z); + tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); + tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1); + tcg_gen_xor_i32(z, arg1, arg2); + tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, z); + tcg_gen_mov_i32(ret, cpu_psw_s); + tcg_temp_free(z); +} + +/* adc #imm, rd */ +static bool trans_ADC_ir(DisasContext *ctx, arg_ADC_ir *a) +{ + rx_gen_op_irr(rx_adc, a->rd, a->rd, a->imm); + return true; +} + +/* adc rs, rd */ +static bool trans_ADC_rr(DisasContext *ctx, arg_ADC_rr *a) +{ + rx_gen_op_rrr(rx_adc, a->rd, a->rd, a->rs); + return true; +} + +/* adc dsp[rs], rd */ +static bool trans_ADC_mr(DisasContext *ctx, arg_ADC_mr *a) +{ + /* mi only 2 */ + if (a->mi !=3D 2) { + return false; + } + rx_gen_op_mr(rx_adc, ctx, a->rd, a->rs, a->ld, a->mi); + return true; +} + +/* ret =3D arg1 + arg2 */ +static void rx_add(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv z; + z =3D tcg_const_i32(0); + tcg_gen_add2_i32(cpu_psw_s, cpu_psw_c, arg1, z, arg2, z); + tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); + tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1); + tcg_gen_xor_i32(z, arg1, arg2); + tcg_gen_andc_i32(cpu_psw_o, cpu_psw_o, z); + tcg_gen_mov_i32(ret, cpu_psw_s); + tcg_temp_free(z); +} + +/* add #uimm4, rd */ +/* add #imm, rs, rd */ +static bool trans_ADD_irr(DisasContext *ctx, arg_ADD_irr *a) +{ + rx_gen_op_irr(rx_add, a->rd, a->rs2, a->imm); + return true; +} + +/* add rs, rd */ +/* add dsp[rs], rd */ +static bool trans_ADD_mr(DisasContext *ctx, arg_ADD_mr *a) +{ + rx_gen_op_mr(rx_add, ctx, a->rd, a->rs, a->ld, a->mi); + return true; +} + +/* add rs, rs2, rd */ +static bool trans_ADD_rrr(DisasContext *ctx, arg_ADD_rrr *a) +{ + rx_gen_op_rrr(rx_add, a->rd, a->rs, a->rs2); + return true; +} + +/* ret =3D arg1 - arg2 */ +static void rx_sub(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv temp; + tcg_gen_sub_i32(cpu_psw_s, arg1, arg2); + tcg_gen_mov_i32(cpu_psw_z, cpu_psw_s); + tcg_gen_setcond_i32(TCG_COND_GEU, cpu_psw_c, arg1, arg2); + tcg_gen_xor_i32(cpu_psw_o, cpu_psw_s, arg1); + temp =3D tcg_temp_new_i32(); + tcg_gen_xor_i32(temp, arg1, arg2); + tcg_gen_and_i32(cpu_psw_o, cpu_psw_o, temp); + tcg_temp_free_i32(temp); + /* CMP not requred return */ + if (ret) { + tcg_gen_mov_i32(ret, cpu_psw_s); + } +} +static void rx_cmp(TCGv dummy, TCGv arg1, TCGv arg2) +{ + rx_sub(NULL, arg1, arg2); +} +/* ret =3D arg1 - arg2 - !psw_c */ +/* -> ret =3D arg1 + ~arg2 + psw_c */ +static void rx_sbb(TCGv ret, TCGv arg1, TCGv arg2) +{ + TCGv temp; + temp =3D tcg_temp_new(); + tcg_gen_not_i32(temp, arg2); + rx_adc(ret, arg1, temp); + tcg_temp_free(temp); +} + +/* cmp #imm4, rs2 */ +/* cmp #imm8, rs2 */ +/* cmp #imm, rs2 */ +static bool trans_CMP_ir(DisasContext *ctx, arg_CMP_ir *a) +{ + rx_gen_op_irr(rx_cmp, 0, a->rs2, a->imm); + return true; +} + +/* cmp rs, rs2 */ +/* cmp dsp[rs], rs2 */ +static bool trans_CMP_mr(DisasContext *ctx, arg_CMP_mr *a) +{ + rx_gen_op_mr(rx_cmp, ctx, a->rd, a->rs, a->ld, a->mi); + return true; +} + +/* sub #imm4, rd */ +static bool trans_SUB_ir(DisasContext *ctx, arg_SUB_ir *a) +{ + rx_gen_op_irr(rx_sub, a->rd, a->rd, a->imm); + return true; +} + +/* sub rs, rd */ +/* sub dsp[rs], rd */ +static bool trans_SUB_mr(DisasContext *ctx, arg_SUB_mr *a) +{ + rx_gen_op_mr(rx_sub, ctx, a->rd, a->rs, a->ld, a->mi); + return true; +} + +/* sub rs2, rs, rd */ +static bool trans_SUB_rrr(DisasContext *ctx, arg_SUB_rrr *a) +{ + rx_gen_op_rrr(rx_sub, a->rd, a->rs2, a->rs); + return true; +} + +/* sbb rs, rd */ +static bool trans_SBB_rr(DisasContext *ctx, arg_SBB_rr *a) +{ + rx_gen_op_rrr(rx_sbb, a->rd, a->rd, a->rs); + return true; +} + +/* sbb dsp[rs], rd */ +static bool trans_SBB_mr(DisasContext *ctx, arg_SBB_mr *a) +{ + /* mi only 2 */ + if (a->mi !=3D 2) { + return false; + } + rx_gen_op_mr(rx_sbb, ctx, a->rd, a->rs, a->ld, a->mi); + return true; +} + +static void rx_abs(TCGv ret, TCGv arg1) +{ + TCGv neg; + TCGv zero; + neg =3D tcg_temp_new(); + zero =3D tcg_const_i32(0); + tcg_gen_neg_i32(neg, arg1); + tcg_gen_movcond_i32(TCG_COND_LT, ret, arg1, zero, neg, arg1); + tcg_temp_free(neg); + tcg_temp_free(zero); +} + +/* abs rd */ +/* abs rs, rd */ +static bool trans_ABS_rr(DisasContext *ctx, arg_ABS_rr *a) +{ + rx_gen_op_rr(rx_abs, a->rd, a->rs); + return true; +} + +/* max #imm, rd */ +static bool trans_MAX_ir(DisasContext *ctx, arg_MAX_ir *a) +{ + rx_gen_op_irr(tcg_gen_smax_i32, a->rd, a->rd, a->imm); + return true; +} + +/* max rs, rd */ +/* max dsp[rs], rd */ +static bool trans_MAX_mr(DisasContext *ctx, arg_MAX_mr *a) +{ + rx_gen_op_mr(tcg_gen_smax_i32, ctx, a->rd, a->rs, a->ld, a->mi); + return true; +} + +/* min #imm, rd */ +static bool trans_MIN_ir(DisasContext *ctx, arg_MIN_ir *a) +{ + rx_gen_op_irr(tcg_gen_smin_i32, a->rd, a->rd, a->imm); + return true; +} + +/* min rs, rd */ +/* min dsp[rs], rd */ +static bool trans_MIN_mr(DisasContext *ctx, arg_MIN_mr *a) +{ + rx_gen_op_mr(tcg_gen_smin_i32, ctx, a->rd, a->rs, a->ld, a->mi); + return true; +} + +/* mul #uimm4, rd */ +/* mul #imm, rd */ +static bool trans_MUL_ir(DisasContext *ctx, arg_MUL_ir *a) +{ + rx_gen_op_irr(tcg_gen_mul_i32, a->rd, a->rd, a->imm); + return true; +} + +/* mul rs, rd */ +/* mul dsp[rs], rd */ +static bool trans_MUL_mr(DisasContext *ctx, arg_MUL_mr *a) +{ + rx_gen_op_mr(tcg_gen_mul_i32, ctx, a->rd, a->rs, a->ld, a->mi); + return true; +} + +/* mul rs, rs2, rd */ +static bool trans_MUL_rrr(DisasContext *ctx, arg_MUL_rrr *a) +{ + rx_gen_op_rrr(tcg_gen_mul_i32, a->rd, a->rs, a->rs2); + return true; +} + +/* emul #imm, rd */ +static bool trans_EMUL_ir(DisasContext *ctx, arg_EMUL_ir *a) +{ + TCGv imm =3D tcg_const_i32(a->imm); + if (a->rd > 14) { + qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); + } + tcg_gen_muls2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], + cpu_regs[a->rd], imm); + tcg_temp_free(imm); + return true; +} + +/* emul rs, rd */ +/* emul dsp[rs], rd */ +static bool trans_EMUL_mr(DisasContext *ctx, arg_EMUL_mr *a) +{ + TCGv val, mem; + if (a->rd > 14) { + qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); + } + mem =3D tcg_temp_new(); + val =3D rx_load_source(ctx, mem, a->ld, a->mi, a->rs); + tcg_gen_muls2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], + cpu_regs[a->rd], val); + tcg_temp_free(mem); + return true; +} + +/* emulu #imm, rd */ +static bool trans_EMULU_ir(DisasContext *ctx, arg_EMULU_ir *a) +{ + TCGv imm =3D tcg_const_i32(a->imm); + if (a->rd > 14) { + qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); + } + tcg_gen_mulu2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], + cpu_regs[a->rd], imm); + tcg_temp_free(imm); + return true; +} + +/* emulu rs, rd */ +/* emulu dsp[rs], rd */ +static bool trans_EMULU_mr(DisasContext *ctx, arg_EMULU_mr *a) +{ + TCGv val, mem; + if (a->rd > 14) { + qemu_log_mask(LOG_GUEST_ERROR, "rd too large %d", a->rd); + } + mem =3D tcg_temp_new(); + val =3D rx_load_source(ctx, mem, a->ld, a->mi, a->rs); + tcg_gen_mulu2_i32(cpu_regs[a->rd], cpu_regs[(a->rd + 1) & 15], + cpu_regs[a->rd], val); + tcg_temp_free(mem); + return true; +} + +static void rx_div(TCGv ret, TCGv arg1, TCGv arg2) +{ + gen_helper_div(ret, cpu_env, arg1, arg2); +} + +static void rx_divu(TCGv ret, TCGv arg1, TCGv arg2) +{ + gen_helper_divu(ret, cpu_env, arg1, arg2); +} + +/* div #imm, rd */ +static bool trans_DIV_ir(DisasContext *ctx, arg_DIV_ir *a) +{ + rx_gen_op_irr(rx_div, a->rd, a->rd, a->imm); + return true; +} + +/* div rs, rd */ +/* div dsp[rs], rd */ +static bool trans_DIV_mr(DisasContext *ctx, arg_DIV_mr *a) +{ + rx_gen_op_mr(rx_div, ctx, a->rd, a->rs, a->ld, a->mi); + return true; +} + +/* divu #imm, rd */ +static bool trans_DIVU_ir(DisasContext *ctx, arg_DIVU_ir *a) +{ + rx_gen_op_irr(rx_divu, a->rd, a->rd, a->imm); + return true; +} + +/* divu rs, rd */ +/* divu dsp[rs], rd */ +static bool trans_DIVU_mr(DisasContext *ctx, arg_DIVU_mr *a) +{ + rx_gen_op_mr(rx_divu, ctx, a->rd, a->rs, a->ld, a->mi); + return true; +} + + +/* shll #imm:5, rd */ +/* shll #imm:5, rs2, rd */ +static bool trans_SHLL_irr(DisasContext *ctx, arg_SHLL_irr *a) +{ + TCGv tmp; + tmp =3D tcg_temp_new(); + if (a->imm) { + tcg_gen_sari_i32(cpu_psw_c, cpu_regs[a->rs2], 32 - a->imm); + tcg_gen_shli_i32(cpu_regs[a->rd], cpu_regs[a->rs2], a->imm); + tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, cpu_psw_c, 0); + tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_psw_c, 0xffffffff); + tcg_gen_or_i32(cpu_psw_o, cpu_psw_o, tmp); + tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, cpu_psw_c, 0); + } else { + tcg_gen_mov_i32(cpu_regs[a->rd], cpu_regs[a->rs2]); + tcg_gen_movi_i32(cpu_psw_c, 0); + tcg_gen_movi_i32(cpu_psw_o, 0); + } + tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); + tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); + return true; +} + +/* shll rs, rd */ +static bool trans_SHLL_rr(DisasContext *ctx, arg_SHLL_rr *a) +{ + TCGLabel *noshift, *done; + TCGv count, tmp; + + noshift =3D gen_new_label(); + done =3D gen_new_label(); + /* if (cpu_regs[a->rs]) { */ + tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_regs[a->rs], 0, noshift); + count =3D tcg_const_i32(32); + tmp =3D tcg_temp_new(); + tcg_gen_andi_i32(tmp, cpu_regs[a->rs], 31); + tcg_gen_sub_i32(count, count, tmp); + tcg_gen_sar_i32(cpu_psw_c, cpu_regs[a->rd], count); + tcg_gen_shl_i32(cpu_regs[a->rd], cpu_regs[a->rd], tmp); + tcg_gen_setcondi_i32(TCG_COND_EQ, cpu_psw_o, cpu_psw_c, 0); + tcg_gen_setcondi_i32(TCG_COND_EQ, tmp, cpu_psw_c, 0xffffffff); + tcg_gen_or_i32(cpu_psw_o, cpu_psw_o, tmp); + tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, cpu_psw_c, 0); + tcg_gen_br(done); + /* } else { */ + gen_set_label(noshift); + tcg_gen_movi_i32(cpu_psw_c, 0); + tcg_gen_movi_i32(cpu_psw_o, 0); + /* } */ + gen_set_label(done); + tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); + tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); + tcg_temp_free(count); + tcg_temp_free(tmp); + return true; +} + +static inline void shiftr_imm(uint32_t rd, uint32_t rs, uint32_t imm, + unsigned int alith) +{ + static void (* const gen_sXri[])(TCGv ret, TCGv arg1, int arg2) =3D { + tcg_gen_shri_i32, tcg_gen_sari_i32, + }; + tcg_debug_assert(alith < 2); + if (imm) { + gen_sXri[alith](cpu_regs[rd], cpu_regs[rs], imm - 1); + tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001); + gen_sXri[alith](cpu_regs[rd], cpu_regs[rd], 1); + } else { + tcg_gen_mov_i32(cpu_regs[rd], cpu_regs[rs]); + tcg_gen_movi_i32(cpu_psw_c, 0); + } + tcg_gen_movi_i32(cpu_psw_o, 0); + tcg_gen_mov_i32(cpu_psw_z, cpu_regs[rd]); + tcg_gen_mov_i32(cpu_psw_s, cpu_regs[rd]); +} + +static inline void shiftr_reg(uint32_t rd, uint32_t rs, unsigned int alith) +{ + TCGLabel *noshift, *done; + TCGv count; + static void (* const gen_sXri[])(TCGv ret, TCGv arg1, int arg2) =3D { + tcg_gen_shri_i32, tcg_gen_sari_i32, + }; + static void (* const gen_sXr[])(TCGv ret, TCGv arg1, TCGv arg2) =3D { + tcg_gen_shr_i32, tcg_gen_sar_i32, + }; + tcg_debug_assert(alith < 2); + noshift =3D gen_new_label(); + done =3D gen_new_label(); + count =3D tcg_temp_new(); + /* if (cpu_regs[rs]) { */ + tcg_gen_brcondi_i32(TCG_COND_EQ, cpu_regs[rs], 0, noshift); + tcg_gen_andi_i32(count, cpu_regs[rs], 31); + tcg_gen_subi_i32(count, count, 1); + gen_sXr[alith](cpu_regs[rd], cpu_regs[rd], count); + tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001); + gen_sXri[alith](cpu_regs[rd], cpu_regs[rd], 1); + tcg_gen_br(done); + /* } else { */ + gen_set_label(noshift); + tcg_gen_movi_i32(cpu_psw_c, 0); + /* } */ + gen_set_label(done); + tcg_gen_movi_i32(cpu_psw_o, 0); + tcg_gen_mov_i32(cpu_psw_z, cpu_regs[rd]); + tcg_gen_mov_i32(cpu_psw_s, cpu_regs[rd]); + tcg_temp_free(count); +} + +/* shar #imm:5, rd */ +/* shar #imm:5, rs2, rd */ +static bool trans_SHAR_irr(DisasContext *ctx, arg_SHAR_irr *a) +{ + shiftr_imm(a->rd, a->rs2, a->imm, 1); + return true; +} + +/* shar rs, rd */ +static bool trans_SHAR_rr(DisasContext *ctx, arg_SHAR_rr *a) +{ + shiftr_reg(a->rd, a->rs, 1); + return true; +} + +/* shlr #imm:5, rd */ +/* shlr #imm:5, rs2, rd */ +static bool trans_SHLR_irr(DisasContext *ctx, arg_SHLR_irr *a) +{ + shiftr_imm(a->rd, a->rs2, a->imm, 0); + return true; +} + +/* shlr rs, rd */ +static bool trans_SHLR_rr(DisasContext *ctx, arg_SHLR_rr *a) +{ + shiftr_reg(a->rd, a->rs, 0); + return true; +} + +/* rolc rd */ +static bool trans_ROLC(DisasContext *ctx, arg_ROLC *a) +{ + TCGv tmp; + tmp =3D tcg_temp_new(); + tcg_gen_shri_i32(tmp, cpu_regs[a->rd], 31); + tcg_gen_shli_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1); + tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], cpu_psw_c); + tcg_gen_mov_i32(cpu_psw_c, tmp); + tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); + tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); + tcg_temp_free(tmp); + return true; +} + +/* rorc rd */ +static bool trans_RORC(DisasContext *ctx, arg_RORC *a) +{ + TCGv tmp; + tmp =3D tcg_temp_new(); + tcg_gen_andi_i32(tmp, cpu_regs[a->rd], 0x00000001); + tcg_gen_shri_i32(cpu_regs[a->rd], cpu_regs[a->rd], 1); + tcg_gen_shli_i32(cpu_psw_c, cpu_psw_c, 31); + tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], cpu_psw_c); + tcg_gen_mov_i32(cpu_psw_c, tmp); + tcg_gen_mov_i32(cpu_psw_z, cpu_regs[a->rd]); + tcg_gen_mov_i32(cpu_psw_s, cpu_regs[a->rd]); + return true; +} + +enum {ROTR =3D 0, ROTL =3D 1}; +enum {ROT_IMM =3D 0, ROT_REG =3D 1}; +static inline void rx_rot(int ir, int dir, int rd, int src) +{ + switch (dir) { + case ROTL: + if (ir =3D=3D ROT_IMM) { + tcg_gen_rotli_i32(cpu_regs[rd], cpu_regs[rd], src); + } else { + tcg_gen_rotl_i32(cpu_regs[rd], cpu_regs[rd], cpu_regs[src]); + } + tcg_gen_andi_i32(cpu_psw_c, cpu_regs[rd], 0x00000001); + break; + case ROTR: + if (ir =3D=3D ROT_IMM) { + tcg_gen_rotri_i32(cpu_regs[rd], cpu_regs[rd], src); + } else { + tcg_gen_rotr_i32(cpu_regs[rd], cpu_regs[rd], cpu_regs[src]); + } + tcg_gen_shri_i32(cpu_psw_c, cpu_regs[rd], 31); + break; + } + tcg_gen_mov_i32(cpu_psw_z, cpu_regs[rd]); + tcg_gen_mov_i32(cpu_psw_s, cpu_regs[rd]); +} + +/* rotl #imm, rd */ +static bool trans_ROTL_ir(DisasContext *ctx, arg_ROTL_ir *a) +{ + rx_rot(ROT_IMM, ROTL, a->rd, a->imm); + return true; +} + +/* rotl rs, rd */ +static bool trans_ROTL_rr(DisasContext *ctx, arg_ROTL_rr *a) +{ + rx_rot(ROT_REG, ROTL, a->rd, a->rs); + return true; +} + +/* rotr #imm, rd */ +static bool trans_ROTR_ir(DisasContext *ctx, arg_ROTR_ir *a) +{ + rx_rot(ROT_IMM, ROTR, a->rd, a->imm); + return true; +} + +/* rotr rs, rd */ +static bool trans_ROTR_rr(DisasContext *ctx, arg_ROTR_rr *a) +{ + rx_rot(ROT_REG, ROTR, a->rd, a->rs); + return true; +} + +/* revl rs, rd */ +static bool trans_REVL(DisasContext *ctx, arg_REVL *a) +{ + tcg_gen_bswap32_i32(cpu_regs[a->rd], cpu_regs[a->rs]); + return true; +} + +/* revw rs, rd */ +static bool trans_REVW(DisasContext *ctx, arg_REVW *a) +{ + TCGv tmp; + tmp =3D tcg_temp_new(); + tcg_gen_andi_i32(tmp, cpu_regs[a->rs], 0x00ff00ff); + tcg_gen_shli_i32(tmp, tmp, 8); + tcg_gen_shri_i32(cpu_regs[a->rd], cpu_regs[a->rs], 8); + tcg_gen_andi_i32(cpu_regs[a->rd], cpu_regs[a->rd], 0x00ff00ff); + tcg_gen_or_i32(cpu_regs[a->rd], cpu_regs[a->rd], tmp); + tcg_temp_free(tmp); + return true; +} + +/* conditional branch helper */ +static void rx_bcnd_main(DisasContext *ctx, int cd, int dst) +{ + DisasCompare dc; + TCGLabel *t, *done; + + switch (cd) { + case 0 ... 13: + dc.temp =3D tcg_temp_new(); + psw_cond(&dc, cd); + t =3D gen_new_label(); + done =3D gen_new_label(); + tcg_gen_brcondi_i32(dc.cond, dc.value, 0, t); + gen_goto_tb(ctx, 0, ctx->base.pc_next); + tcg_gen_br(done); + gen_set_label(t); + gen_goto_tb(ctx, 1, ctx->pc + dst); + gen_set_label(done); + tcg_temp_free(dc.temp); + break; + case 14: + /* always true case */ + gen_goto_tb(ctx, 0, ctx->pc + dst); + break; + case 15: + /* always false case */ + /* Nothing do */ + break; + } +} + +/* beq dsp:3 / bne dsp:3 */ +/* beq dsp:8 / bne dsp:8 */ +/* bc dsp:8 / bnc dsp:8 */ +/* bgtu dsp:8 / bleu dsp:8 */ +/* bpz dsp:8 / bn dsp:8 */ +/* bge dsp:8 / blt dsp:8 */ +/* bgt dsp:8 / ble dsp:8 */ +/* bo dsp:8 / bno dsp:8 */ +/* beq dsp:16 / bne dsp:16 */ +static bool trans_BCnd(DisasContext *ctx, arg_BCnd *a) +{ + rx_bcnd_main(ctx, a->cd, a->dsp); + return true; +} + +/* bra dsp:3 */ +/* bra dsp:8 */ +/* bra dsp:16 */ +/* bra dsp:24 */ +static bool trans_BRA(DisasContext *ctx, arg_BRA *a) +{ + rx_bcnd_main(ctx, 14, a->dsp); + return true; +} + +/* bra rs */ +static bool trans_BRA_l(DisasContext *ctx, arg_BRA_l *a) +{ + tcg_gen_addi_i32(cpu_pc, cpu_regs[a->rd], ctx->pc); + ctx->base.is_jmp =3D DISAS_JUMP; + return true; +} + +static inline void rx_save_pc(DisasContext *ctx) +{ + TCGv pc =3D tcg_const_i32(ctx->base.pc_next); + push(pc); + tcg_temp_free(pc); +} + +/* jmp rs */ +static bool trans_JMP(DisasContext *ctx, arg_JMP *a) +{ + tcg_gen_mov_i32(cpu_pc, cpu_regs[a->rs]); + ctx->base.is_jmp =3D DISAS_JUMP; + return true; +} + +/* jsr rs */ +static bool trans_JSR(DisasContext *ctx, arg_JSR *a) +{ + rx_save_pc(ctx); + tcg_gen_mov_i32(cpu_pc, cpu_regs[a->rs]); + ctx->base.is_jmp =3D DISAS_JUMP; + return true; +} + +/* bsr dsp:16 */ +/* bsr dsp:24 */ +static bool trans_BSR(DisasContext *ctx, arg_BSR *a) +{ + rx_save_pc(ctx); + rx_bcnd_main(ctx, 14, a->dsp); + return true; +} + +/* bsr rs */ +static bool trans_BSR_l(DisasContext *ctx, arg_BSR_l *a) +{ + rx_save_pc(ctx); + tcg_gen_addi_i32(cpu_pc, cpu_regs[a->rd], ctx->pc); + ctx->base.is_jmp =3D DISAS_JUMP; + return true; +} + +/* rts */ +static bool trans_RTS(DisasContext *ctx, arg_RTS *a) +{ + pop(cpu_pc); + ctx->base.is_jmp =3D DISAS_JUMP; + return true; +} + +/* nop */ +static bool trans_NOP(DisasContext *ctx, arg_NOP *a) +{ + return true; +} + +/* scmpu */ +static bool trans_SCMPU(DisasContext *ctx, arg_SCMPU *a) +{ + gen_helper_scmpu(cpu_env); + return true; +} + +/* smovu */ +static bool trans_SMOVU(DisasContext *ctx, arg_SMOVU *a) +{ + gen_helper_smovu(cpu_env); + return true; +} + +/* smovf */ +static bool trans_SMOVF(DisasContext *ctx, arg_SMOVF *a) +{ + gen_helper_smovf(cpu_env); + return true; +} + +/* smovb */ +static bool trans_SMOVB(DisasContext *ctx, arg_SMOVB *a) +{ + gen_helper_smovb(cpu_env); + return true; +} + +#define STRING(op) \ + do { \ + TCGv size =3D tcg_const_i32(a->sz); \ + gen_helper_##op(cpu_env, size); \ + tcg_temp_free(size); \ + } while (0) + +/* suntile. */ +static bool trans_SUNTIL(DisasContext *ctx, arg_SUNTIL *a) +{ + STRING(suntil); + return true; +} + +/* swhile. */ +static bool trans_SWHILE(DisasContext *ctx, arg_SWHILE *a) +{ + STRING(swhile); + return true; +} +/* sstr. */ +static bool trans_SSTR(DisasContext *ctx, arg_SSTR *a) +{ + STRING(sstr); + return true; +} + +/* rmpa. */ +static bool trans_RMPA(DisasContext *ctx, arg_RMPA *a) +{ + STRING(rmpa); + return true; +} + +static void rx_mul64hi(TCGv_i64 ret, int rs, int rs2) +{ + TCGv_i64 tmp0, tmp1; + tmp0 =3D tcg_temp_new_i64(); + tmp1 =3D tcg_temp_new_i64(); + tcg_gen_ext_i32_i64(tmp0, cpu_regs[rs]); + tcg_gen_sari_i64(tmp0, tmp0, 16); + tcg_gen_ext_i32_i64(tmp1, cpu_regs[rs2]); + tcg_gen_sari_i64(tmp1, tmp1, 16); + tcg_gen_mul_i64(ret, tmp0, tmp1); + tcg_gen_shli_i64(ret, ret, 16); + tcg_temp_free_i64(tmp0); + tcg_temp_free_i64(tmp1); +} + +static void rx_mul64lo(TCGv_i64 ret, int rs, int rs2) +{ + TCGv_i64 tmp0, tmp1; + tmp0 =3D tcg_temp_new_i64(); + tmp1 =3D tcg_temp_new_i64(); + tcg_gen_ext_i32_i64(tmp0, cpu_regs[rs]); + tcg_gen_ext16s_i64(tmp0, tmp0); + tcg_gen_ext_i32_i64(tmp1, cpu_regs[rs2]); + tcg_gen_ext16s_i64(tmp1, tmp1); + tcg_gen_mul_i64(ret, tmp0, tmp1); + tcg_gen_shli_i64(ret, ret, 16); + tcg_temp_free_i64(tmp0); + tcg_temp_free_i64(tmp1); +} + +/* mulhi rs,rs2 */ +static bool trans_MULHI(DisasContext *ctx, arg_MULHI *a) +{ + rx_mul64hi(cpu_acc, a->rs, a->rs2); + return true; +} + +/* mullo rs,rs2 */ +static bool trans_MULLO(DisasContext *ctx, arg_MULLO *a) +{ + rx_mul64lo(cpu_acc, a->rs, a->rs2); + return true; +} + +/* machi rs,rs2 */ +static bool trans_MACHI(DisasContext *ctx, arg_MACHI *a) +{ + TCGv_i64 tmp; + tmp =3D tcg_temp_new_i64(); + rx_mul64hi(tmp, a->rs, a->rs2); + tcg_gen_add_i64(cpu_acc, cpu_acc, tmp); + tcg_temp_free_i64(tmp); + return true; +} + +/* maclo rs,rs2 */ +static bool trans_MACLO(DisasContext *ctx, arg_MACLO *a) +{ + TCGv_i64 tmp; + tmp =3D tcg_temp_new_i64(); + rx_mul64lo(tmp, a->rs, a->rs2); + tcg_gen_add_i64(cpu_acc, cpu_acc, tmp); + tcg_temp_free_i64(tmp); + return true; +} + +/* mvfachi rd */ +static bool trans_MVFACHI(DisasContext *ctx, arg_MVFACHI *a) +{ + tcg_gen_extrh_i64_i32(cpu_regs[a->rd], cpu_acc); + return true; +} + +/* mvfacmi rd */ +static bool trans_MVFACMI(DisasContext *ctx, arg_MVFACMI *a) +{ + TCGv_i64 rd64; + rd64 =3D tcg_temp_new_i64(); + tcg_gen_extract_i64(rd64, cpu_acc, 16, 32); + tcg_gen_extrl_i64_i32(cpu_regs[a->rd], rd64); + tcg_temp_free_i64(rd64); + return true; +} + +/* mvtachi rs */ +static bool trans_MVTACHI(DisasContext *ctx, arg_MVTACHI *a) +{ + TCGv_i64 rs64; + rs64 =3D tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(rs64, cpu_regs[a->rs]); + tcg_gen_deposit_i64(cpu_acc, cpu_acc, rs64, 32, 32); + tcg_temp_free_i64(rs64); + return true; +} + +/* mvtaclo rs */ +static bool trans_MVTACLO(DisasContext *ctx, arg_MVTACLO *a) +{ + TCGv_i64 rs64; + rs64 =3D tcg_temp_new_i64(); + tcg_gen_extu_i32_i64(rs64, cpu_regs[a->rs]); + tcg_gen_deposit_i64(cpu_acc, cpu_acc, rs64, 0, 32); + tcg_temp_free_i64(rs64); + return true; +} + +/* racw #imm */ +static bool trans_RACW(DisasContext *ctx, arg_RACW *a) +{ + TCGv imm =3D tcg_const_i32(a->imm + 1); + gen_helper_racw(cpu_env, imm); + tcg_temp_free(imm); + return true; +} + +/* sat rd */ +static bool trans_SAT(DisasContext *ctx, arg_SAT *a) +{ + TCGv tmp, z; + tmp =3D tcg_temp_new(); + z =3D tcg_const_i32(0); + /* S =3D=3D 1 -> 0xffffffff / S =3D=3D 0 -> 0x00000000 */ + tcg_gen_sari_i32(tmp, cpu_psw_s, 31); + /* S =3D=3D 1 -> 0x7fffffff / S =3D=3D 0 -> 0x80000000 */ + tcg_gen_xori_i32(tmp, tmp, 0x80000000); + tcg_gen_movcond_i32(TCG_COND_LT, cpu_regs[a->rd], + cpu_psw_o, z, tmp, cpu_regs[a->rd]); + tcg_temp_free(tmp); + tcg_temp_free(z); + return true; +} + +/* satr */ +static bool trans_SATR(DisasContext *ctx, arg_SATR *a) +{ + gen_helper_satr(cpu_env); + return true; +} + +#define cat3(a, b, c) a##b##c +#define FOP(name, op) \ + static bool cat3(trans_, name, _ir)(DisasContext *ctx, \ + cat3(arg_, name, _ir) * a) \ + { \ + TCGv imm =3D tcg_const_i32(li(ctx, 0)); \ + gen_helper_##op(cpu_regs[a->rd], cpu_env, \ + cpu_regs[a->rd], imm); \ + tcg_temp_free(imm); \ + return true; \ + } \ + static bool cat3(trans_, name, _mr)(DisasContext *ctx, \ + cat3(arg_, name, _mr) * a) \ + { \ + TCGv val, mem; \ + mem =3D tcg_temp_new(); \ + val =3D rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \ + gen_helper_##op(cpu_regs[a->rd], cpu_env, \ + cpu_regs[a->rd], val); \ + tcg_temp_free(mem); \ + return true; \ + } + +#define FCONVOP(name, op) \ + static bool trans_##name(DisasContext *ctx, arg_##name * a) \ + { \ + TCGv val, mem; \ + mem =3D tcg_temp_new(); \ + val =3D rx_load_source(ctx, mem, a->ld, MO_32, a->rs); \ + gen_helper_##op(cpu_regs[a->rd], cpu_env, val); \ + tcg_temp_free(mem); \ + return true; \ + } + +FOP(FADD, fadd) +FOP(FSUB, fsub) +FOP(FMUL, fmul) +FOP(FDIV, fdiv) + +/* fcmp #imm, rd */ +static bool trans_FCMP_ir(DisasContext *ctx, arg_FCMP_ir * a) +{ + TCGv imm =3D tcg_const_i32(li(ctx, 0)); + gen_helper_fcmp(cpu_env, cpu_regs[a->rd], imm); + tcg_temp_free(imm); + return true; +} + +/* fcmp dsp[rs], rd */ +/* fcmp rs, rd */ +static bool trans_FCMP_mr(DisasContext *ctx, arg_FCMP_mr *a) +{ + TCGv val, mem; + mem =3D tcg_temp_new(); + val =3D rx_load_source(ctx, mem, a->ld, MO_32, a->rs); + gen_helper_fcmp(cpu_env, cpu_regs[a->rd], val); + tcg_temp_free(mem); + return true; +} + +FCONVOP(FTOI, ftoi) +FCONVOP(ROUND, round) + +/* itof rs, rd */ +/* itof dsp[rs], rd */ +static bool trans_ITOF(DisasContext *ctx, arg_ITOF * a) +{ + TCGv val, mem; + mem =3D tcg_temp_new(); + val =3D rx_load_source(ctx, mem, a->ld, a->mi, a->rs); + gen_helper_itof(cpu_regs[a->rd], cpu_env, val); + tcg_temp_free(mem); + return true; +} + +static void rx_bsetm(TCGv mem, TCGv mask) +{ + TCGv val; + val =3D tcg_temp_new(); + rx_gen_ld(MO_8, val, mem); + tcg_gen_or_i32(val, val, mask); + rx_gen_st(MO_8, val, mem); + tcg_temp_free(val); +} + +static void rx_bclrm(TCGv mem, TCGv mask) +{ + TCGv val; + val =3D tcg_temp_new(); + rx_gen_ld(MO_8, val, mem); + tcg_gen_andc_i32(val, val, mask); + rx_gen_st(MO_8, val, mem); + tcg_temp_free(val); +} + +static void rx_btstm(TCGv mem, TCGv mask) +{ + TCGv val; + val =3D tcg_temp_new(); + rx_gen_ld(MO_8, val, mem); + tcg_gen_and_i32(val, val, mask); + tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, val, 0); + tcg_gen_mov_i32(cpu_psw_z, cpu_psw_c); + tcg_temp_free(val); +} + +static void rx_bnotm(TCGv mem, TCGv mask) +{ + TCGv val; + val =3D tcg_temp_new(); + rx_gen_ld(MO_8, val, mem); + tcg_gen_xor_i32(val, val, mask); + rx_gen_st(MO_8, val, mem); + tcg_temp_free(val); +} + +static void rx_bsetr(TCGv reg, TCGv mask) +{ + tcg_gen_or_i32(reg, reg, mask); +} + +static void rx_bclrr(TCGv reg, TCGv mask) +{ + tcg_gen_andc_i32(reg, reg, mask); +} + +static inline void rx_btstr(TCGv reg, TCGv mask) +{ + TCGv t0; + t0 =3D tcg_temp_new(); + tcg_gen_and_i32(t0, reg, mask); + tcg_gen_setcondi_i32(TCG_COND_NE, cpu_psw_c, t0, 0); + tcg_gen_mov_i32(cpu_psw_z, cpu_psw_c); + tcg_temp_free(t0); +} + +static inline void rx_bnotr(TCGv reg, TCGv mask) +{ + tcg_gen_xor_i32(reg, reg, mask); +} + +#define BITOP(name, op) \ + static bool cat3(trans_, name, _im)(DisasContext *ctx, \ + cat3(arg_, name, _im) * a) \ + { \ + TCGv mask, mem, addr; \ + mem =3D tcg_temp_new(); \ + mask =3D tcg_const_i32(1 << a->imm); \ + addr =3D rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \ + cat3(rx_, op, m)(addr, mask); \ + tcg_temp_free(mask); \ + tcg_temp_free(mem); \ + return true; \ + } \ + static bool cat3(trans_, name, _ir)(DisasContext *ctx, \ + cat3(arg_, name, _ir) * a) \ + { \ + TCGv mask; \ + mask =3D tcg_const_i32(1 << a->imm); \ + cat3(rx_, op, r)(cpu_regs[a->rd], mask); \ + tcg_temp_free(mask); \ + return true; \ + } \ + static bool cat3(trans_, name, _rr)(DisasContext *ctx, \ + cat3(arg_, name, _rr) * a) \ + { \ + TCGv mask, b; \ + mask =3D tcg_const_i32(1); \ + b =3D tcg_temp_new(); \ + tcg_gen_andi_i32(b, cpu_regs[a->rs], 31); \ + tcg_gen_shl_i32(mask, mask, b); \ + cat3(rx_, op, r)(cpu_regs[a->rd], mask); \ + tcg_temp_free(mask); \ + tcg_temp_free(b); \ + return true; \ + } \ + static bool cat3(trans_, name, _rm)(DisasContext *ctx, \ + cat3(arg_, name, _rm) * a) \ + { \ + TCGv mask, mem, addr, b; \ + mask =3D tcg_const_i32(1); \ + b =3D tcg_temp_new(); \ + tcg_gen_andi_i32(b, cpu_regs[a->rd], 7); \ + tcg_gen_shl_i32(mask, mask, b); \ + mem =3D tcg_temp_new(); \ + addr =3D rx_index_addr(ctx, mem, a->ld, MO_8, a->rs); \ + cat3(rx_, op, m)(addr, mask); \ + tcg_temp_free(mem); \ + tcg_temp_free(mask); \ + tcg_temp_free(b); \ + return true; \ + } + +BITOP(BSET, bset) +BITOP(BCLR, bclr) +BITOP(BTST, btst) +BITOP(BNOT, bnot) + +static inline void bmcnd_op(TCGv val, TCGCond cond, int pos) +{ + TCGv bit; + DisasCompare dc; + dc.temp =3D tcg_temp_new(); + bit =3D tcg_temp_new(); + psw_cond(&dc, cond); + tcg_gen_andi_i32(val, val, ~(1 << pos)); + tcg_gen_setcondi_i32(dc.cond, bit, dc.value, 0); + tcg_gen_deposit_i32(val, val, bit, pos, 1); + tcg_temp_free(bit); + tcg_temp_free(dc.temp); + } + +/* bmcnd #imm, dsp[rd] */ +static bool trans_BMCnd_im(DisasContext *ctx, arg_BMCnd_im *a) +{ + TCGv val, mem, addr; + val =3D tcg_temp_new(); + mem =3D tcg_temp_new(); + addr =3D rx_index_addr(ctx, mem, a->ld, MO_8, a->rd); + rx_gen_ld(MO_8, val, addr); + bmcnd_op(val, a->cd, a->imm); + rx_gen_st(MO_8, val, addr); + tcg_temp_free(val); + tcg_temp_free(mem); + return true; +} + +/* bmcond #imm, rd */ +static bool trans_BMCnd_ir(DisasContext *ctx, arg_BMCnd_ir *a) +{ + bmcnd_op(cpu_regs[a->rd], a->cd, a->imm); + return true; +} + +enum { + PSW_C =3D 0, + PSW_Z =3D 1, + PSW_S =3D 2, + PSW_O =3D 3, + PSW_I =3D 8, + PSW_U =3D 9, +}; + +static inline void clrsetpsw(DisasContext *ctx, int cb, int val) +{ + if (cb < 8) { + switch (cb) { + case PSW_C: + tcg_gen_movi_i32(cpu_psw_c, val); + break; + case PSW_Z: + tcg_gen_movi_i32(cpu_psw_z, val =3D=3D 0); + break; + case PSW_S: + tcg_gen_movi_i32(cpu_psw_s, val ? -1 : 0); + break; + case PSW_O: + tcg_gen_movi_i32(cpu_psw_o, val << 31); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "Invalid distination %d", cb); + break; + } + } else if (is_privileged(ctx, 0)) { + switch (cb) { + case PSW_I: + tcg_gen_movi_i32(cpu_psw_i, val); + ctx->base.is_jmp =3D DISAS_UPDATE; + break; + case PSW_U: + tcg_gen_movi_i32(cpu_psw_u, val); + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "Invalid distination %d", cb); + break; + } + } +} + +/* clrpsw psw */ +static bool trans_CLRPSW(DisasContext *ctx, arg_CLRPSW *a) +{ + clrsetpsw(ctx, a->cb, 0); + return true; +} + +/* setpsw psw */ +static bool trans_SETPSW(DisasContext *ctx, arg_SETPSW *a) +{ + clrsetpsw(ctx, a->cb, 1); + return true; +} + +/* mvtipl #imm */ +static bool trans_MVTIPL(DisasContext *ctx, arg_MVTIPL *a) +{ + if (is_privileged(ctx, 1)) { + tcg_gen_movi_i32(cpu_psw_ipl, a->imm); + ctx->base.is_jmp =3D DISAS_UPDATE; + } + return true; +} + +/* mvtc #imm, rd */ +static bool trans_MVTC_i(DisasContext *ctx, arg_MVTC_i *a) +{ + TCGv imm; + + imm =3D tcg_const_i32(a->imm); + move_to_cr(ctx, imm, a->cr); + if (a->cr =3D=3D 0 && is_privileged(ctx, 0)) { + ctx->base.is_jmp =3D DISAS_UPDATE; + } + tcg_temp_free(imm); + return true; +} + +/* mvtc rs, rd */ +static bool trans_MVTC_r(DisasContext *ctx, arg_MVTC_r *a) +{ + move_to_cr(ctx, cpu_regs[a->rs], a->cr); + if (a->cr =3D=3D 0 && is_privileged(ctx, 0)) { + ctx->base.is_jmp =3D DISAS_UPDATE; + } + return true; +} + +/* mvfc rs, rd */ +static bool trans_MVFC(DisasContext *ctx, arg_MVFC *a) +{ + move_from_cr(cpu_regs[a->rd], a->cr, ctx->pc); + return true; +} + +/* rtfi */ +static bool trans_RTFI(DisasContext *ctx, arg_RTFI *a) +{ + TCGv psw; + if (is_privileged(ctx, 1)) { + psw =3D tcg_temp_new(); + tcg_gen_mov_i32(cpu_pc, cpu_bpc); + tcg_gen_mov_i32(psw, cpu_bpsw); + gen_helper_set_psw_rte(cpu_env, psw); + ctx->base.is_jmp =3D DISAS_EXIT; + tcg_temp_free(psw); + } + return true; +} + +/* rte */ +static bool trans_RTE(DisasContext *ctx, arg_RTE *a) +{ + TCGv psw; + if (is_privileged(ctx, 1)) { + psw =3D tcg_temp_new(); + pop(cpu_pc); + pop(psw); + gen_helper_set_psw_rte(cpu_env, psw); + ctx->base.is_jmp =3D DISAS_EXIT; + tcg_temp_free(psw); + } + return true; +} + +/* brk */ +static bool trans_BRK(DisasContext *ctx, arg_BRK *a) +{ + tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); + gen_helper_rxbrk(cpu_env); + ctx->base.is_jmp =3D DISAS_NORETURN; + return true; +} + +/* int #imm */ +static bool trans_INT(DisasContext *ctx, arg_INT *a) +{ + TCGv vec; + + tcg_debug_assert(a->imm < 0x100); + vec =3D tcg_const_i32(a->imm); + tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); + gen_helper_rxint(cpu_env, vec); + tcg_temp_free(vec); + ctx->base.is_jmp =3D DISAS_NORETURN; + return true; +} + +/* wait */ +static bool trans_WAIT(DisasContext *ctx, arg_WAIT *a) +{ + if (is_privileged(ctx, 1)) { + tcg_gen_addi_i32(cpu_pc, cpu_pc, 2); + gen_helper_wait(cpu_env); + } + return true; +} + +static void rx_tr_init_disas_context(DisasContextBase *dcbase, CPUState *c= s) +{ + CPURXState *env =3D cs->env_ptr; + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + ctx->env =3D env; +} + +static void rx_tr_tb_start(DisasContextBase *dcbase, CPUState *cs) +{ +} + +static void rx_tr_insn_start(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + + tcg_gen_insn_start(ctx->base.pc_next); +} + +static bool rx_tr_breakpoint_check(DisasContextBase *dcbase, CPUState *cs, + const CPUBreakpoint *bp) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + + /* We have hit a breakpoint - make sure PC is up-to-date */ + tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); + gen_helper_debug(cpu_env); + ctx->base.is_jmp =3D DISAS_NORETURN; + ctx->base.pc_next +=3D 1; + return true; +} + +static void rx_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + uint32_t insn; + + ctx->pc =3D ctx->base.pc_next; + insn =3D decode_load(ctx); + if (!decode(ctx, insn)) { + gen_helper_raise_illegal_instruction(cpu_env); + } +} + +static void rx_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) +{ + DisasContext *ctx =3D container_of(dcbase, DisasContext, base); + + switch (ctx->base.is_jmp) { + case DISAS_NEXT: + case DISAS_TOO_MANY: + gen_goto_tb(ctx, 0, dcbase->pc_next); + break; + case DISAS_JUMP: + if (ctx->base.singlestep_enabled) { + gen_helper_debug(cpu_env); + } else { + tcg_gen_lookup_and_goto_ptr(); + } + break; + case DISAS_UPDATE: + tcg_gen_movi_i32(cpu_pc, ctx->base.pc_next); + case DISAS_EXIT: + tcg_gen_exit_tb(NULL, 0); + break; + case DISAS_NORETURN: + break; + default: + g_assert_not_reached(); + } +} + +static void rx_tr_disas_log(const DisasContextBase *dcbase, CPUState *cs) +{ + qemu_log("IN:\n"); /* , lookup_symbol(dcbase->pc_first)); */ + log_target_disas(cs, dcbase->pc_first, dcbase->tb->size); +} + +static const TranslatorOps rx_tr_ops =3D { + .init_disas_context =3D rx_tr_init_disas_context, + .tb_start =3D rx_tr_tb_start, + .insn_start =3D rx_tr_insn_start, + .breakpoint_check =3D rx_tr_breakpoint_check, + .translate_insn =3D rx_tr_translate_insn, + .tb_stop =3D rx_tr_tb_stop, + .disas_log =3D rx_tr_disas_log, +}; + +void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_ins= ns) +{ + DisasContext dc; + + translator_loop(&rx_tr_ops, &dc.base, cs, tb, max_insns); +} + +void restore_state_to_opc(CPURXState *env, TranslationBlock *tb, + target_ulong *data) +{ + env->pc =3D data[0]; +} + +#define ALLOC_REGISTER(sym, name) \ + cpu_##sym =3D tcg_global_mem_new_i32(cpu_env, \ + offsetof(CPURXState, sym), name) + +void rx_translate_init(void) +{ + static const char * const regnames[NUM_REGS] =3D { + "R0", "R1", "R2", "R3", "R4", "R5", "R6", "R7", + "R8", "R9", "R10", "R11", "R12", "R13", "R14", "R15" + }; + int i; + + for (i =3D 0; i < NUM_REGS; i++) { + cpu_regs[i] =3D tcg_global_mem_new_i32(cpu_env, + offsetof(CPURXState, regs[i]= ), + regnames[i]); + } + ALLOC_REGISTER(pc, "PC"); + ALLOC_REGISTER(psw_o, "PSW(O)"); + ALLOC_REGISTER(psw_s, "PSW(S)"); + ALLOC_REGISTER(psw_z, "PSW(Z)"); + ALLOC_REGISTER(psw_c, "PSW(C)"); + ALLOC_REGISTER(psw_u, "PSW(U)"); + ALLOC_REGISTER(psw_i, "PSW(I)"); + ALLOC_REGISTER(psw_pm, "PSW(PM)"); + ALLOC_REGISTER(psw_ipl, "PSW(IPL)"); + ALLOC_REGISTER(usp, "USP"); + ALLOC_REGISTER(fpsw, "FPSW"); + ALLOC_REGISTER(bpsw, "BPSW"); + ALLOC_REGISTER(bpc, "BPC"); + ALLOC_REGISTER(isp, "ISP"); + ALLOC_REGISTER(fintv, "FINTV"); + ALLOC_REGISTER(intb, "INTB"); + cpu_acc =3D tcg_global_mem_new_i64(cpu_env, + offsetof(CPURXState, acc), "ACC"); +} diff --git a/target/rx/Makefile.objs b/target/rx/Makefile.objs new file mode 100644 index 0000000000..aa6f2d2d6c --- /dev/null +++ b/target/rx/Makefile.objs @@ -0,0 +1,12 @@ +obj-y +=3D translate.o op_helper.o helper.o cpu.o gdbstub.o disas.o +obj-$(CONFIG_SOFTMMU) +=3D monitor.o + +DECODETREE =3D $(SRC_PATH)/scripts/decodetree.py + +target/rx/decode.inc.c: \ + $(SRC_PATH)/target/rx/insns.decode $(DECODETREE) + $(call quiet-command,\ + $(PYTHON) $(DECODETREE) --varinsnwidth 32 -o $@ $<, "GEN", $(TARGET_DIR= )$@) + +target/rx/translate.o: target/rx/decode.inc.c +target/rx/disas.o: target/rx/decode.inc.c --=20 2.21.1 From nobody Sun May 5 08:48:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; 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[83.59.163.96]) by smtp.gmail.com with ESMTPSA id b202sm4618697wmd.15.2020.03.17.09.36.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Mar 2020 09:36:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6zwkV1x1C+DM5VOWiaa2lkInOLISGYBrNqxqw04s6aU=; b=YE69kze4MDahCTD5f5JMZKNHHAM06cWf3WpHoKAje0gfw4OGAR//QEWP2DWAzqZAJw 1Gu8Bqc/GkqfZZoml3/K3/OO50Kkd+WSU76gIEd7INFjkUWPck+Br/zXS2+F61obP9Hf gsMRyNyknkajwyrznS33ijYrLE++oSAcEIXizjdiZ/elK1hJF2EsJd6fUeP2r/K/p/Bk Aaq6KDPJzeNghc5G8cEQULHKb1z6RkS7HHopDkfQfoKiNwYqIo2X+FQZt4XgER0ZRYl4 TuPIfcpd6MKR1DmNYGf4Xbf+4+XPZS0HXpwLN5tLjNSTm0W+briFZ/QfP9yPzHjOhpFl ZWyQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=6zwkV1x1C+DM5VOWiaa2lkInOLISGYBrNqxqw04s6aU=; b=SV1xeHBiiNlKfGZAQAbyxKKHKcvXBvEFDmyovZcbHi8LOVLar0WHDk3eapUUD+OzNF d5m8vx9HwKLbxTyRiTE4nU8uotpqniTPGQWQmXpCDKwOyQamws+CEDBPlEEsxadXUhyn OPRF4RsnC5YYNRlS0udP5AhTajnGTfFRaWSYGvCD5g48cv/HYA8YmjsORK3cd9oNxH6y mqBcuJ4OLuZZMQC7XOqAaQLtsWjNutoQvICB7cJjva0WCIftRXeKRz9/i5nAvkf2kX9e 3i6BLyzVSLU3LIVQauy4GbJI08a0rWNpTX9JAWj1g6SGN4J+tRglYc+b4/qaCyLW6fT+ 8M5g== X-Gm-Message-State: ANhLgQ0QenzkTHP01BdvxfIAv4h13u8oZNdxPcUzIDY6uK5+6vSODou3 V0ApSFMRIiF6HH3b7i8O1f68PKKR X-Google-Smtp-Source: ADFU+vvKN/O09a/7gGp2MxcsWeqUBwdDEK/lAZ9IV+sNzmTI7qN/uR5LdyldZjO7fCpqv+bL6KmCjA== X-Received: by 2002:a1c:791a:: with SMTP id l26mr126374wme.103.1584462983504; Tue, 17 Mar 2020 09:36:23 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 04/13] target/rx: TCG helpers Date: Tue, 17 Mar 2020 17:36:07 +0100 Message-Id: <20200317163616.30027-5-f4bug@amsat.org> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200317163616.30027-1-f4bug@amsat.org> References: <20200317163616.30027-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::330 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yoshinori Sato , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Yoshinori Sato Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Yoshinori Sato Signed-off-by: Richard Henderson [PMD: Removed tlb_fill, extracted from patch of Yoshinori Sato 'Convert to CPUClass::tlb_fill'] Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20200224141923.82118-6-ysato@users.sourceforge.jp> Acked-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/rx/helper.h | 31 +++ target/rx/helper.c | 149 +++++++++++++ target/rx/op_helper.c | 470 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 650 insertions(+) create mode 100644 target/rx/helper.h create mode 100644 target/rx/helper.c create mode 100644 target/rx/op_helper.c diff --git a/target/rx/helper.h b/target/rx/helper.h new file mode 100644 index 0000000000..f0b7ebbbf7 --- /dev/null +++ b/target/rx/helper.h @@ -0,0 +1,31 @@ +DEF_HELPER_1(raise_illegal_instruction, noreturn, env) +DEF_HELPER_1(raise_access_fault, noreturn, env) +DEF_HELPER_1(raise_privilege_violation, noreturn, env) +DEF_HELPER_1(wait, noreturn, env) +DEF_HELPER_1(debug, noreturn, env) +DEF_HELPER_2(rxint, noreturn, env, i32) +DEF_HELPER_1(rxbrk, noreturn, env) +DEF_HELPER_FLAGS_3(fadd, TCG_CALL_NO_WG, f32, env, f32, f32) +DEF_HELPER_FLAGS_3(fsub, TCG_CALL_NO_WG, f32, env, f32, f32) +DEF_HELPER_FLAGS_3(fmul, TCG_CALL_NO_WG, f32, env, f32, f32) +DEF_HELPER_FLAGS_3(fdiv, TCG_CALL_NO_WG, f32, env, f32, f32) +DEF_HELPER_FLAGS_3(fcmp, TCG_CALL_NO_WG, void, env, f32, f32) +DEF_HELPER_FLAGS_2(ftoi, TCG_CALL_NO_WG, i32, env, f32) +DEF_HELPER_FLAGS_2(round, TCG_CALL_NO_WG, i32, env, f32) +DEF_HELPER_FLAGS_2(itof, TCG_CALL_NO_WG, f32, env, i32) +DEF_HELPER_2(set_fpsw, void, env, i32) +DEF_HELPER_FLAGS_2(racw, TCG_CALL_NO_WG, void, env, i32) +DEF_HELPER_FLAGS_2(set_psw_rte, TCG_CALL_NO_WG, void, env, i32) +DEF_HELPER_FLAGS_2(set_psw, TCG_CALL_NO_WG, void, env, i32) +DEF_HELPER_1(pack_psw, i32, env) +DEF_HELPER_FLAGS_3(div, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_3(divu, TCG_CALL_NO_WG, i32, env, i32, i32) +DEF_HELPER_FLAGS_1(scmpu, TCG_CALL_NO_WG, void, env) +DEF_HELPER_1(smovu, void, env) +DEF_HELPER_1(smovf, void, env) +DEF_HELPER_1(smovb, void, env) +DEF_HELPER_2(sstr, void, env, i32) +DEF_HELPER_FLAGS_2(swhile, TCG_CALL_NO_WG, void, env, i32) +DEF_HELPER_FLAGS_2(suntil, TCG_CALL_NO_WG, void, env, i32) +DEF_HELPER_FLAGS_2(rmpa, TCG_CALL_NO_WG, void, env, i32) +DEF_HELPER_1(satr, void, env) diff --git a/target/rx/helper.c b/target/rx/helper.c new file mode 100644 index 0000000000..a6a337a311 --- /dev/null +++ b/target/rx/helper.c @@ -0,0 +1,149 @@ +/* + * RX emulation + * + * Copyright (c) 2019 Yoshinori Sato + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/bitops.h" +#include "cpu.h" +#include "exec/log.h" +#include "exec/cpu_ldst.h" +#include "sysemu/sysemu.h" +#include "hw/irq.h" + +void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte) +{ + if (env->psw_pm =3D=3D 0) { + env->psw_ipl =3D FIELD_EX32(psw, PSW, IPL); + if (rte) { + /* PSW.PM can write RTE and RTFI */ + env->psw_pm =3D FIELD_EX32(psw, PSW, PM); + } + env->psw_u =3D FIELD_EX32(psw, PSW, U); + env->psw_i =3D FIELD_EX32(psw, PSW, I); + } + env->psw_o =3D FIELD_EX32(psw, PSW, O) << 31; + env->psw_s =3D FIELD_EX32(psw, PSW, S) << 31; + env->psw_z =3D 1 - FIELD_EX32(psw, PSW, Z); + env->psw_c =3D FIELD_EX32(psw, PSW, C); +} + +#define INT_FLAGS (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR) +void rx_cpu_do_interrupt(CPUState *cs) +{ + RXCPU *cpu =3D RXCPU(cs); + CPURXState *env =3D &cpu->env; + int do_irq =3D cs->interrupt_request & INT_FLAGS; + uint32_t save_psw; + + env->in_sleep =3D 0; + + if (env->psw_u) { + env->usp =3D env->regs[0]; + } else { + env->isp =3D env->regs[0]; + } + save_psw =3D rx_cpu_pack_psw(env); + env->psw_pm =3D env->psw_i =3D env->psw_u =3D 0; + + if (do_irq) { + if (do_irq & CPU_INTERRUPT_FIR) { + env->bpc =3D env->pc; + env->bpsw =3D save_psw; + env->pc =3D env->fintv; + env->psw_ipl =3D 15; + cs->interrupt_request &=3D ~CPU_INTERRUPT_FIR; + qemu_set_irq(env->ack, env->ack_irq); + qemu_log_mask(CPU_LOG_INT, "fast interrupt raised\n"); + } else if (do_irq & CPU_INTERRUPT_HARD) { + env->isp -=3D 4; + cpu_stl_data(env, env->isp, save_psw); + env->isp -=3D 4; + cpu_stl_data(env, env->isp, env->pc); + env->pc =3D cpu_ldl_data(env, env->intb + env->ack_irq * 4); + env->psw_ipl =3D env->ack_ipl; + cs->interrupt_request &=3D ~CPU_INTERRUPT_HARD; + qemu_set_irq(env->ack, env->ack_irq); + qemu_log_mask(CPU_LOG_INT, + "interrupt 0x%02x raised\n", env->ack_irq); + } + } else { + uint32_t vec =3D cs->exception_index; + const char *expname =3D "unknown exception"; + + env->isp -=3D 4; + cpu_stl_data(env, env->isp, save_psw); + env->isp -=3D 4; + cpu_stl_data(env, env->isp, env->pc); + + if (vec < 0x100) { + env->pc =3D cpu_ldl_data(env, 0xffffffc0 + vec * 4); + } else { + env->pc =3D cpu_ldl_data(env, env->intb + (vec & 0xff) * 4); + } + switch (vec) { + case 20: + expname =3D "privilege violation"; + break; + case 21: + expname =3D "access exception"; + break; + case 23: + expname =3D "illegal instruction"; + break; + case 25: + expname =3D "fpu exception"; + break; + case 30: + expname =3D "non-maskable interrupt"; + break; + case 0x100 ... 0x1ff: + expname =3D "unconditional trap"; + } + qemu_log_mask(CPU_LOG_INT, "exception 0x%02x [%s] raised\n", + (vec & 0xff), expname); + } + env->regs[0] =3D env->isp; +} + +bool rx_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + RXCPU *cpu =3D RXCPU(cs); + CPURXState *env =3D &cpu->env; + int accept =3D 0; + /* hardware interrupt (Normal) */ + if ((interrupt_request & CPU_INTERRUPT_HARD) && + env->psw_i && (env->psw_ipl < env->req_ipl)) { + env->ack_irq =3D env->req_irq; + env->ack_ipl =3D env->req_ipl; + accept =3D 1; + } + /* hardware interrupt (FIR) */ + if ((interrupt_request & CPU_INTERRUPT_FIR) && + env->psw_i && (env->psw_ipl < 15)) { + accept =3D 1; + } + if (accept) { + rx_cpu_do_interrupt(cs); + return true; + } + return false; +} + +hwaddr rx_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +{ + return addr; +} diff --git a/target/rx/op_helper.c b/target/rx/op_helper.c new file mode 100644 index 0000000000..f89d294f2b --- /dev/null +++ b/target/rx/op_helper.c @@ -0,0 +1,470 @@ +/* + * RX helper functions + * + * Copyright (c) 2019 Yoshinori Sato + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/bitops.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "exec/helper-proto.h" +#include "exec/cpu_ldst.h" +#include "fpu/softfloat.h" + +static inline void QEMU_NORETURN raise_exception(CPURXState *env, int inde= x, + uintptr_t retaddr); + +static void _set_psw(CPURXState *env, uint32_t psw, uint32_t rte) +{ + uint32_t prev_u; + prev_u =3D env->psw_u; + rx_cpu_unpack_psw(env, psw, rte); + if (prev_u !=3D env->psw_u) { + /* switch r0 */ + if (env->psw_u) { + env->isp =3D env->regs[0]; + env->regs[0] =3D env->usp; + } else { + env->usp =3D env->regs[0]; + env->regs[0] =3D env->isp; + } + } +} + +void helper_set_psw(CPURXState *env, uint32_t psw) +{ + _set_psw(env, psw, 0); +} + +void helper_set_psw_rte(CPURXState *env, uint32_t psw) +{ + _set_psw(env, psw, 1); +} + +uint32_t helper_pack_psw(CPURXState *env) +{ + return rx_cpu_pack_psw(env); +} + +#define SET_FPSW(b) \ + do { \ + env->fpsw =3D FIELD_DP32(env->fpsw, FPSW, C ## b, 1); \ + if (!FIELD_EX32(env->fpsw, FPSW, E ## b)) { \ + env->fpsw =3D FIELD_DP32(env->fpsw, FPSW, F ## b, 1); \ + } \ + } while (0) + +/* fp operations */ +static void update_fpsw(CPURXState *env, float32 ret, uintptr_t retaddr) +{ + int xcpt, cause, enable; + + env->psw_z =3D ret & ~(1 << 31); /* mask sign bit */ + env->psw_s =3D ret; + + xcpt =3D get_float_exception_flags(&env->fp_status); + + /* Clear the cause entries */ + env->fpsw =3D FIELD_DP32(env->fpsw, FPSW, CAUSE, 0); + + /* set FPSW */ + if (unlikely(xcpt)) { + if (xcpt & float_flag_invalid) { + SET_FPSW(V); + } + if (xcpt & float_flag_divbyzero) { + SET_FPSW(Z); + } + if (xcpt & float_flag_overflow) { + SET_FPSW(O); + } + if (xcpt & float_flag_underflow) { + SET_FPSW(U); + } + if (xcpt & float_flag_inexact) { + SET_FPSW(X); + } + if ((xcpt & (float_flag_input_denormal + | float_flag_output_denormal)) + && !FIELD_EX32(env->fpsw, FPSW, DN)) { + env->fpsw =3D FIELD_DP32(env->fpsw, FPSW, CE, 1); + } + + /* update FPSW_FLAG_S */ + if (FIELD_EX32(env->fpsw, FPSW, FLAGS) !=3D 0) { + env->fpsw =3D FIELD_DP32(env->fpsw, FPSW, FS, 1); + } + + /* Generate an exception if enabled */ + cause =3D FIELD_EX32(env->fpsw, FPSW, CAUSE); + enable =3D FIELD_EX32(env->fpsw, FPSW, ENABLE); + enable |=3D 1 << 5; /* CE always enabled */ + if (cause & enable) { + raise_exception(env, 21, retaddr); + } + } +} + +void helper_set_fpsw(CPURXState *env, uint32_t val) +{ + static const int roundmode[] =3D { + float_round_nearest_even, + float_round_to_zero, + float_round_up, + float_round_down, + }; + uint32_t fpsw =3D env->fpsw; + fpsw |=3D 0x7fffff03; + val &=3D ~0x80000000; + fpsw &=3D val; + FIELD_DP32(fpsw, FPSW, FS, FIELD_EX32(fpsw, FPSW, FLAGS) !=3D 0); + env->fpsw =3D fpsw; + set_float_rounding_mode(roundmode[FIELD_EX32(env->fpsw, FPSW, RM)], + &env->fp_status); +} + +#define FLOATOP(op, func) \ + float32 helper_##op(CPURXState *env, float32 t0, float32 t1) \ + { \ + float32 ret; \ + ret =3D func(t0, t1, &env->fp_status); \ + update_fpsw(env, *(uint32_t *)&ret, GETPC()); \ + return ret; \ + } + +FLOATOP(fadd, float32_add) +FLOATOP(fsub, float32_sub) +FLOATOP(fmul, float32_mul) +FLOATOP(fdiv, float32_div) + +void helper_fcmp(CPURXState *env, float32 t0, float32 t1) +{ + int st; + st =3D float32_compare(t0, t1, &env->fp_status); + update_fpsw(env, 0, GETPC()); + env->psw_z =3D 1; + env->psw_s =3D env->psw_o =3D 0; + switch (st) { + case float_relation_equal: + env->psw_z =3D 0; + break; + case float_relation_less: + env->psw_s =3D -1; + break; + case float_relation_unordered: + env->psw_o =3D -1; + break; + } +} + +uint32_t helper_ftoi(CPURXState *env, float32 t0) +{ + uint32_t ret; + ret =3D float32_to_int32_round_to_zero(t0, &env->fp_status); + update_fpsw(env, ret, GETPC()); + return ret; +} + +uint32_t helper_round(CPURXState *env, float32 t0) +{ + uint32_t ret; + ret =3D float32_to_int32(t0, &env->fp_status); + update_fpsw(env, ret, GETPC()); + return ret; +} + +float32 helper_itof(CPURXState *env, uint32_t t0) +{ + float32 ret; + ret =3D int32_to_float32(t0, &env->fp_status); + update_fpsw(env, ret, GETPC()); + return ret; +} + +/* string operations */ +void helper_scmpu(CPURXState *env) +{ + uint8_t tmp0, tmp1; + if (env->regs[3] =3D=3D 0) { + return; + } + while (env->regs[3] !=3D 0) { + tmp0 =3D cpu_ldub_data_ra(env, env->regs[1]++, GETPC()); + tmp1 =3D cpu_ldub_data_ra(env, env->regs[2]++, GETPC()); + env->regs[3]--; + if (tmp0 !=3D tmp1 || tmp0 =3D=3D '\0') { + break; + } + } + env->psw_z =3D tmp0 - tmp1; + env->psw_c =3D (tmp0 >=3D tmp1); +} + +static uint32_t (* const cpu_ldufn[])(CPUArchState *env, + target_ulong ptr, + uintptr_t retaddr) =3D { + cpu_ldub_data_ra, cpu_lduw_data_ra, cpu_ldl_data_ra, +}; + +static uint32_t (* const cpu_ldfn[])(CPUArchState *env, + target_ulong ptr, + uintptr_t retaddr) =3D { + cpu_ldub_data_ra, cpu_lduw_data_ra, cpu_ldl_data_ra, +}; + +static void (* const cpu_stfn[])(CPUArchState *env, + target_ulong ptr, + uint32_t val, + uintptr_t retaddr) =3D { + cpu_stb_data_ra, cpu_stw_data_ra, cpu_stl_data_ra, +}; + +void helper_sstr(CPURXState *env, uint32_t sz) +{ + tcg_debug_assert(sz < 3); + while (env->regs[3] !=3D 0) { + cpu_stfn[sz](env, env->regs[1], env->regs[2], GETPC()); + env->regs[1] +=3D 1 << sz; + env->regs[3]--; + } +} + +#define OP_SMOVU 1 +#define OP_SMOVF 0 +#define OP_SMOVB 2 + +static void smov(uint32_t mode, CPURXState *env) +{ + uint8_t tmp; + int dir; + + dir =3D (mode & OP_SMOVB) ? -1 : 1; + while (env->regs[3] !=3D 0) { + tmp =3D cpu_ldub_data_ra(env, env->regs[2], GETPC()); + cpu_stb_data_ra(env, env->regs[1], tmp, GETPC()); + env->regs[1] +=3D dir; + env->regs[2] +=3D dir; + env->regs[3]--; + if ((mode & OP_SMOVU) && tmp =3D=3D 0) { + break; + } + } +} + +void helper_smovu(CPURXState *env) +{ + smov(OP_SMOVU, env); +} + +void helper_smovf(CPURXState *env) +{ + smov(OP_SMOVF, env); +} + +void helper_smovb(CPURXState *env) +{ + smov(OP_SMOVB, env); +} + + +void helper_suntil(CPURXState *env, uint32_t sz) +{ + uint32_t tmp; + tcg_debug_assert(sz < 3); + if (env->regs[3] =3D=3D 0) { + return ; + } + while (env->regs[3] !=3D 0) { + tmp =3D cpu_ldufn[sz](env, env->regs[1], GETPC()); + env->regs[1] +=3D 1 << sz; + env->regs[3]--; + if (tmp =3D=3D env->regs[2]) { + break; + } + } + env->psw_z =3D tmp - env->regs[2]; + env->psw_c =3D (tmp <=3D env->regs[2]); +} + +void helper_swhile(CPURXState *env, uint32_t sz) +{ + uint32_t tmp; + tcg_debug_assert(sz < 3); + if (env->regs[3] =3D=3D 0) { + return ; + } + while (env->regs[3] !=3D 0) { + tmp =3D cpu_ldufn[sz](env, env->regs[1], GETPC()); + env->regs[1] +=3D 1 << sz; + env->regs[3]--; + if (tmp !=3D env->regs[2]) { + break; + } + } + env->psw_z =3D env->regs[3]; + env->psw_c =3D (tmp <=3D env->regs[2]); +} + +/* accumlator operations */ +void helper_rmpa(CPURXState *env, uint32_t sz) +{ + uint64_t result_l, prev; + int32_t result_h; + int64_t tmp0, tmp1; + + if (env->regs[3] =3D=3D 0) { + return; + } + result_l =3D env->regs[5]; + result_l <<=3D 32; + result_l |=3D env->regs[4]; + result_h =3D env->regs[6]; + env->psw_o =3D 0; + + while (env->regs[3] !=3D 0) { + tmp0 =3D cpu_ldfn[sz](env, env->regs[1], GETPC()); + tmp1 =3D cpu_ldfn[sz](env, env->regs[2], GETPC()); + tmp0 *=3D tmp1; + prev =3D result_l; + result_l +=3D tmp0; + /* carry / bollow */ + if (tmp0 < 0) { + if (prev > result_l) { + result_h--; + } + } else { + if (prev < result_l) { + result_h++; + } + } + + env->regs[1] +=3D 1 << sz; + env->regs[2] +=3D 1 << sz; + } + env->psw_s =3D result_h; + env->psw_o =3D (result_h !=3D 0 && result_h !=3D -1) << 31; + env->regs[6] =3D result_h; + env->regs[5] =3D result_l >> 32; + env->regs[4] =3D result_l & 0xffffffff; +} + +void helper_racw(CPURXState *env, uint32_t imm) +{ + int64_t acc; + acc =3D env->acc; + acc <<=3D (imm + 1); + acc +=3D 0x0000000080000000LL; + if (acc > 0x00007fff00000000LL) { + acc =3D 0x00007fff00000000LL; + } else if (acc < -0x800000000000LL) { + acc =3D -0x800000000000LL; + } else { + acc &=3D 0xffffffff00000000LL; + } + env->acc =3D acc; +} + +void helper_satr(CPURXState *env) +{ + if (env->psw_o >> 31) { + if ((int)env->psw_s < 0) { + env->regs[6] =3D 0x00000000; + env->regs[5] =3D 0x7fffffff; + env->regs[4] =3D 0xffffffff; + } else { + env->regs[6] =3D 0xffffffff; + env->regs[5] =3D 0x80000000; + env->regs[4] =3D 0x00000000; + } + } +} + +/* div */ +uint32_t helper_div(CPURXState *env, uint32_t num, uint32_t den) +{ + uint32_t ret =3D num; + if (!((num =3D=3D INT_MIN && den =3D=3D -1) || den =3D=3D 0)) { + ret =3D (int32_t)num / (int32_t)den; + env->psw_o =3D 0; + } else { + env->psw_o =3D -1; + } + return ret; +} + +uint32_t helper_divu(CPURXState *env, uint32_t num, uint32_t den) +{ + uint32_t ret =3D num; + if (den !=3D 0) { + ret =3D num / den; + env->psw_o =3D 0; + } else { + env->psw_o =3D -1; + } + return ret; +} + +/* exception */ +static inline void QEMU_NORETURN raise_exception(CPURXState *env, int inde= x, + uintptr_t retaddr) +{ + CPUState *cs =3D env_cpu(env); + + cs->exception_index =3D index; + cpu_loop_exit_restore(cs, retaddr); +} + +void QEMU_NORETURN helper_raise_privilege_violation(CPURXState *env) +{ + raise_exception(env, 20, GETPC()); +} + +void QEMU_NORETURN helper_raise_access_fault(CPURXState *env) +{ + raise_exception(env, 21, GETPC()); +} + +void QEMU_NORETURN helper_raise_illegal_instruction(CPURXState *env) +{ + raise_exception(env, 23, GETPC()); +} + +void QEMU_NORETURN helper_wait(CPURXState *env) +{ + CPUState *cs =3D env_cpu(env); + + cs->halted =3D 1; + env->in_sleep =3D 1; + raise_exception(env, EXCP_HLT, 0); +} + +void QEMU_NORETURN helper_debug(CPURXState *env) +{ + CPUState *cs =3D env_cpu(env); + + cs->exception_index =3D EXCP_DEBUG; + cpu_loop_exit(cs); +} + +void QEMU_NORETURN helper_rxint(CPURXState *env, uint32_t vec) +{ + raise_exception(env, 0x100 + vec, 0); +} + +void QEMU_NORETURN helper_rxbrk(CPURXState *env) +{ + raise_exception(env, 0x100, 0); +} --=20 2.21.1 From nobody Sun May 5 08:48:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=amsat.org ARC-Seal: i=1; a=rsa-sha256; t=1584464085; cv=none; d=zohomail.com; s=zohoarc; b=P+dTt0RQR3aSl/dD+/AgiejAA2YkIRqPZciUmWQTcrokKq/mKFy3i5g71FWyLY9JU7x2PFVIERXKN6oGPWpV3wIFv+fEG3CnGdSYNLuAIaZms3nrjKLa5Ec9G54HgM4+AbEdp+w61mjSJzE+cETpDIiIru3eIGze2vOiMAaBtTg= ARC-Message-Signature: i=1; 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[83.59.163.96]) by smtp.gmail.com with ESMTPSA id b202sm4618697wmd.15.2020.03.17.09.36.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Mar 2020 09:36:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kKVEzrX1Vwvdev5eqhm8qk4hduJr2cOR2lHMb0uawjY=; b=s0uW48HIkFWFWpJWfLzb9+LzW/0dniWPFsVOtsEHeJ6bOImtlTxcT+kJD5BbDlPD45 oZTKJT885xwNddPXVPRXtVXOl4W1c7HAj1aX20WGCT5DiVPpdJX2yr9bb/GImpBcQJcs HQ7ScABdOv9V6Ii0RCSQwrHxG/bJZDCCMYKkYaoLaslDCeakXZGaqA5UERmoimAv0KJt +E094xS7sbiNFXAmSSeGXO0tTaOHJuMnMYfMEEd6oKUZCX+QwTZs8jX7gAyggtg+98v8 vq5HIDHPHiBtl3MoyBiRUh3zyHpqtf0H5li48rhCF9+7wohYkMcLoQN++xOuC3yt3frA 4YCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=kKVEzrX1Vwvdev5eqhm8qk4hduJr2cOR2lHMb0uawjY=; b=XfGgPDvJ8njGjo6LLAmo7nByCTjvPPdmLTMqzJMVQx12crFnSds1IPjGNj8ZL/ldZw RhLJyB+ChPoRYT4yUpm9A4l4opsDMRld9ZKsuSR4H5vM67dvVRU/SbBRodDQuet6Jkrg 0IxAFHN2DRxrouFeBiPDzeg8OQzaS+uAPfAgeoCfrqjKqE0Et9LgPJkJITP3WQJ5e5ks WsAgEaaTKmBEsxAsnwqdHUkF8bvb8hkjVHW5O6+X/DD6hgVC98PQ4o0dClXaNvrQkZQK /NaozxbmtzvcBPDDuAHHWLTdzcA/Ztyg4ocyGecRsAwJEoC2o1ga2cn/0xVFTDU0QXPk u+rA== X-Gm-Message-State: ANhLgQ2vc94/Oe1GPimNMFxngUyDgmSlgLT4Qi57ZoaBhOlTvTVJvuM5 Zol2V/soy4my3wWHxpdZJErN4Xna X-Google-Smtp-Source: ADFU+vv8dyP2QjiSnITMRQeUaD5FrwEHjniWpiJi2bb6jS/WONKThb8oN+6IQAbfT9hEVLo6SR5xNw== X-Received: by 2002:a5d:4dc7:: with SMTP id f7mr6769695wru.72.1584462985075; Tue, 17 Mar 2020 09:36:25 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 05/13] target/rx: CPU definitions Date: Tue, 17 Mar 2020 17:36:08 +0100 Message-Id: <20200317163616.30027-6-f4bug@amsat.org> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200317163616.30027-1-f4bug@amsat.org> References: <20200317163616.30027-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42c X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yoshinori Sato , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Igor Mammedov , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Yoshinori Sato Reviewed-by: Richard Henderson Signed-off-by: Yoshinori Sato Signed-off-by: Richard Henderson [PMD: Use newer QOM style, split cpu-qom.h, restrict access to extable array, use rx_cpu_tlb_fill() extracted from patch of Yoshinori Sato 'Convert to CPUClass::tlb_fill', call cpu_reset after qemu_init_vcpu, make rx_crname a function] Signed-off-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Igor Mammedov Message-Id: <20200224141923.82118-7-ysato@users.sourceforge.jp> Acked-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/rx/cpu-param.h | 30 ++++++ target/rx/cpu-qom.h | 54 ++++++++++ target/rx/cpu.h | 180 ++++++++++++++++++++++++++++++++ target/rx/cpu.c | 226 ++++++++++++++++++++++++++++++++++++++++ target/rx/gdbstub.c | 112 ++++++++++++++++++++ target/rx/translate.c | 17 ++- gdb-xml/rx-core.xml | 70 +++++++++++++ target/rx/Makefile.objs | 1 - 8 files changed, 684 insertions(+), 6 deletions(-) create mode 100644 target/rx/cpu-param.h create mode 100644 target/rx/cpu-qom.h create mode 100644 target/rx/cpu.h create mode 100644 target/rx/cpu.c create mode 100644 target/rx/gdbstub.c create mode 100644 gdb-xml/rx-core.xml diff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h new file mode 100644 index 0000000000..b156ad1ca0 --- /dev/null +++ b/target/rx/cpu-param.h @@ -0,0 +1,30 @@ +/* + * RX cpu parameters + * + * Copyright (c) 2019 Yoshinori Sato + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef RX_CPU_PARAM_H +#define RX_CPU_PARAM_H + +#define TARGET_LONG_BITS 32 +#define TARGET_PAGE_BITS 12 + +#define TARGET_PHYS_ADDR_SPACE_BITS 32 +#define TARGET_VIRT_ADDR_SPACE_BITS 32 + +#define NB_MMU_MODES 1 + +#endif diff --git a/target/rx/cpu-qom.h b/target/rx/cpu-qom.h new file mode 100644 index 0000000000..d64e89ca99 --- /dev/null +++ b/target/rx/cpu-qom.h @@ -0,0 +1,54 @@ +/* + * RX CPU + * + * Copyright (c) 2019 Yoshinori Sato + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef RX_CPU_QOM_H +#define RX_CPU_QOM_H + +#include "hw/core/cpu.h" + +#define TYPE_RX_CPU "rx-cpu" + +#define TYPE_RX62N_CPU RX_CPU_TYPE_NAME("rx62n") + +#define RXCPU_CLASS(klass) \ + OBJECT_CLASS_CHECK(RXCPUClass, (klass), TYPE_RX_CPU) +#define RXCPU(obj) \ + OBJECT_CHECK(RXCPU, (obj), TYPE_RX_CPU) +#define RXCPU_GET_CLASS(obj) \ + OBJECT_GET_CLASS(RXCPUClass, (obj), TYPE_RX_CPU) + +/* + * RXCPUClass: + * @parent_realize: The parent class' realize handler. + * @parent_reset: The parent class' reset handler. + * + * A RX CPU model. + */ +typedef struct RXCPUClass { + /*< private >*/ + CPUClass parent_class; + /*< public >*/ + + DeviceRealize parent_realize; + void (*parent_reset)(CPUState *cpu); + +} RXCPUClass; + +#define CPUArchState struct CPURXState + +#endif diff --git a/target/rx/cpu.h b/target/rx/cpu.h new file mode 100644 index 0000000000..b716fc5789 --- /dev/null +++ b/target/rx/cpu.h @@ -0,0 +1,180 @@ +/* + * RX emulation definition + * + * Copyright (c) 2019 Yoshinori Sato + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef RX_CPU_H +#define RX_CPU_H + +#include "qemu/bitops.h" +#include "qemu-common.h" +#include "hw/registerfields.h" +#include "cpu-qom.h" + +#include "exec/cpu-defs.h" + +/* PSW define */ +REG32(PSW, 0) +FIELD(PSW, C, 0, 1) +FIELD(PSW, Z, 1, 1) +FIELD(PSW, S, 2, 1) +FIELD(PSW, O, 3, 1) +FIELD(PSW, I, 16, 1) +FIELD(PSW, U, 17, 1) +FIELD(PSW, PM, 20, 1) +FIELD(PSW, IPL, 24, 4) + +/* FPSW define */ +REG32(FPSW, 0) +FIELD(FPSW, RM, 0, 2) +FIELD(FPSW, CV, 2, 1) +FIELD(FPSW, CO, 3, 1) +FIELD(FPSW, CZ, 4, 1) +FIELD(FPSW, CU, 5, 1) +FIELD(FPSW, CX, 6, 1) +FIELD(FPSW, CE, 7, 1) +FIELD(FPSW, CAUSE, 2, 6) +FIELD(FPSW, DN, 8, 1) +FIELD(FPSW, EV, 10, 1) +FIELD(FPSW, EO, 11, 1) +FIELD(FPSW, EZ, 12, 1) +FIELD(FPSW, EU, 13, 1) +FIELD(FPSW, EX, 14, 1) +FIELD(FPSW, ENABLE, 10, 5) +FIELD(FPSW, FV, 26, 1) +FIELD(FPSW, FO, 27, 1) +FIELD(FPSW, FZ, 28, 1) +FIELD(FPSW, FU, 29, 1) +FIELD(FPSW, FX, 30, 1) +FIELD(FPSW, FLAGS, 26, 4) +FIELD(FPSW, FS, 31, 1) + +enum { + NUM_REGS =3D 16, +}; + +typedef struct CPURXState { + /* CPU registers */ + uint32_t regs[NUM_REGS]; /* general registers */ + uint32_t psw_o; /* O bit of status register */ + uint32_t psw_s; /* S bit of status register */ + uint32_t psw_z; /* Z bit of status register */ + uint32_t psw_c; /* C bit of status register */ + uint32_t psw_u; + uint32_t psw_i; + uint32_t psw_pm; + uint32_t psw_ipl; + uint32_t bpsw; /* backup status */ + uint32_t bpc; /* backup pc */ + uint32_t isp; /* global base register */ + uint32_t usp; /* vector base register */ + uint32_t pc; /* program counter */ + uint32_t intb; /* interrupt vector */ + uint32_t fintv; + uint32_t fpsw; + uint64_t acc; + + /* Fields up to this point are cleared by a CPU reset */ + struct {} end_reset_fields; + + /* Internal use */ + uint32_t in_sleep; + uint32_t req_irq; /* Requested interrupt no (hard) */ + uint32_t req_ipl; /* Requested interrupt level */ + uint32_t ack_irq; /* execute irq */ + uint32_t ack_ipl; /* execute ipl */ + float_status fp_status; + qemu_irq ack; /* Interrupt acknowledge */ +} CPURXState; + +/* + * RXCPU: + * @env: #CPURXState + * + * A RX CPU + */ +struct RXCPU { + /*< private >*/ + CPUState parent_obj; + /*< public >*/ + + CPUNegativeOffsetState neg; + CPURXState env; +}; + +typedef struct RXCPU RXCPU; +typedef RXCPU ArchCPU; + +#define ENV_OFFSET offsetof(RXCPU, env) + +#define RX_CPU_TYPE_SUFFIX "-" TYPE_RX_CPU +#define RX_CPU_TYPE_NAME(model) model RX_CPU_TYPE_SUFFIX +#define CPU_RESOLVING_TYPE TYPE_RX_CPU + +const char *rx_crname(uint8_t cr); +void rx_cpu_do_interrupt(CPUState *cpu); +bool rx_cpu_exec_interrupt(CPUState *cpu, int int_req); +void rx_cpu_dump_state(CPUState *cpu, FILE *f, int flags); +int rx_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); +int rx_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); +hwaddr rx_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); + +void rx_translate_init(void); +int cpu_rx_signal_handler(int host_signum, void *pinfo, + void *puc); + +void rx_cpu_list(void); +void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte); + +#define cpu_signal_handler cpu_rx_signal_handler +#define cpu_list rx_cpu_list + +#include "exec/cpu-all.h" + +#define CPU_INTERRUPT_SOFT CPU_INTERRUPT_TGT_INT_0 +#define CPU_INTERRUPT_FIR CPU_INTERRUPT_TGT_INT_1 + +#define RX_CPU_IRQ 0 +#define RX_CPU_FIR 1 + +static inline void cpu_get_tb_cpu_state(CPURXState *env, target_ulong *pc, + target_ulong *cs_base, uint32_t *f= lags) +{ + *pc =3D env->pc; + *cs_base =3D 0; + *flags =3D FIELD_DP32(0, PSW, PM, env->psw_pm); +} + +static inline int cpu_mmu_index(CPURXState *env, bool ifetch) +{ + return 0; +} + +static inline uint32_t rx_cpu_pack_psw(CPURXState *env) +{ + uint32_t psw =3D 0; + psw =3D FIELD_DP32(psw, PSW, IPL, env->psw_ipl); + psw =3D FIELD_DP32(psw, PSW, PM, env->psw_pm); + psw =3D FIELD_DP32(psw, PSW, U, env->psw_u); + psw =3D FIELD_DP32(psw, PSW, I, env->psw_i); + psw =3D FIELD_DP32(psw, PSW, O, env->psw_o >> 31); + psw =3D FIELD_DP32(psw, PSW, S, env->psw_s >> 31); + psw =3D FIELD_DP32(psw, PSW, Z, env->psw_z =3D=3D 0); + psw =3D FIELD_DP32(psw, PSW, C, env->psw_c); + return psw; +} + +#endif /* RX_CPU_H */ diff --git a/target/rx/cpu.c b/target/rx/cpu.c new file mode 100644 index 0000000000..9c224a273c --- /dev/null +++ b/target/rx/cpu.c @@ -0,0 +1,226 @@ +/* + * QEMU RX CPU + * + * Copyright (c) 2019 Yoshinori Sato + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/qemu-print.h" +#include "qapi/error.h" +#include "cpu.h" +#include "qemu-common.h" +#include "migration/vmstate.h" +#include "exec/exec-all.h" +#include "hw/loader.h" +#include "fpu/softfloat.h" + +static void rx_cpu_set_pc(CPUState *cs, vaddr value) +{ + RXCPU *cpu =3D RXCPU(cs); + + cpu->env.pc =3D value; +} + +static void rx_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb) +{ + RXCPU *cpu =3D RXCPU(cs); + + cpu->env.pc =3D tb->pc; +} + +static bool rx_cpu_has_work(CPUState *cs) +{ + return cs->interrupt_request & + (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR); +} + +static void rx_cpu_reset(CPUState *s) +{ + RXCPU *cpu =3D RXCPU(s); + RXCPUClass *rcc =3D RXCPU_GET_CLASS(cpu); + CPURXState *env =3D &cpu->env; + uint32_t *resetvec; + + rcc->parent_reset(s); + + memset(env, 0, offsetof(CPURXState, end_reset_fields)); + + resetvec =3D rom_ptr(0xfffffffc, 4); + if (resetvec) { + /* In the case of kernel, it is ignored because it is not set. */ + env->pc =3D ldl_p(resetvec); + } + rx_cpu_unpack_psw(env, 0, 1); + env->regs[0] =3D env->isp =3D env->usp =3D 0; + env->fpsw =3D 0; + set_flush_to_zero(1, &env->fp_status); + set_flush_inputs_to_zero(1, &env->fp_status); +} + +static void rx_cpu_list_entry(gpointer data, gpointer user_data) +{ + ObjectClass *oc =3D data; + + qemu_printf(" %s\n", object_class_get_name(oc)); +} + +void rx_cpu_list(void) +{ + GSList *list; + list =3D object_class_get_list_sorted(TYPE_RX_CPU, false); + qemu_printf("Available CPUs:\n"); + g_slist_foreach(list, rx_cpu_list_entry, NULL); + g_slist_free(list); +} + +static ObjectClass *rx_cpu_class_by_name(const char *cpu_model) +{ + ObjectClass *oc; + char *typename; + + oc =3D object_class_by_name(cpu_model); + if (oc !=3D NULL && object_class_dynamic_cast(oc, TYPE_RX_CPU) !=3D NU= LL && + !object_class_is_abstract(oc)) { + return oc; + } + typename =3D g_strdup_printf(RX_CPU_TYPE_NAME("%s"), cpu_model); + oc =3D object_class_by_name(typename); + g_free(typename); + if (oc !=3D NULL && object_class_is_abstract(oc)) { + oc =3D NULL; + } + + return oc; +} + +static void rx_cpu_realize(DeviceState *dev, Error **errp) +{ + CPUState *cs =3D CPU(dev); + RXCPUClass *rcc =3D RXCPU_GET_CLASS(dev); + Error *local_err =3D NULL; + + cpu_exec_realizefn(cs, &local_err); + if (local_err !=3D NULL) { + error_propagate(errp, local_err); + return; + } + + qemu_init_vcpu(cs); + cpu_reset(cs); + + rcc->parent_realize(dev, errp); +} + +static void rx_cpu_set_irq(void *opaque, int no, int request) +{ + RXCPU *cpu =3D opaque; + CPUState *cs =3D CPU(cpu); + int irq =3D request & 0xff; + + static const int mask[] =3D { + [RX_CPU_IRQ] =3D CPU_INTERRUPT_HARD, + [RX_CPU_FIR] =3D CPU_INTERRUPT_FIR, + }; + if (irq) { + cpu->env.req_irq =3D irq; + cpu->env.req_ipl =3D (request >> 8) & 0x0f; + cpu_interrupt(cs, mask[no]); + } else { + cpu_reset_interrupt(cs, mask[no]); + } +} + +static void rx_cpu_disas_set_info(CPUState *cpu, disassemble_info *info) +{ + info->mach =3D bfd_mach_rx; + info->print_insn =3D print_insn_rx; +} + +static bool rx_cpu_tlb_fill(CPUState *cs, vaddr addr, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + uint32_t address, physical, prot; + + /* Linear mapping */ + address =3D physical =3D addr & TARGET_PAGE_MASK; + prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; + tlb_set_page(cs, address, physical, prot, mmu_idx, TARGET_PAGE_SIZE); + return true; +} + +static void rx_cpu_init(Object *obj) +{ + CPUState *cs =3D CPU(obj); + RXCPU *cpu =3D RXCPU(obj); + CPURXState *env =3D &cpu->env; + + cpu_set_cpustate_pointers(cpu); + cs->env_ptr =3D env; + qdev_init_gpio_in(DEVICE(cpu), rx_cpu_set_irq, 2); +} + +static void rx_cpu_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + CPUClass *cc =3D CPU_CLASS(klass); + RXCPUClass *rcc =3D RXCPU_CLASS(klass); + + device_class_set_parent_realize(dc, rx_cpu_realize, + &rcc->parent_realize); + + rcc->parent_reset =3D cc->reset; + cc->reset =3D rx_cpu_reset; + + cc->class_by_name =3D rx_cpu_class_by_name; + cc->has_work =3D rx_cpu_has_work; + cc->do_interrupt =3D rx_cpu_do_interrupt; + cc->cpu_exec_interrupt =3D rx_cpu_exec_interrupt; + cc->dump_state =3D rx_cpu_dump_state; + cc->set_pc =3D rx_cpu_set_pc; + cc->synchronize_from_tb =3D rx_cpu_synchronize_from_tb; + cc->gdb_read_register =3D rx_cpu_gdb_read_register; + cc->gdb_write_register =3D rx_cpu_gdb_write_register; + cc->get_phys_page_debug =3D rx_cpu_get_phys_page_debug; + cc->disas_set_info =3D rx_cpu_disas_set_info; + cc->tcg_initialize =3D rx_translate_init; + cc->tlb_fill =3D rx_cpu_tlb_fill; + + cc->gdb_num_core_regs =3D 26; + cc->gdb_core_xml_file =3D "rx-core.xml"; +} + +static const TypeInfo rx_cpu_info =3D { + .name =3D TYPE_RX_CPU, + .parent =3D TYPE_CPU, + .instance_size =3D sizeof(RXCPU), + .instance_init =3D rx_cpu_init, + .abstract =3D true, + .class_size =3D sizeof(RXCPUClass), + .class_init =3D rx_cpu_class_init, +}; + +static const TypeInfo rx62n_rx_cpu_info =3D { + .name =3D TYPE_RX62N_CPU, + .parent =3D TYPE_RX_CPU, +}; + +static void rx_cpu_register_types(void) +{ + type_register_static(&rx_cpu_info); + type_register_static(&rx62n_rx_cpu_info); +} + +type_init(rx_cpu_register_types) diff --git a/target/rx/gdbstub.c b/target/rx/gdbstub.c new file mode 100644 index 0000000000..d76ca52e82 --- /dev/null +++ b/target/rx/gdbstub.c @@ -0,0 +1,112 @@ +/* + * RX gdb server stub + * + * Copyright (c) 2019 Yoshinori Sato + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "cpu.h" +#include "exec/gdbstub.h" + +int rx_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + RXCPU *cpu =3D RXCPU(cs); + CPURXState *env =3D &cpu->env; + + switch (n) { + case 0 ... 15: + return gdb_get_regl(mem_buf, env->regs[n]); + case 16: + return gdb_get_regl(mem_buf, (env->psw_u) ? env->regs[0] : env->us= p); + case 17: + return gdb_get_regl(mem_buf, (!env->psw_u) ? env->regs[0] : env->i= sp); + case 18: + return gdb_get_regl(mem_buf, rx_cpu_pack_psw(env)); + case 19: + return gdb_get_regl(mem_buf, env->pc); + case 20: + return gdb_get_regl(mem_buf, env->intb); + case 21: + return gdb_get_regl(mem_buf, env->bpsw); + case 22: + return gdb_get_regl(mem_buf, env->bpc); + case 23: + return gdb_get_regl(mem_buf, env->fintv); + case 24: + return gdb_get_regl(mem_buf, env->fpsw); + case 25: + return 0; + } + return 0; +} + +int rx_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) +{ + RXCPU *cpu =3D RXCPU(cs); + CPURXState *env =3D &cpu->env; + uint32_t psw; + switch (n) { + case 0 ... 15: + env->regs[n] =3D ldl_p(mem_buf); + if (n =3D=3D 0) { + if (env->psw_u) { + env->usp =3D env->regs[0]; + } else { + env->isp =3D env->regs[0]; + } + } + break; + case 16: + env->usp =3D ldl_p(mem_buf); + if (env->psw_u) { + env->regs[0] =3D ldl_p(mem_buf); + } + break; + case 17: + env->isp =3D ldl_p(mem_buf); + if (!env->psw_u) { + env->regs[0] =3D ldl_p(mem_buf); + } + break; + case 18: + psw =3D ldl_p(mem_buf); + rx_cpu_unpack_psw(env, psw, 1); + break; + case 19: + env->pc =3D ldl_p(mem_buf); + break; + case 20: + env->intb =3D ldl_p(mem_buf); + break; + case 21: + env->bpsw =3D ldl_p(mem_buf); + break; + case 22: + env->bpc =3D ldl_p(mem_buf); + break; + case 23: + env->fintv =3D ldl_p(mem_buf); + break; + case 24: + env->fpsw =3D ldl_p(mem_buf); + break; + case 25: + return 8; + default: + return 0; + } + + return 4; +} diff --git a/target/rx/translate.c b/target/rx/translate.c index 6b52424d0f..b3d7305f23 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -41,10 +41,17 @@ typedef struct DisasCompare { TCGCond cond; } DisasCompare; =20 -const char rx_crname[][6] =3D { - "psw", "pc", "usp", "fpsw", "", "", "", "", - "bpsw", "bpc", "isp", "fintv", "intb", "", "", "", -}; +const char *rx_crname(uint8_t cr) +{ + static const char *cr_names[] =3D { + "psw", "pc", "usp", "fpsw", "", "", "", "", + "bpsw", "bpc", "isp", "fintv", "intb", "", "", "" + }; + if (cr >=3D ARRAY_SIZE(cr_names)) { + return "illegal"; + } + return cr_names[cr]; +} =20 /* Target-specific values for dc->base.is_jmp. */ #define DISAS_JUMP DISAS_TARGET_0 @@ -365,7 +372,7 @@ static void move_to_cr(DisasContext *ctx, TCGv val, int= cr) if (cr >=3D 8 && !is_privileged(ctx, 0)) { /* Some control registers can only be written in privileged mode. = */ qemu_log_mask(LOG_GUEST_ERROR, - "disallow control register write %s", rx_crname[cr]); + "disallow control register write %s", rx_crname(cr)); return; } z =3D tcg_const_i32(0); diff --git a/gdb-xml/rx-core.xml b/gdb-xml/rx-core.xml new file mode 100644 index 0000000000..b5aa9ac4a8 --- /dev/null +++ b/gdb-xml/rx-core.xml @@ -0,0 +1,70 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/target/rx/Makefile.objs b/target/rx/Makefile.objs index aa6f2d2d6c..a0018d5bc5 100644 --- a/target/rx/Makefile.objs +++ b/target/rx/Makefile.objs @@ -1,5 +1,4 @@ obj-y +=3D translate.o op_helper.o helper.o cpu.o gdbstub.o disas.o -obj-$(CONFIG_SOFTMMU) +=3D monitor.o =20 DECODETREE =3D $(SRC_PATH)/scripts/decodetree.py =20 --=20 2.21.1 From nobody Sun May 5 08:48:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[83.59.163.96]) by smtp.gmail.com with ESMTPSA id b202sm4618697wmd.15.2020.03.17.09.36.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Mar 2020 09:36:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GkpjOwNVSoO+iFZINKRcTDdCxSh50B6NkZiRsIuGtV8=; b=DtxhHEeAhySdpV1NkFgSygaNAAvZ/ckF9K6MMssJHl+0P1VKrY1GLOJfHfGoqMgQVe UpNs7ElhkziMHRh98h2d8Aa2Gaszg0u51kz/IcFoaYZs6h9OOXQIFVcRkb+hvL0GSDPq gvpCuSmZkGujSliNpypI1GS3B94MutGNqNTDvznxMAnqHC+IgZZgTIOqkuC2shYj7pD1 nubZjm0IM5wCge6Y7SbFEAmUDZDmz9L96kEMyIS5db6yflXyyRKd1Lv1eBYHYUvcF4Du qkY3coKqOtZ+ksD89qyY132mhxxbZD6+mYK4m72wR19VXwzqpH2AQ/CFdEco1Qk+h5ZT v/Tw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=GkpjOwNVSoO+iFZINKRcTDdCxSh50B6NkZiRsIuGtV8=; b=shBQcZkwqAKpm8lmkjCfH9RIC3j2j+duciLICKo/EgvlR+KkXMpGityNnMQHGqP0oI uvsUA9o8REz7uKrC6RZRFu7kWZsd1SwgqynpGFzS5HOVCZjP8HUloMWlg4rKDt4hD6nX 81YGSHS6ixNmMpBTF/SGrIJPiu+9lRUdReeRJcVoH+kAO19VRWrG2CcJa65D/b3/WRfO BTyFyCn4D+s+Im3/xGdtBGbOLaK5jELbVEAcWWVTS3h7V4PRYVDLoVHXzpFaO7BdpmDZ B225jZDHPJbpVeTRPvqueWsTYiZ/nncg1SCbN3psWOnyzqeoSMbQeX85tz9o/0cM3fWa KT3w== X-Gm-Message-State: ANhLgQ0FSKva/f97ls9ILUaN0w/uX6mJATa8ffkgymnyOaILOJOHRmWl x47H2ei6T+SAmCwznTAGGVQagKQ7 X-Google-Smtp-Source: ADFU+vsmSCrUFk0Wd2eE55azxGc8C62rsMOaDXOKf9WLv4fQ64/FmUVY/rctXyTqbsdkatWtNiiBAA== X-Received: by 2002:a1c:b4c6:: with SMTP id d189mr151305wmf.132.1584462986379; Tue, 17 Mar 2020 09:36:26 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 06/13] target/rx: RX disassembler Date: Tue, 17 Mar 2020 17:36:09 +0100 Message-Id: <20200317163616.30027-7-f4bug@amsat.org> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200317163616.30027-1-f4bug@amsat.org> References: <20200317163616.30027-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::335 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yoshinori Sato , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Yoshinori Sato Reviewed-by: Richard Henderson Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Yoshinori Sato Signed-off-by: Richard Henderson Message-Id: <20200224141923.82118-8-ysato@users.sourceforge.jp> Acked-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- include/disas/dis-asm.h | 5 + target/rx/disas.c | 1480 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 1485 insertions(+) create mode 100644 target/rx/disas.c diff --git a/include/disas/dis-asm.h b/include/disas/dis-asm.h index f87f468809..c5f9fa08ab 100644 --- a/include/disas/dis-asm.h +++ b/include/disas/dis-asm.h @@ -226,6 +226,10 @@ enum bfd_architecture #define bfd_mach_nios2r2 2 bfd_arch_lm32, /* Lattice Mico32 */ #define bfd_mach_lm32 1 + bfd_arch_rx, /* Renesas RX */ +#define bfd_mach_rx 0x75 +#define bfd_mach_rx_v2 0x76 +#define bfd_mach_rx_v3 0x77 bfd_arch_last }; #define bfd_mach_s390_31 31 @@ -436,6 +440,7 @@ int print_insn_little_nios2 (bfd_vma, disassemble_i= nfo*); int print_insn_xtensa (bfd_vma, disassemble_info*); int print_insn_riscv32 (bfd_vma, disassemble_info*); int print_insn_riscv64 (bfd_vma, disassemble_info*); +int print_insn_rx(bfd_vma, disassemble_info *); =20 #if 0 /* Fetch the disassembler for a given BFD, if that support is available. = */ diff --git a/target/rx/disas.c b/target/rx/disas.c new file mode 100644 index 0000000000..04cdfdc567 --- /dev/null +++ b/target/rx/disas.c @@ -0,0 +1,1480 @@ +/* + * Renesas RX Disassembler + * + * Copyright (c) 2019 Yoshinori Sato + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "disas/dis-asm.h" +#include "qemu/bitops.h" +#include "cpu.h" + +typedef struct DisasContext { + disassemble_info *dis; + uint32_t addr; + uint32_t pc; +} DisasContext; + + +static uint32_t decode_load_bytes(DisasContext *ctx, uint32_t insn, + int i, int n) +{ + bfd_byte buf; + while (++i <=3D n) { + ctx->dis->read_memory_func(ctx->addr++, &buf, 1, ctx->dis); + insn |=3D buf << (32 - i * 8); + } + return insn; +} + +static int32_t li(DisasContext *ctx, int sz) +{ + int32_t addr; + bfd_byte buf[4]; + addr =3D ctx->addr; + + switch (sz) { + case 1: + ctx->addr +=3D 1; + ctx->dis->read_memory_func(addr, buf, 1, ctx->dis); + return (int8_t)buf[0]; + case 2: + ctx->addr +=3D 2; + ctx->dis->read_memory_func(addr, buf, 2, ctx->dis); + return ldsw_le_p(buf); + case 3: + ctx->addr +=3D 3; + ctx->dis->read_memory_func(addr, buf, 3, ctx->dis); + return (int8_t)buf[2] << 16 | lduw_le_p(buf); + case 0: + ctx->addr +=3D 4; + ctx->dis->read_memory_func(addr, buf, 4, ctx->dis); + return ldl_le_p(buf); + default: + g_assert_not_reached(); + } +} + +static int bdsp_s(DisasContext *ctx, int d) +{ + /* + * 0 -> 8 + * 1 -> 9 + * 2 -> 10 + * 3 -> 3 + * : + * 7 -> 7 + */ + if (d < 3) { + d +=3D 8; + } + return d; +} + +/* Include the auto-generated decoder. */ +#include "decode.inc.c" + +#define prt(...) (ctx->dis->fprintf_func)((ctx->dis->stream), __VA_ARGS__) + +#define RX_MEMORY_BYTE 0 +#define RX_MEMORY_WORD 1 +#define RX_MEMORY_LONG 2 + +#define RX_IM_BYTE 0 +#define RX_IM_WORD 1 +#define RX_IM_LONG 2 +#define RX_IM_UWORD 3 + +static const char size[] =3D {'b', 'w', 'l'}; +static const char cond[][4] =3D { + "eq", "ne", "c", "nc", "gtu", "leu", "pz", "n", + "ge", "lt", "gt", "le", "o", "no", "ra", "f" +}; +static const char psw[] =3D { + 'c', 'z', 's', 'o', 0, 0, 0, 0, + 'i', 'u', 0, 0, 0, 0, 0, 0, +}; + +static uint32_t rx_index_addr(int ld, int size, DisasContext *ctx) +{ + bfd_byte buf[2]; + switch (ld) { + case 0: + return 0; + case 1: + ctx->dis->read_memory_func(ctx->addr, buf, 1, ctx->dis); + ctx->addr +=3D 1; + return ((uint8_t)buf[0]) << size; + case 2: + ctx->dis->read_memory_func(ctx->addr, buf, 2, ctx->dis); + ctx->addr +=3D 2; + return lduw_le_p(buf) << size; + } + g_assert_not_reached(); +} + +static void operand(DisasContext *ctx, int ld, int mi, int rs, int rd) +{ + int dsp; + static const char sizes[][4] =3D {".b", ".w", ".l", ".uw", ".ub"}; + if (ld < 3) { + switch (mi) { + case 4: + /* dsp[rs].ub */ + dsp =3D rx_index_addr(ld, RX_MEMORY_BYTE, ctx); + break; + case 3: + /* dsp[rs].uw */ + dsp =3D rx_index_addr(ld, RX_MEMORY_WORD, ctx); + break; + default: + /* dsp[rs].b */ + /* dsp[rs].w */ + /* dsp[rs].l */ + dsp =3D rx_index_addr(ld, mi, ctx); + break; + } + if (dsp > 0) { + prt("%d", dsp); + } + prt("[r%d]%s", rs, sizes[mi]); + } else { + prt("r%d", rs); + } + prt(", r%d", rd); +} + +static void prt_ir(DisasContext *ctx, const char *insn, int imm, int rd) +{ + if (imm < 0x100) { + prt("%s\t#%d, r%d", insn, imm, rd); + } else { + prt("%s\t#0x%08x, r%d", insn, imm, rd); + } +} + +/* mov.[bwl] rs,dsp:[rd] */ +static bool trans_MOV_rm(DisasContext *ctx, arg_MOV_rm *a) +{ + if (a->dsp > 0) { + prt("mov.%c\tr%d,%d[r%d]", + size[a->sz], a->rs, a->dsp << a->sz, a->rd); + } else { + prt("mov.%c\tr%d,[r%d]", + size[a->sz], a->rs, a->rd); + } + return true; +} + +/* mov.[bwl] dsp:[rs],rd */ +static bool trans_MOV_mr(DisasContext *ctx, arg_MOV_mr *a) +{ + if (a->dsp > 0) { + prt("mov.%c\t%d[r%d], r%d", + size[a->sz], a->dsp << a->sz, a->rs, a->rd); + } else { + prt("mov.%c\t[r%d], r%d", + size[a->sz], a->rs, a->rd); + } + return true; +} + +/* mov.l #uimm4,rd */ +/* mov.l #uimm8,rd */ +/* mov.l #imm,rd */ +static bool trans_MOV_ir(DisasContext *ctx, arg_MOV_ir *a) +{ + prt_ir(ctx, "mov.l", a->imm, a->rd); + return true; +} + +/* mov.[bwl] #uimm8,dsp:[rd] */ +/* mov #imm, dsp:[rd] */ +static bool trans_MOV_im(DisasContext *ctx, arg_MOV_im *a) +{ + if (a->dsp > 0) { + prt("mov.%c\t#%d,%d[r%d]", + size[a->sz], a->imm, a->dsp << a->sz, a->rd); + } else { + prt("mov.%c\t#%d,[r%d]", + size[a->sz], a->imm, a->rd); + } + return true; +} + +/* mov.[bwl] [ri,rb],rd */ +static bool trans_MOV_ar(DisasContext *ctx, arg_MOV_ar *a) +{ + prt("mov.%c\t[r%d,r%d], r%d", size[a->sz], a->ri, a->rb, a->rd); + return true; +} + +/* mov.[bwl] rd,[ri,rb] */ +static bool trans_MOV_ra(DisasContext *ctx, arg_MOV_ra *a) +{ + prt("mov.%c\tr%d, [r%d, r%d]", size[a->sz], a->rs, a->ri, a->rb); + return true; +} + + +/* mov.[bwl] dsp:[rs],dsp:[rd] */ +/* mov.[bwl] rs,dsp:[rd] */ +/* mov.[bwl] dsp:[rs],rd */ +/* mov.[bwl] rs,rd */ +static bool trans_MOV_mm(DisasContext *ctx, arg_MOV_mm *a) +{ + int dsp; + + prt("mov.%c\t", size[a->sz]); + if (a->lds =3D=3D 3 && a->ldd =3D=3D 3) { + /* mov.[bwl] rs,rd */ + prt("r%d, r%d", a->rs, a->rd); + return true; + } + if (a->lds =3D=3D 3) { + prt("r%d, ", a->rd); + dsp =3D rx_index_addr(a->ldd, a->sz, ctx); + if (dsp > 0) { + prt("%d", dsp); + } + prt("[r%d]", a->rs); + } else if (a->ldd =3D=3D 3) { + dsp =3D rx_index_addr(a->lds, a->sz, ctx); + if (dsp > 0) { + prt("%d", dsp); + } + prt("[r%d], r%d", a->rs, a->rd); + } else { + dsp =3D rx_index_addr(a->lds, a->sz, ctx); + if (dsp > 0) { + prt("%d", dsp); + } + prt("[r%d], ", a->rs); + dsp =3D rx_index_addr(a->ldd, a->sz, ctx); + if (dsp > 0) { + prt("%d", dsp); + } + prt("[r%d]", a->rd); + } + return true; +} + +/* mov.[bwl] rs,[rd+] */ +/* mov.[bwl] rs,[-rd] */ +static bool trans_MOV_rp(DisasContext *ctx, arg_MOV_rp *a) +{ + prt("mov.%c\tr%d, ", size[a->sz], a->rs); + prt((a->ad =3D=3D 0) ? "[r%d+]" : "[-r%d]", a->rd); + return true; +} + +/* mov.[bwl] [rd+],rs */ +/* mov.[bwl] [-rd],rs */ +static bool trans_MOV_pr(DisasContext *ctx, arg_MOV_pr *a) +{ + prt("mov.%c\t", size[a->sz]); + prt((a->ad =3D=3D 0) ? "[r%d+]" : "[-r%d]", a->rd); + prt(", r%d", a->rs); + return true; +} + +/* movu.[bw] dsp5:[rs],rd */ +static bool trans_MOVU_mr(DisasContext *ctx, arg_MOVU_mr *a) +{ + if (a->dsp > 0) { + prt("movu.%c\t%d[r%d], r%d", size[a->sz], + a->dsp << a->sz, a->rs, a->rd); + } else { + prt("movu.%c\t[r%d], r%d", size[a->sz], a->rs, a->rd); + } + return true; +} + +/* movu.[bw] rs,rd */ +static bool trans_MOVU_rr(DisasContext *ctx, arg_MOVU_rr *a) +{ + prt("movu.%c\tr%d, r%d", size[a->sz], a->rs, a->rd); + return true; +} + +/* movu.[bw] [ri,rb],rd */ +static bool trans_MOVU_ar(DisasContext *ctx, arg_MOVU_ar *a) +{ + prt("mov.%c\t[r%d,r%d], r%d", size[a->sz], a->ri, a->rb, a->rd); + return true; +} + +/* movu.[bw] [rs+],rd */ +/* movu.[bw] [-rs],rd */ +static bool trans_MOVU_pr(DisasContext *ctx, arg_MOVU_pr *a) +{ + prt("movu.%c\t", size[a->sz]); + prt((a->ad =3D=3D 0) ? "[r%d+]" : "[-r%d]", a->rd); + prt(", r%d", a->rs); + return true; +} + +/* pop rd */ +static bool trans_POP(DisasContext *ctx, arg_POP *a) +{ + prt("pop\tr%d", a->rd); + return true; +} + +/* popc rx */ +static bool trans_POPC(DisasContext *ctx, arg_POPC *a) +{ + prt("pop\tr%s", rx_crname(a->cr)); + return true; +} + +/* popm rd-rd2 */ +static bool trans_POPM(DisasContext *ctx, arg_POPM *a) +{ + prt("popm\tr%d-r%d", a->rd, a->rd2); + return true; +} + +/* push rs */ +static bool trans_PUSH_r(DisasContext *ctx, arg_PUSH_r *a) +{ + prt("push\tr%d", a->rs); + return true; +} + +/* push dsp[rs] */ +static bool trans_PUSH_m(DisasContext *ctx, arg_PUSH_m *a) +{ + prt("push\t"); + int dsp =3D rx_index_addr(a->ld, a->sz, ctx); + if (dsp > 0) { + prt("%d", dsp); + } + prt("[r%d]", a->rs); + return true; +} + +/* pushc rx */ +static bool trans_PUSHC(DisasContext *ctx, arg_PUSHC *a) +{ + prt("push\t%s", rx_crname(a->cr)); + return true; +} + +/* pushm rs-rs2*/ +static bool trans_PUSHM(DisasContext *ctx, arg_PUSHM *a) +{ + prt("pushm\tr%d-r%d", a->rs, a->rs2); + return true; +} + +/* xchg rs,rd */ +static bool trans_XCHG_rr(DisasContext *ctx, arg_XCHG_rr *a) +{ + prt("xchg\tr%d, r%d", a->rs, a->rd); + return true; +} +/* xchg dsp[rs].,rd */ +static bool trans_XCHG_mr(DisasContext *ctx, arg_XCHG_mr *a) +{ + int dsp; + static const char msize[][4] =3D { + "b", "w", "l", "ub", "uw", + }; + + prt("xchg\t"); + dsp =3D rx_index_addr(a->ld, a->mi, ctx); + if (dsp > 0) { + prt("%d", dsp); + } + prt("[r%d].%s, r%d", a->rs, msize[a->mi], a->rd); + return true; +} + +/* stz #imm,rd */ +static bool trans_STZ(DisasContext *ctx, arg_STZ *a) +{ + prt_ir(ctx, "stz", a->imm, a->rd); + return true; +} + +/* stnz #imm,rd */ +static bool trans_STNZ(DisasContext *ctx, arg_STNZ *a) +{ + prt_ir(ctx, "stnz", a->imm, a->rd); + return true; +} + +/* rtsd #imm */ +static bool trans_RTSD_i(DisasContext *ctx, arg_RTSD_i *a) +{ + prt("rtsd\t#%d", a->imm << 2); + return true; +} + +/* rtsd #imm, rd-rd2 */ +static bool trans_RTSD_irr(DisasContext *ctx, arg_RTSD_irr *a) +{ + prt("rtsd\t#%d, r%d - r%d", a->imm << 2, a->rd, a->rd2); + return true; +} + +/* and #uimm:4, rd */ +/* and #imm, rd */ +static bool trans_AND_ir(DisasContext *ctx, arg_AND_ir *a) +{ + prt_ir(ctx, "and", a->imm, a->rd); + return true; +} + +/* and dsp[rs], rd */ +/* and rs,rd */ +static bool trans_AND_mr(DisasContext *ctx, arg_AND_mr *a) +{ + prt("and\t"); + operand(ctx, a->ld, a->mi, a->rs, a->rd); + return true; +} + +/* and rs,rs2,rd */ +static bool trans_AND_rrr(DisasContext *ctx, arg_AND_rrr *a) +{ + prt("and\tr%d,r%d, r%d", a->rs, a->rs2, a->rd); + return true; +} + +/* or #uimm:4, rd */ +/* or #imm, rd */ +static bool trans_OR_ir(DisasContext *ctx, arg_OR_ir *a) +{ + prt_ir(ctx, "or", a->imm, a->rd); + return true; +} + +/* or dsp[rs], rd */ +/* or rs,rd */ +static bool trans_OR_mr(DisasContext *ctx, arg_OR_mr *a) +{ + prt("or\t"); + operand(ctx, a->ld, a->mi, a->rs, a->rd); + return true; +} + +/* or rs,rs2,rd */ +static bool trans_OR_rrr(DisasContext *ctx, arg_OR_rrr *a) +{ + prt("or\tr%d, r%d, r%d", a->rs, a->rs2, a->rd); + return true; +} + +/* xor #imm, rd */ +static bool trans_XOR_ir(DisasContext *ctx, arg_XOR_ir *a) +{ + prt_ir(ctx, "xor", a->imm, a->rd); + return true; +} + +/* xor dsp[rs], rd */ +/* xor rs,rd */ +static bool trans_XOR_mr(DisasContext *ctx, arg_XOR_mr *a) +{ + prt("xor\t"); + operand(ctx, a->ld, a->mi, a->rs, a->rd); + return true; +} + +/* tst #imm, rd */ +static bool trans_TST_ir(DisasContext *ctx, arg_TST_ir *a) +{ + prt_ir(ctx, "tst", a->imm, a->rd); + return true; +} + +/* tst dsp[rs], rd */ +/* tst rs, rd */ +static bool trans_TST_mr(DisasContext *ctx, arg_TST_mr *a) +{ + prt("tst\t"); + operand(ctx, a->ld, a->mi, a->rs, a->rd); + return true; +} + +/* not rd */ +/* not rs, rd */ +static bool trans_NOT_rr(DisasContext *ctx, arg_NOT_rr *a) +{ + prt("not\t"); + if (a->rs !=3D a->rd) { + prt("r%d, ", a->rs); + } + prt("r%d", a->rd); + return true; +} + +/* neg rd */ +/* neg rs, rd */ +static bool trans_NEG_rr(DisasContext *ctx, arg_NEG_rr *a) +{ + prt("neg\t"); + if (a->rs !=3D a->rd) { + prt("r%d, ", a->rs); + } + prt("r%d", a->rd); + return true; +} + +/* adc #imm, rd */ +static bool trans_ADC_ir(DisasContext *ctx, arg_ADC_ir *a) +{ + prt_ir(ctx, "adc", a->imm, a->rd); + return true; +} + +/* adc rs, rd */ +static bool trans_ADC_rr(DisasContext *ctx, arg_ADC_rr *a) +{ + prt("adc\tr%d, r%d", a->rs, a->rd); + return true; +} + +/* adc dsp[rs], rd */ +static bool trans_ADC_mr(DisasContext *ctx, arg_ADC_mr *a) +{ + int dsp; + prt("adc\t"); + dsp =3D rx_index_addr(a->ld, 2, ctx); + if (dsp > 0) { + prt("%d", dsp); + } + prt("[r%d], r%d", a->rs, a->rd); + return true; +} + +/* add #uimm4, rd */ +/* add #imm, rs, rd */ +static bool trans_ADD_irr(DisasContext *ctx, arg_ADD_irr *a) +{ + if (a->imm < 0x10 && a->rs2 =3D=3D a->rd) { + prt("add\t#%d, r%d", a->imm, a->rd); + } else { + prt("add\t#0x%08x, r%d, r%d", a->imm, a->rs2, a->rd); + } + return true; +} + +/* add rs, rd */ +/* add dsp[rs], rd */ +static bool trans_ADD_mr(DisasContext *ctx, arg_ADD_mr *a) +{ + prt("add\t"); + operand(ctx, a->ld, a->mi, a->rs, a->rd); + return true; +} + +/* add rs, rs2, rd */ +static bool trans_ADD_rrr(DisasContext *ctx, arg_ADD_rrr *a) +{ + prt("add\tr%d, r%d, r%d", a->rs, a->rs2, a->rd); + return true; +} + +/* cmp #imm4, rd */ +/* cmp #imm8, rd */ +/* cmp #imm, rs2 */ +static bool trans_CMP_ir(DisasContext *ctx, arg_CMP_ir *a) +{ + prt_ir(ctx, "cmp", a->imm, a->rs2); + return true; +} + +/* cmp rs, rs2 */ +/* cmp dsp[rs], rs2 */ +static bool trans_CMP_mr(DisasContext *ctx, arg_CMP_mr *a) +{ + prt("cmp\t"); + operand(ctx, a->ld, a->mi, a->rs, a->rd); + return true; +} + +/* sub #imm4, rd */ +static bool trans_SUB_ir(DisasContext *ctx, arg_SUB_ir *a) +{ + prt("sub\t#%d, r%d", a->imm, a->rd); + return true; +} + +/* sub rs, rd */ +/* sub dsp[rs], rd */ +static bool trans_SUB_mr(DisasContext *ctx, arg_SUB_mr *a) +{ + prt("sub\t"); + operand(ctx, a->ld, a->mi, a->rs, a->rd); + return true; +} + +/* sub rs, rs2, rd */ +static bool trans_SUB_rrr(DisasContext *ctx, arg_SUB_rrr *a) +{ + prt("sub\tr%d, r%d, r%d", a->rs, a->rs2, a->rd); + return true; +} + +/* sbb rs, rd */ +static bool trans_SBB_rr(DisasContext *ctx, arg_SBB_rr *a) +{ + prt("sbb\tr%d, r%d", a->rs, a->rd); + return true; +} + +/* sbb dsp[rs], rd */ +static bool trans_SBB_mr(DisasContext *ctx, arg_SBB_mr *a) +{ + prt("sbb\t"); + operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd); + return true; +} + +/* abs rd */ +/* abs rs, rd */ +static bool trans_ABS_rr(DisasContext *ctx, arg_ABS_rr *a) +{ + prt("abs\t"); + if (a->rs =3D=3D a->rd) { + prt("r%d", a->rd); + } else { + prt("r%d, r%d", a->rs, a->rd); + } + return true; +} + +/* max #imm, rd */ +static bool trans_MAX_ir(DisasContext *ctx, arg_MAX_ir *a) +{ + prt_ir(ctx, "max", a->imm, a->rd); + return true; +} + +/* max rs, rd */ +/* max dsp[rs], rd */ +static bool trans_MAX_mr(DisasContext *ctx, arg_MAX_mr *a) +{ + prt("max\t"); + operand(ctx, a->ld, a->mi, a->rs, a->rd); + return true; +} + +/* min #imm, rd */ +static bool trans_MIN_ir(DisasContext *ctx, arg_MIN_ir *a) +{ + prt_ir(ctx, "min", a->imm, a->rd); + return true; +} + +/* min rs, rd */ +/* min dsp[rs], rd */ +static bool trans_MIN_mr(DisasContext *ctx, arg_MIN_mr *a) +{ + prt("max\t"); + operand(ctx, a->ld, a->mi, a->rs, a->rd); + return true; +} + +/* mul #uimm4, rd */ +/* mul #imm, rd */ +static bool trans_MUL_ir(DisasContext *ctx, arg_MUL_ir *a) +{ + prt_ir(ctx, "mul", a->imm, a->rd); + return true; +} + +/* mul rs, rd */ +/* mul dsp[rs], rd */ +static bool trans_MUL_mr(DisasContext *ctx, arg_MUL_mr *a) +{ + prt("mul\t"); + operand(ctx, a->ld, a->mi, a->rs, a->rd); + return true; +} + +/* mul rs, rs2, rd */ +static bool trans_MUL_rrr(DisasContext *ctx, arg_MUL_rrr *a) +{ + prt("mul\tr%d,r%d,r%d", a->rs, a->rs2, a->rd); + return true; +} + +/* emul #imm, rd */ +static bool trans_EMUL_ir(DisasContext *ctx, arg_EMUL_ir *a) +{ + prt_ir(ctx, "emul", a->imm, a->rd); + return true; +} + +/* emul rs, rd */ +/* emul dsp[rs], rd */ +static bool trans_EMUL_mr(DisasContext *ctx, arg_EMUL_mr *a) +{ + prt("emul\t"); + operand(ctx, a->ld, a->mi, a->rs, a->rd); + return true; +} + +/* emulu #imm, rd */ +static bool trans_EMULU_ir(DisasContext *ctx, arg_EMULU_ir *a) +{ + prt_ir(ctx, "emulu", a->imm, a->rd); + return true; +} + +/* emulu rs, rd */ +/* emulu dsp[rs], rd */ +static bool trans_EMULU_mr(DisasContext *ctx, arg_EMULU_mr *a) +{ + prt("emulu\t"); + operand(ctx, a->ld, a->mi, a->rs, a->rd); + return true; +} + +/* div #imm, rd */ +static bool trans_DIV_ir(DisasContext *ctx, arg_DIV_ir *a) +{ + prt_ir(ctx, "div", a->imm, a->rd); + return true; +} + +/* div rs, rd */ +/* div dsp[rs], rd */ +static bool trans_DIV_mr(DisasContext *ctx, arg_DIV_mr *a) +{ + prt("div\t"); + operand(ctx, a->ld, a->mi, a->rs, a->rd); + return true; +} + +/* divu #imm, rd */ +static bool trans_DIVU_ir(DisasContext *ctx, arg_DIVU_ir *a) +{ + prt_ir(ctx, "divu", a->imm, a->rd); + return true; +} + +/* divu rs, rd */ +/* divu dsp[rs], rd */ +static bool trans_DIVU_mr(DisasContext *ctx, arg_DIVU_mr *a) +{ + prt("divu\t"); + operand(ctx, a->ld, a->mi, a->rs, a->rd); + return true; +} + + +/* shll #imm:5, rd */ +/* shll #imm:5, rs, rd */ +static bool trans_SHLL_irr(DisasContext *ctx, arg_SHLL_irr *a) +{ + prt("shll\t#%d, ", a->imm); + if (a->rs2 !=3D a->rd) { + prt("r%d, ", a->rs2); + } + prt("r%d", a->rd); + return true; +} + +/* shll rs, rd */ +static bool trans_SHLL_rr(DisasContext *ctx, arg_SHLL_rr *a) +{ + prt("shll\tr%d, r%d", a->rs, a->rd); + return true; +} + +/* shar #imm:5, rd */ +/* shar #imm:5, rs, rd */ +static bool trans_SHAR_irr(DisasContext *ctx, arg_SHAR_irr *a) +{ + prt("shar\t#%d,", a->imm); + if (a->rs2 !=3D a->rd) { + prt("r%d, ", a->rs2); + } + prt("r%d", a->rd); + return true; +} + +/* shar rs, rd */ +static bool trans_SHAR_rr(DisasContext *ctx, arg_SHAR_rr *a) +{ + prt("shar\tr%d, r%d", a->rs, a->rd); + return true; +} + +/* shlr #imm:5, rd */ +/* shlr #imm:5, rs, rd */ +static bool trans_SHLR_irr(DisasContext *ctx, arg_SHLR_irr *a) +{ + prt("shlr\t#%d, ", a->imm); + if (a->rs2 !=3D a->rd) { + prt("r%d, ", a->rs2); + } + prt("r%d", a->rd); + return true; +} + +/* shlr rs, rd */ +static bool trans_SHLR_rr(DisasContext *ctx, arg_SHLR_rr *a) +{ + prt("shlr\tr%d, r%d", a->rs, a->rd); + return true; +} + +/* rolc rd */ +static bool trans_ROLC(DisasContext *ctx, arg_ROLC *a) +{ + prt("rorc\tr%d", a->rd); + return true; +} + +/* rorc rd */ +static bool trans_RORC(DisasContext *ctx, arg_RORC *a) +{ + prt("rorc\tr%d", a->rd); + return true; +} + +/* rotl #imm, rd */ +static bool trans_ROTL_ir(DisasContext *ctx, arg_ROTL_ir *a) +{ + prt("rotl\t#%d, r%d", a->imm, a->rd); + return true; +} + +/* rotl rs, rd */ +static bool trans_ROTL_rr(DisasContext *ctx, arg_ROTL_rr *a) +{ + prt("rotl\tr%d, r%d", a->rs, a->rd); + return true; +} + +/* rotr #imm, rd */ +static bool trans_ROTR_ir(DisasContext *ctx, arg_ROTR_ir *a) +{ + prt("rotr\t#%d, r%d", a->imm, a->rd); + return true; +} + +/* rotr rs, rd */ +static bool trans_ROTR_rr(DisasContext *ctx, arg_ROTR_rr *a) +{ + prt("rotr\tr%d, r%d", a->rs, a->rd); + return true; +} + +/* revl rs, rd */ +static bool trans_REVL(DisasContext *ctx, arg_REVL *a) +{ + prt("revl\tr%d, r%d", a->rs, a->rd); + return true; +} + +/* revw rs, rd */ +static bool trans_REVW(DisasContext *ctx, arg_REVW *a) +{ + prt("revw\tr%d, r%d", a->rs, a->rd); + return true; +} + +/* conditional branch helper */ +static void rx_bcnd_main(DisasContext *ctx, int cd, int len, int dst) +{ + static const char sz[] =3D {'s', 'b', 'w', 'a'}; + prt("b%s.%c\t%08x", cond[cd], sz[len - 1], ctx->pc + dst); +} + +/* beq dsp:3 / bne dsp:3 */ +/* beq dsp:8 / bne dsp:8 */ +/* bc dsp:8 / bnc dsp:8 */ +/* bgtu dsp:8 / bleu dsp:8 */ +/* bpz dsp:8 / bn dsp:8 */ +/* bge dsp:8 / blt dsp:8 */ +/* bgt dsp:8 / ble dsp:8 */ +/* bo dsp:8 / bno dsp:8 */ +/* beq dsp:16 / bne dsp:16 */ +static bool trans_BCnd(DisasContext *ctx, arg_BCnd *a) +{ + rx_bcnd_main(ctx, a->cd, a->sz, a->dsp); + return true; +} + +/* bra dsp:3 */ +/* bra dsp:8 */ +/* bra dsp:16 */ +/* bra dsp:24 */ +static bool trans_BRA(DisasContext *ctx, arg_BRA *a) +{ + rx_bcnd_main(ctx, 14, a->sz, a->dsp); + return true; +} + +/* bra rs */ +static bool trans_BRA_l(DisasContext *ctx, arg_BRA_l *a) +{ + prt("bra.l\tr%d", a->rd); + return true; +} + +/* jmp rs */ +static bool trans_JMP(DisasContext *ctx, arg_JMP *a) +{ + prt("jmp\tr%d", a->rs); + return true; +} + +/* jsr rs */ +static bool trans_JSR(DisasContext *ctx, arg_JSR *a) +{ + prt("jsr\tr%d", a->rs); + return true; +} + +/* bsr dsp:16 */ +/* bsr dsp:24 */ +static bool trans_BSR(DisasContext *ctx, arg_BSR *a) +{ + static const char sz[] =3D {'w', 'a'}; + prt("bsr.%c\t%08x", sz[a->sz - 3], ctx->pc + a->dsp); + return true; +} + +/* bsr rs */ +static bool trans_BSR_l(DisasContext *ctx, arg_BSR_l *a) +{ + prt("bsr.l\tr%d", a->rd); + return true; +} + +/* rts */ +static bool trans_RTS(DisasContext *ctx, arg_RTS *a) +{ + prt("rts"); + return true; +} + +/* nop */ +static bool trans_NOP(DisasContext *ctx, arg_NOP *a) +{ + prt("nop"); + return true; +} + +/* scmpu */ +static bool trans_SCMPU(DisasContext *ctx, arg_SCMPU *a) +{ + prt("scmpu"); + return true; +} + +/* smovu */ +static bool trans_SMOVU(DisasContext *ctx, arg_SMOVU *a) +{ + prt("smovu"); + return true; +} + +/* smovf */ +static bool trans_SMOVF(DisasContext *ctx, arg_SMOVF *a) +{ + prt("smovf"); + return true; +} + +/* smovb */ +static bool trans_SMOVB(DisasContext *ctx, arg_SMOVB *a) +{ + prt("smovb"); + return true; +} + +/* suntile */ +static bool trans_SUNTIL(DisasContext *ctx, arg_SUNTIL *a) +{ + prt("suntil.%c", size[a->sz]); + return true; +} + +/* swhile */ +static bool trans_SWHILE(DisasContext *ctx, arg_SWHILE *a) +{ + prt("swhile.%c", size[a->sz]); + return true; +} +/* sstr */ +static bool trans_SSTR(DisasContext *ctx, arg_SSTR *a) +{ + prt("sstr.%c", size[a->sz]); + return true; +} + +/* rmpa */ +static bool trans_RMPA(DisasContext *ctx, arg_RMPA *a) +{ + prt("rmpa.%c", size[a->sz]); + return true; +} + +/* mulhi rs,rs2 */ +static bool trans_MULHI(DisasContext *ctx, arg_MULHI *a) +{ + prt("mulhi\tr%d,r%d", a->rs, a->rs2); + return true; +} + +/* mullo rs,rs2 */ +static bool trans_MULLO(DisasContext *ctx, arg_MULLO *a) +{ + prt("mullo\tr%d, r%d", a->rs, a->rs2); + return true; +} + +/* machi rs,rs2 */ +static bool trans_MACHI(DisasContext *ctx, arg_MACHI *a) +{ + prt("machi\tr%d, r%d", a->rs, a->rs2); + return true; +} + +/* maclo rs,rs2 */ +static bool trans_MACLO(DisasContext *ctx, arg_MACLO *a) +{ + prt("maclo\tr%d, r%d", a->rs, a->rs2); + return true; +} + +/* mvfachi rd */ +static bool trans_MVFACHI(DisasContext *ctx, arg_MVFACHI *a) +{ + prt("mvfachi\tr%d", a->rd); + return true; +} + +/* mvfacmi rd */ +static bool trans_MVFACMI(DisasContext *ctx, arg_MVFACMI *a) +{ + prt("mvfacmi\tr%d", a->rd); + return true; +} + +/* mvtachi rs */ +static bool trans_MVTACHI(DisasContext *ctx, arg_MVTACHI *a) +{ + prt("mvtachi\tr%d", a->rs); + return true; +} + +/* mvtaclo rs */ +static bool trans_MVTACLO(DisasContext *ctx, arg_MVTACLO *a) +{ + prt("mvtaclo\tr%d", a->rs); + return true; +} + +/* racw #imm */ +static bool trans_RACW(DisasContext *ctx, arg_RACW *a) +{ + prt("racw\t#%d", a->imm + 1); + return true; +} + +/* sat rd */ +static bool trans_SAT(DisasContext *ctx, arg_SAT *a) +{ + prt("sat\tr%d", a->rd); + return true; +} + +/* satr */ +static bool trans_SATR(DisasContext *ctx, arg_SATR *a) +{ + prt("satr"); + return true; +} + +/* fadd #imm, rd */ +static bool trans_FADD_ir(DisasContext *ctx, arg_FADD_ir *a) +{ + prt("fadd\t#%d,r%d", li(ctx, 0), a->rd); + return true; +} + +/* fadd dsp[rs], rd */ +/* fadd rs, rd */ +static bool trans_FADD_mr(DisasContext *ctx, arg_FADD_mr *a) +{ + prt("fadd\t"); + operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd); + return true; +} + +/* fcmp #imm, rd */ +static bool trans_FCMP_ir(DisasContext *ctx, arg_FCMP_ir *a) +{ + prt("fadd\t#%d,r%d", li(ctx, 0), a->rd); + return true; +} + +/* fcmp dsp[rs], rd */ +/* fcmp rs, rd */ +static bool trans_FCMP_mr(DisasContext *ctx, arg_FCMP_mr *a) +{ + prt("fcmp\t"); + operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd); + return true; +} + +/* fsub #imm, rd */ +static bool trans_FSUB_ir(DisasContext *ctx, arg_FSUB_ir *a) +{ + prt("fsub\t#%d,r%d", li(ctx, 0), a->rd); + return true; +} + +/* fsub dsp[rs], rd */ +/* fsub rs, rd */ +static bool trans_FSUB_mr(DisasContext *ctx, arg_FSUB_mr *a) +{ + prt("fsub\t"); + operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd); + return true; +} + +/* ftoi dsp[rs], rd */ +/* ftoi rs, rd */ +static bool trans_FTOI(DisasContext *ctx, arg_FTOI *a) +{ + prt("ftoi\t"); + operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd); + return true; +} + +/* fmul #imm, rd */ +static bool trans_FMUL_ir(DisasContext *ctx, arg_FMUL_ir *a) +{ + prt("fmul\t#%d,r%d", li(ctx, 0), a->rd); + return true; +} + +/* fmul dsp[rs], rd */ +/* fmul rs, rd */ +static bool trans_FMUL_mr(DisasContext *ctx, arg_FMUL_mr *a) +{ + prt("fmul\t"); + operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd); + return true; +} + +/* fdiv #imm, rd */ +static bool trans_FDIV_ir(DisasContext *ctx, arg_FDIV_ir *a) +{ + prt("fdiv\t#%d,r%d", li(ctx, 0), a->rd); + return true; +} + +/* fdiv dsp[rs], rd */ +/* fdiv rs, rd */ +static bool trans_FDIV_mr(DisasContext *ctx, arg_FDIV_mr *a) +{ + prt("fdiv\t"); + operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd); + return true; +} + +/* round dsp[rs], rd */ +/* round rs, rd */ +static bool trans_ROUND(DisasContext *ctx, arg_ROUND *a) +{ + prt("round\t"); + operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd); + return true; +} + +/* itof rs, rd */ +/* itof dsp[rs], rd */ +static bool trans_ITOF(DisasContext *ctx, arg_ITOF *a) +{ + prt("itof\t"); + operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd); + return true; +} + +#define BOP_IM(name, reg) \ + do { \ + int dsp; \ + prt("b%s\t#%d, ", #name, a->imm); \ + dsp =3D rx_index_addr(a->ld, RX_MEMORY_BYTE, ctx); \ + if (dsp > 0) { \ + prt("%d", dsp); \ + } \ + prt("[r%d]", reg); \ + return true; \ + } while (0) + +#define BOP_RM(name) \ + do { \ + int dsp; \ + prt("b%s\tr%d, ", #name, a->rd); \ + dsp =3D rx_index_addr(a->ld, RX_MEMORY_BYTE, ctx); \ + if (dsp > 0) { \ + prt("%d", dsp); \ + } \ + prt("[r%d]", a->rs); \ + return true; \ + } while (0) + +/* bset #imm, dsp[rd] */ +static bool trans_BSET_im(DisasContext *ctx, arg_BSET_im *a) +{ + BOP_IM(bset, a->rs); +} + +/* bset rs, dsp[rd] */ +static bool trans_BSET_rm(DisasContext *ctx, arg_BSET_rm *a) +{ + BOP_RM(set); +} + +/* bset rs, rd */ +static bool trans_BSET_rr(DisasContext *ctx, arg_BSET_rr *a) +{ + prt("bset\tr%d,r%d", a->rs, a->rd); + return true; +} + +/* bset #imm, rd */ +static bool trans_BSET_ir(DisasContext *ctx, arg_BSET_ir *a) +{ + prt("bset\t#%d, r%d", a->imm, a->rd); + return true; +} + +/* bclr #imm, dsp[rd] */ +static bool trans_BCLR_im(DisasContext *ctx, arg_BCLR_im *a) +{ + BOP_IM(clr, a->rs); +} + +/* bclr rs, dsp[rd] */ +static bool trans_BCLR_rm(DisasContext *ctx, arg_BCLR_rm *a) +{ + BOP_RM(clr); +} + +/* bclr rs, rd */ +static bool trans_BCLR_rr(DisasContext *ctx, arg_BCLR_rr *a) +{ + prt("bclr\tr%d, r%d", a->rs, a->rd); + return true; +} + +/* bclr #imm, rd */ +static bool trans_BCLR_ir(DisasContext *ctx, arg_BCLR_ir *a) +{ + prt("bclr\t#%d,r%d", a->imm, a->rd); + return true; +} + +/* btst #imm, dsp[rd] */ +static bool trans_BTST_im(DisasContext *ctx, arg_BTST_im *a) +{ + BOP_IM(tst, a->rs); +} + +/* btst rs, dsp[rd] */ +static bool trans_BTST_rm(DisasContext *ctx, arg_BTST_rm *a) +{ + BOP_RM(tst); +} + +/* btst rs, rd */ +static bool trans_BTST_rr(DisasContext *ctx, arg_BTST_rr *a) +{ + prt("btst\tr%d, r%d", a->rs, a->rd); + return true; +} + +/* btst #imm, rd */ +static bool trans_BTST_ir(DisasContext *ctx, arg_BTST_ir *a) +{ + prt("btst\t#%d, r%d", a->imm, a->rd); + return true; +} + +/* bnot rs, dsp[rd] */ +static bool trans_BNOT_rm(DisasContext *ctx, arg_BNOT_rm *a) +{ + BOP_RM(not); +} + +/* bnot rs, rd */ +static bool trans_BNOT_rr(DisasContext *ctx, arg_BNOT_rr *a) +{ + prt("bnot\tr%d, r%d", a->rs, a->rd); + return true; +} + +/* bnot #imm, dsp[rd] */ +static bool trans_BNOT_im(DisasContext *ctx, arg_BNOT_im *a) +{ + BOP_IM(not, a->rs); +} + +/* bnot #imm, rd */ +static bool trans_BNOT_ir(DisasContext *ctx, arg_BNOT_ir *a) +{ + prt("bnot\t#%d, r%d", a->imm, a->rd); + return true; +} + +/* bmcond #imm, dsp[rd] */ +static bool trans_BMCnd_im(DisasContext *ctx, arg_BMCnd_im *a) +{ + int dsp =3D rx_index_addr(a->ld, RX_MEMORY_BYTE, ctx); + prt("bm%s\t#%d, ", cond[a->cd], a->imm); + if (dsp > 0) { + prt("%d", dsp); + } + prt("[%d]", a->rd); + return true; +} + +/* bmcond #imm, rd */ +static bool trans_BMCnd_ir(DisasContext *ctx, arg_BMCnd_ir *a) +{ + prt("bm%s\t#%d, r%d", cond[a->cd], a->imm, a->rd); + return true; +} + +/* clrpsw psw */ +static bool trans_CLRPSW(DisasContext *ctx, arg_CLRPSW *a) +{ + prt("clrpsw\t%c", psw[a->cb]); + return true; +} + +/* setpsw psw */ +static bool trans_SETPSW(DisasContext *ctx, arg_SETPSW *a) +{ + prt("setpsw\t%c", psw[a->cb]); + return true; +} + +/* mvtipl #imm */ +static bool trans_MVTIPL(DisasContext *ctx, arg_MVTIPL *a) +{ + prt("movtipl\t#%d", a->imm); + return true; +} + +/* mvtc #imm, rd */ +static bool trans_MVTC_i(DisasContext *ctx, arg_MVTC_i *a) +{ + prt("mvtc\t#0x%08x, %s", a->imm, rx_crname(a->cr)); + return true; +} + +/* mvtc rs, rd */ +static bool trans_MVTC_r(DisasContext *ctx, arg_MVTC_r *a) +{ + prt("mvtc\tr%d, %s", a->rs, rx_crname(a->cr)); + return true; +} + +/* mvfc rs, rd */ +static bool trans_MVFC(DisasContext *ctx, arg_MVFC *a) +{ + prt("mvfc\t%s, r%d", rx_crname(a->cr), a->rd); + return true; +} + +/* rtfi */ +static bool trans_RTFI(DisasContext *ctx, arg_RTFI *a) +{ + prt("rtfi"); + return true; +} + +/* rte */ +static bool trans_RTE(DisasContext *ctx, arg_RTE *a) +{ + prt("rte"); + return true; +} + +/* brk */ +static bool trans_BRK(DisasContext *ctx, arg_BRK *a) +{ + prt("brk"); + return true; +} + +/* int #imm */ +static bool trans_INT(DisasContext *ctx, arg_INT *a) +{ + prt("int\t#%d", a->imm); + return true; +} + +/* wait */ +static bool trans_WAIT(DisasContext *ctx, arg_WAIT *a) +{ + prt("wait"); + return true; +} + +/* sccnd.[bwl] rd */ +/* sccnd.[bwl] dsp:[rd] */ +static bool trans_SCCnd(DisasContext *ctx, arg_SCCnd *a) +{ + int dsp; + prt("sc%s.%c\t", cond[a->cd], size[a->sz]); + if (a->ld < 3) { + dsp =3D rx_index_addr(a->sz, a->ld, ctx); + if (dsp > 0) { + prt("%d", dsp); + } + prt("[r%d]", a->rd); + } else { + prt("r%d", a->rd); + } + return true; +} + +int print_insn_rx(bfd_vma addr, disassemble_info *dis) +{ + DisasContext ctx; + uint32_t insn; + int i; + ctx.dis =3D dis; + ctx.pc =3D ctx.addr =3D addr; + + insn =3D decode_load(&ctx); + if (!decode(&ctx, insn)) { + ctx.dis->fprintf_func(ctx.dis->stream, ".byte\t"); + for (i =3D 0; i < ctx.addr - addr; i++) { + if (i > 0) { + ctx.dis->fprintf_func(ctx.dis->stream, ","); + } + ctx.dis->fprintf_func(ctx.dis->stream, "0x%02x", insn >> 24); + insn <<=3D 8; + } + } + return ctx.addr - addr; +} --=20 2.21.1 From nobody Sun May 5 08:48:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1584463976; cv=none; d=zohomail.com; s=zohoarc; b=lNM0a7nOSeUezNjLJShu1SEgJ+d8Qbl0ZtbOmVfW+/2iAjaXfCbb6Fa3ZG4pCEhAHR9L+MXW8tZXgsAGgQUDLB+vbI94qCD2nkVtbdnBAxGJsqGZw262jfgoUiIDFhLY5CPEHRL1ouA3MnfbgOxKBzUK7Ltz7aNTmpnhmo0KDt0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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[83.59.163.96]) by smtp.gmail.com with ESMTPSA id b202sm4618697wmd.15.2020.03.17.09.36.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Mar 2020 09:36:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8H31Kuq83wCqOybbZslqXDuQ3rjWt6eVyrdWP3O9Tt4=; b=Zj05tBN4m1B4KoT/wmoCrgGzodfDvKiFchX1wty7xjDCPM0uPocYEnMz/0B6upbJ8L 3cu1MKBTxB7ZDDR7CQPRuxskHBeO+I//ZKmbGnzKwsVN/0qa0HHel1vOa24rOQZommhv i7zaA5vEnEbYO86U0CD/dJdEECs/cEBBt5GZYWKX9txQmhjesBNLex539bWcDQ7t0BhA 8DM9+Mx4HTgUhtUJvrOheAF/5QW17VL3GirbAJWNE5wjzIIrx/EiykMw9vhELjSSOCza ODpl/L9HGNM1rmRtj/F1wJwcUhAPAaGVdSZopEu3Sj9ID/OCEk4wwilVbk3dai33Hv/m GBVg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=8H31Kuq83wCqOybbZslqXDuQ3rjWt6eVyrdWP3O9Tt4=; b=K57AOkY9m0BCxFUqEE8Vz6NvzOyy9JcpbHEUWgzIeontwjbX+uPOPpZwClgclK6N5W T43/CcspSrJxmPdDkhrJ4I8FITjfBcZ5tA7VkC1+uUGusNsiG6C8bnPqnn0bAK/b6Mwp UgYKEoLy4sV4CTzRMa+DFtjP0ggUBRQnxFD3DMC0LK84i7z9H2pXkrOjaKp0hHbYBLKs ++zKsd+rfA7npYX90lhEDXSpyQCZpVfXIr8oKBuOnoqpIMulBWqyOLV/G4rS0nZmSj0k FsYXPHmTMGEzYObEwdjnGtcYXnbCjFlwIdX/30anyZYMYocLELrggHj1rtQSWEFKlZb9 U50w== X-Gm-Message-State: ANhLgQ1J4JymtEPAQFI2GcCqn70SxfqSMO45CP6n44pOBjXKd4POCfGV roQQclyou4u6p8h/9pb/bOTiZj/Q X-Google-Smtp-Source: ADFU+vv0XNXomYy7ylVwZpjkONIvfJK2JM1ZZEri40EGda5Rjt5x1k5bB4+pBDC8JJrlR+9CweQVAA== X-Received: by 2002:a7b:c854:: with SMTP id c20mr120961wml.99.1584462987441; Tue, 17 Mar 2020 09:36:27 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 07/13] target/rx: Disassemble rx_index_addr into a string Date: Tue, 17 Mar 2020 17:36:10 +0100 Message-Id: <20200317163616.30027-8-f4bug@amsat.org> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200317163616.30027-1-f4bug@amsat.org> References: <20200317163616.30027-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::333 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yoshinori Sato , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Richard Henderson We were eliding all zero indexes. It is only ld=3D=3D0 that does not have an index in the instruction. This also allows us to avoid breaking the final print into multiple pieces. Reviewed-by: Yoshinori Sato Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-Id: <20190531134315.4109-19-richard.henderson@linaro.org> Acked-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/rx/disas.c | 154 +++++++++++++++++----------------------------- 1 file changed, 55 insertions(+), 99 deletions(-) diff --git a/target/rx/disas.c b/target/rx/disas.c index 04cdfdc567..7abb53d776 100644 --- a/target/rx/disas.c +++ b/target/rx/disas.c @@ -107,49 +107,42 @@ static const char psw[] =3D { 'i', 'u', 0, 0, 0, 0, 0, 0, }; =20 -static uint32_t rx_index_addr(int ld, int size, DisasContext *ctx) +static void rx_index_addr(DisasContext *ctx, char out[8], int ld, int mi) { - bfd_byte buf[2]; + uint32_t addr =3D ctx->addr; + uint8_t buf[2]; + uint16_t dsp; + switch (ld) { case 0: - return 0; + /* No index; return empty string. */ + out[0] =3D '\0'; + return; case 1: - ctx->dis->read_memory_func(ctx->addr, buf, 1, ctx->dis); ctx->addr +=3D 1; - return ((uint8_t)buf[0]) << size; + ctx->dis->read_memory_func(addr, buf, 1, ctx->dis); + dsp =3D buf[0]; + break; case 2: - ctx->dis->read_memory_func(ctx->addr, buf, 2, ctx->dis); ctx->addr +=3D 2; - return lduw_le_p(buf) << size; + ctx->dis->read_memory_func(addr, buf, 2, ctx->dis); + dsp =3D lduw_le_p(buf); + break; + default: + g_assert_not_reached(); } - g_assert_not_reached(); + + sprintf(out, "%u", dsp << (mi < 3 ? mi : 4 - mi)); } =20 static void operand(DisasContext *ctx, int ld, int mi, int rs, int rd) { - int dsp; static const char sizes[][4] =3D {".b", ".w", ".l", ".uw", ".ub"}; + char dsp[8]; + if (ld < 3) { - switch (mi) { - case 4: - /* dsp[rs].ub */ - dsp =3D rx_index_addr(ld, RX_MEMORY_BYTE, ctx); - break; - case 3: - /* dsp[rs].uw */ - dsp =3D rx_index_addr(ld, RX_MEMORY_WORD, ctx); - break; - default: - /* dsp[rs].b */ - /* dsp[rs].w */ - /* dsp[rs].l */ - dsp =3D rx_index_addr(ld, mi, ctx); - break; - } - if (dsp > 0) { - prt("%d", dsp); - } - prt("[r%d]%s", rs, sizes[mi]); + rx_index_addr(ctx, dsp, ld, mi); + prt("%s[r%d]%s", dsp, rs, sizes[mi]); } else { prt("r%d", rs); } @@ -235,7 +228,7 @@ static bool trans_MOV_ra(DisasContext *ctx, arg_MOV_ra = *a) /* mov.[bwl] rs,rd */ static bool trans_MOV_mm(DisasContext *ctx, arg_MOV_mm *a) { - int dsp; + char dspd[8], dsps[8]; =20 prt("mov.%c\t", size[a->sz]); if (a->lds =3D=3D 3 && a->ldd =3D=3D 3) { @@ -244,29 +237,15 @@ static bool trans_MOV_mm(DisasContext *ctx, arg_MOV_m= m *a) return true; } if (a->lds =3D=3D 3) { - prt("r%d, ", a->rd); - dsp =3D rx_index_addr(a->ldd, a->sz, ctx); - if (dsp > 0) { - prt("%d", dsp); - } - prt("[r%d]", a->rs); + rx_index_addr(ctx, dspd, a->ldd, a->sz); + prt("r%d, %s[r%d]", a->rs, dspd, a->rd); } else if (a->ldd =3D=3D 3) { - dsp =3D rx_index_addr(a->lds, a->sz, ctx); - if (dsp > 0) { - prt("%d", dsp); - } - prt("[r%d], r%d", a->rs, a->rd); + rx_index_addr(ctx, dsps, a->lds, a->sz); + prt("%s[r%d], r%d", dsps, a->rs, a->rd); } else { - dsp =3D rx_index_addr(a->lds, a->sz, ctx); - if (dsp > 0) { - prt("%d", dsp); - } - prt("[r%d], ", a->rs); - dsp =3D rx_index_addr(a->ldd, a->sz, ctx); - if (dsp > 0) { - prt("%d", dsp); - } - prt("[r%d]", a->rd); + rx_index_addr(ctx, dsps, a->lds, a->sz); + rx_index_addr(ctx, dspd, a->ldd, a->sz); + prt("%s[r%d], %s[r%d]", dsps, a->rs, dspd, a->rd); } return true; } @@ -357,12 +336,10 @@ static bool trans_PUSH_r(DisasContext *ctx, arg_PUSH_= r *a) /* push dsp[rs] */ static bool trans_PUSH_m(DisasContext *ctx, arg_PUSH_m *a) { - prt("push\t"); - int dsp =3D rx_index_addr(a->ld, a->sz, ctx); - if (dsp > 0) { - prt("%d", dsp); - } - prt("[r%d]", a->rs); + char dsp[8]; + + rx_index_addr(ctx, dsp, a->ld, a->sz); + prt("push\t%s[r%d]", dsp, a->rs); return true; } =20 @@ -389,17 +366,13 @@ static bool trans_XCHG_rr(DisasContext *ctx, arg_XCHG= _rr *a) /* xchg dsp[rs].,rd */ static bool trans_XCHG_mr(DisasContext *ctx, arg_XCHG_mr *a) { - int dsp; static const char msize[][4] =3D { "b", "w", "l", "ub", "uw", }; + char dsp[8]; =20 - prt("xchg\t"); - dsp =3D rx_index_addr(a->ld, a->mi, ctx); - if (dsp > 0) { - prt("%d", dsp); - } - prt("[r%d].%s, r%d", a->rs, msize[a->mi], a->rd); + rx_index_addr(ctx, dsp, a->ld, a->mi); + prt("xchg\t%s[r%d].%s, r%d", dsp, a->rs, msize[a->mi], a->rd); return true; } =20 @@ -552,13 +525,10 @@ static bool trans_ADC_rr(DisasContext *ctx, arg_ADC_r= r *a) /* adc dsp[rs], rd */ static bool trans_ADC_mr(DisasContext *ctx, arg_ADC_mr *a) { - int dsp; - prt("adc\t"); - dsp =3D rx_index_addr(a->ld, 2, ctx); - if (dsp > 0) { - prt("%d", dsp); - } - prt("[r%d], r%d", a->rs, a->rd); + char dsp[8]; + + rx_index_addr(ctx, dsp, a->ld, 2); + prt("adc\t%s[r%d], r%d", dsp, a->rs, a->rd); return true; } =20 @@ -1217,25 +1187,17 @@ static bool trans_ITOF(DisasContext *ctx, arg_ITOF = *a) =20 #define BOP_IM(name, reg) \ do { \ - int dsp; \ - prt("b%s\t#%d, ", #name, a->imm); \ - dsp =3D rx_index_addr(a->ld, RX_MEMORY_BYTE, ctx); \ - if (dsp > 0) { \ - prt("%d", dsp); \ - } \ - prt("[r%d]", reg); \ + char dsp[8]; \ + rx_index_addr(ctx, dsp, a->ld, RX_MEMORY_BYTE); \ + prt("b%s\t#%d, %s[r%d]", #name, a->imm, dsp, reg); \ return true; \ } while (0) =20 #define BOP_RM(name) \ do { \ - int dsp; \ - prt("b%s\tr%d, ", #name, a->rd); \ - dsp =3D rx_index_addr(a->ld, RX_MEMORY_BYTE, ctx); \ - if (dsp > 0) { \ - prt("%d", dsp); \ - } \ - prt("[r%d]", a->rs); \ + char dsp[8]; \ + rx_index_addr(ctx, dsp, a->ld, RX_MEMORY_BYTE); \ + prt("b%s\tr%d, %s[r%d]", #name, a->rd, dsp, a->rs); \ return true; \ } while (0) =20 @@ -1346,12 +1308,10 @@ static bool trans_BNOT_ir(DisasContext *ctx, arg_BN= OT_ir *a) /* bmcond #imm, dsp[rd] */ static bool trans_BMCnd_im(DisasContext *ctx, arg_BMCnd_im *a) { - int dsp =3D rx_index_addr(a->ld, RX_MEMORY_BYTE, ctx); - prt("bm%s\t#%d, ", cond[a->cd], a->imm); - if (dsp > 0) { - prt("%d", dsp); - } - prt("[%d]", a->rd); + char dsp[8]; + + rx_index_addr(ctx, dsp, a->ld, RX_MEMORY_BYTE); + prt("bm%s\t#%d, %s[r%d]", cond[a->cd], a->imm, dsp, a->rd); return true; } =20 @@ -1443,16 +1403,12 @@ static bool trans_WAIT(DisasContext *ctx, arg_WAIT = *a) /* sccnd.[bwl] dsp:[rd] */ static bool trans_SCCnd(DisasContext *ctx, arg_SCCnd *a) { - int dsp; - prt("sc%s.%c\t", cond[a->cd], size[a->sz]); if (a->ld < 3) { - dsp =3D rx_index_addr(a->sz, a->ld, ctx); - if (dsp > 0) { - prt("%d", dsp); - } - prt("[r%d]", a->rd); + char dsp[8]; + rx_index_addr(ctx, dsp, a->sz, a->ld); + prt("sc%s.%c\t%s[r%d]", cond[a->cd], size[a->sz], dsp, a->rd); } else { - prt("r%d", a->rd); + prt("sc%s.%c\tr%d", cond[a->cd], size[a->sz], a->rd); } return true; } --=20 2.21.1 From nobody Sun May 5 08:48:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1584463669; cv=none; d=zohomail.com; s=zohoarc; b=Ti9mnlETE9olHDH+g7dwWM5Ng6SimVbYak+ltcPSDBsr1VQ/8ICaTKsD/3uxECyiXNc62M03Kb88kjKLjbra6nOEotaE1YemMDczhoL8blZGHr3t6qUGBYSZyQYq1hiXRONZXsQcOf0ms6El7y1P9D7JiKg3qBnc6u12rVGPK3I= ARC-Message-Signature: i=1; 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[83.59.163.96]) by smtp.gmail.com with ESMTPSA id b202sm4618697wmd.15.2020.03.17.09.36.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Mar 2020 09:36:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yRLrMiYAa2eSXqh7vxtfwTDgpEpApTWjV4HpUsCvytk=; b=YEYR8tnviBuxO41FtcOcuqykOcPhpqXEmGWkSIIFaw/DNoa61/uzYKSEOKTgoq/xe2 6wtTT3MpOSJcyYzfIXgQjc0WJ4DXqpSgXuK81+EliIImM4QfBaO5SOGtGL1+YCniPUBc uXxw3NfeAYmm+YkEgJxifuptTJH9C9mWIWkqeQYVwV7VTPuVZbtS76k1uEFLlh0fe3AM e1bDQUByRq4ZvoEsDa0wOwfZurNl3PFtighH4l4nwQS0/PQ+m5qnI0KbkWcYLWy+MvP6 ENSob6d0Nsemhl7GyEf+ORhuI3Jr23p4+dmNO/hoYy5PQvJGTD4IqtqxZAJPiKiZ4rqs vrcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=yRLrMiYAa2eSXqh7vxtfwTDgpEpApTWjV4HpUsCvytk=; b=fCW6uDTR4TBbtNQoi+KhZS8LsmGNZcAyIqSt0bxZsMevap9TBObNxx0YNqLIUW7wt9 tMIFdlKl9Cm+ObWD88w2eHnwFtWz0kZoKUAvoZtxkhrXMbQE1kO/sQeMN2XQ8UtT5w2R IsHvdbB36VHMNjK3YCO+1B7i0anYAitUTF1uIVpfI0g9DTlQP3LrEbj8KQiwk2HBUI5/ zpXhWScu6kBuLI0CBVVwTYND4Zrx60JjbeIiCVHZlItpBn/TmdvKo3lDFKALIcFMYP0f ZM+Au1rgyICifyof3QJ9lzeBCa4lzc7AYeOeKvf0quAI2c00X8coDOfmG6rLx4H1lQBR eygQ== X-Gm-Message-State: ANhLgQ0kSqMAAZByTONzsnSvFyod4G3jRXrrZosmxsg8CNZUJSWbT6eZ RonefMR+YwpAmtaxX7eNccf1gW+Y X-Google-Smtp-Source: ADFU+vvS7R5D2lrShc04TVDA+kNwnHS5uYQwS++MQkadRn9CvEANK2ne0B+pvrHeNV6AcBVgj1A1gQ== X-Received: by 2002:adf:dc90:: with SMTP id r16mr6155143wrj.338.1584462988630; Tue, 17 Mar 2020 09:36:28 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 08/13] target/rx: Replace operand with prt_ldmi in disassembler Date: Tue, 17 Mar 2020 17:36:11 +0100 Message-Id: <20200317163616.30027-9-f4bug@amsat.org> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200317163616.30027-1-f4bug@amsat.org> References: <20200317163616.30027-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::444 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yoshinori Sato , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Richard Henderson This has consistency with prt_ri(). It loads all data before beginning output. It uses exactly one call to prt() to emit the full instruction. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Yoshinori Sato Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-Id: <20190531134315.4109-20-richard.henderson@linaro.org> Acked-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/rx/disas.c | 77 +++++++++++++++++------------------------------ 1 file changed, 27 insertions(+), 50 deletions(-) diff --git a/target/rx/disas.c b/target/rx/disas.c index 7abb53d776..0c4115669d 100644 --- a/target/rx/disas.c +++ b/target/rx/disas.c @@ -135,18 +135,18 @@ static void rx_index_addr(DisasContext *ctx, char out= [8], int ld, int mi) sprintf(out, "%u", dsp << (mi < 3 ? mi : 4 - mi)); } =20 -static void operand(DisasContext *ctx, int ld, int mi, int rs, int rd) +static void prt_ldmi(DisasContext *ctx, const char *insn, + int ld, int mi, int rs, int rd) { static const char sizes[][4] =3D {".b", ".w", ".l", ".uw", ".ub"}; char dsp[8]; =20 if (ld < 3) { rx_index_addr(ctx, dsp, ld, mi); - prt("%s[r%d]%s", dsp, rs, sizes[mi]); + prt("%s\t%s[r%d]%s, r%d", insn, dsp, rs, sizes[mi], rd); } else { - prt("r%d", rs); + prt("%s\tr%d, r%d", insn, rs, rd); } - prt(", r%d", rd); } =20 static void prt_ir(DisasContext *ctx, const char *insn, int imm, int rd) @@ -416,8 +416,7 @@ static bool trans_AND_ir(DisasContext *ctx, arg_AND_ir = *a) /* and rs,rd */ static bool trans_AND_mr(DisasContext *ctx, arg_AND_mr *a) { - prt("and\t"); - operand(ctx, a->ld, a->mi, a->rs, a->rd); + prt_ldmi(ctx, "and", a->ld, a->mi, a->rs, a->rd); return true; } =20 @@ -440,8 +439,7 @@ static bool trans_OR_ir(DisasContext *ctx, arg_OR_ir *a) /* or rs,rd */ static bool trans_OR_mr(DisasContext *ctx, arg_OR_mr *a) { - prt("or\t"); - operand(ctx, a->ld, a->mi, a->rs, a->rd); + prt_ldmi(ctx, "or", a->ld, a->mi, a->rs, a->rd); return true; } =20 @@ -463,8 +461,7 @@ static bool trans_XOR_ir(DisasContext *ctx, arg_XOR_ir = *a) /* xor rs,rd */ static bool trans_XOR_mr(DisasContext *ctx, arg_XOR_mr *a) { - prt("xor\t"); - operand(ctx, a->ld, a->mi, a->rs, a->rd); + prt_ldmi(ctx, "xor", a->ld, a->mi, a->rs, a->rd); return true; } =20 @@ -479,8 +476,7 @@ static bool trans_TST_ir(DisasContext *ctx, arg_TST_ir = *a) /* tst rs, rd */ static bool trans_TST_mr(DisasContext *ctx, arg_TST_mr *a) { - prt("tst\t"); - operand(ctx, a->ld, a->mi, a->rs, a->rd); + prt_ldmi(ctx, "tst", a->ld, a->mi, a->rs, a->rd); return true; } =20 @@ -548,8 +544,7 @@ static bool trans_ADD_irr(DisasContext *ctx, arg_ADD_ir= r *a) /* add dsp[rs], rd */ static bool trans_ADD_mr(DisasContext *ctx, arg_ADD_mr *a) { - prt("add\t"); - operand(ctx, a->ld, a->mi, a->rs, a->rd); + prt_ldmi(ctx, "add", a->ld, a->mi, a->rs, a->rd); return true; } =20 @@ -573,8 +568,7 @@ static bool trans_CMP_ir(DisasContext *ctx, arg_CMP_ir = *a) /* cmp dsp[rs], rs2 */ static bool trans_CMP_mr(DisasContext *ctx, arg_CMP_mr *a) { - prt("cmp\t"); - operand(ctx, a->ld, a->mi, a->rs, a->rd); + prt_ldmi(ctx, "cmp", a->ld, a->mi, a->rs, a->rd); return true; } =20 @@ -589,8 +583,7 @@ static bool trans_SUB_ir(DisasContext *ctx, arg_SUB_ir = *a) /* sub dsp[rs], rd */ static bool trans_SUB_mr(DisasContext *ctx, arg_SUB_mr *a) { - prt("sub\t"); - operand(ctx, a->ld, a->mi, a->rs, a->rd); + prt_ldmi(ctx, "sub", a->ld, a->mi, a->rs, a->rd); return true; } =20 @@ -611,8 +604,7 @@ static bool trans_SBB_rr(DisasContext *ctx, arg_SBB_rr = *a) /* sbb dsp[rs], rd */ static bool trans_SBB_mr(DisasContext *ctx, arg_SBB_mr *a) { - prt("sbb\t"); - operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd); + prt_ldmi(ctx, "sbb", a->ld, RX_IM_LONG, a->rs, a->rd); return true; } =20 @@ -640,8 +632,7 @@ static bool trans_MAX_ir(DisasContext *ctx, arg_MAX_ir = *a) /* max dsp[rs], rd */ static bool trans_MAX_mr(DisasContext *ctx, arg_MAX_mr *a) { - prt("max\t"); - operand(ctx, a->ld, a->mi, a->rs, a->rd); + prt_ldmi(ctx, "max", a->ld, a->mi, a->rs, a->rd); return true; } =20 @@ -656,8 +647,7 @@ static bool trans_MIN_ir(DisasContext *ctx, arg_MIN_ir = *a) /* min dsp[rs], rd */ static bool trans_MIN_mr(DisasContext *ctx, arg_MIN_mr *a) { - prt("max\t"); - operand(ctx, a->ld, a->mi, a->rs, a->rd); + prt_ldmi(ctx, "min", a->ld, a->mi, a->rs, a->rd); return true; } =20 @@ -673,8 +663,7 @@ static bool trans_MUL_ir(DisasContext *ctx, arg_MUL_ir = *a) /* mul dsp[rs], rd */ static bool trans_MUL_mr(DisasContext *ctx, arg_MUL_mr *a) { - prt("mul\t"); - operand(ctx, a->ld, a->mi, a->rs, a->rd); + prt_ldmi(ctx, "mul", a->ld, a->mi, a->rs, a->rd); return true; } =20 @@ -696,8 +685,7 @@ static bool trans_EMUL_ir(DisasContext *ctx, arg_EMUL_i= r *a) /* emul dsp[rs], rd */ static bool trans_EMUL_mr(DisasContext *ctx, arg_EMUL_mr *a) { - prt("emul\t"); - operand(ctx, a->ld, a->mi, a->rs, a->rd); + prt_ldmi(ctx, "emul", a->ld, a->mi, a->rs, a->rd); return true; } =20 @@ -712,8 +700,7 @@ static bool trans_EMULU_ir(DisasContext *ctx, arg_EMULU= _ir *a) /* emulu dsp[rs], rd */ static bool trans_EMULU_mr(DisasContext *ctx, arg_EMULU_mr *a) { - prt("emulu\t"); - operand(ctx, a->ld, a->mi, a->rs, a->rd); + prt_ldmi(ctx, "emulu", a->ld, a->mi, a->rs, a->rd); return true; } =20 @@ -728,8 +715,7 @@ static bool trans_DIV_ir(DisasContext *ctx, arg_DIV_ir = *a) /* div dsp[rs], rd */ static bool trans_DIV_mr(DisasContext *ctx, arg_DIV_mr *a) { - prt("div\t"); - operand(ctx, a->ld, a->mi, a->rs, a->rd); + prt_ldmi(ctx, "div", a->ld, a->mi, a->rs, a->rd); return true; } =20 @@ -744,8 +730,7 @@ static bool trans_DIVU_ir(DisasContext *ctx, arg_DIVU_i= r *a) /* divu dsp[rs], rd */ static bool trans_DIVU_mr(DisasContext *ctx, arg_DIVU_mr *a) { - prt("divu\t"); - operand(ctx, a->ld, a->mi, a->rs, a->rd); + prt_ldmi(ctx, "divu", a->ld, a->mi, a->rs, a->rd); return true; } =20 @@ -1089,8 +1074,7 @@ static bool trans_FADD_ir(DisasContext *ctx, arg_FADD= _ir *a) /* fadd rs, rd */ static bool trans_FADD_mr(DisasContext *ctx, arg_FADD_mr *a) { - prt("fadd\t"); - operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd); + prt_ldmi(ctx, "fadd", a->ld, RX_IM_LONG, a->rs, a->rd); return true; } =20 @@ -1105,8 +1089,7 @@ static bool trans_FCMP_ir(DisasContext *ctx, arg_FCMP= _ir *a) /* fcmp rs, rd */ static bool trans_FCMP_mr(DisasContext *ctx, arg_FCMP_mr *a) { - prt("fcmp\t"); - operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd); + prt_ldmi(ctx, "fcmp", a->ld, RX_IM_LONG, a->rs, a->rd); return true; } =20 @@ -1121,8 +1104,7 @@ static bool trans_FSUB_ir(DisasContext *ctx, arg_FSUB= _ir *a) /* fsub rs, rd */ static bool trans_FSUB_mr(DisasContext *ctx, arg_FSUB_mr *a) { - prt("fsub\t"); - operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd); + prt_ldmi(ctx, "fsub", a->ld, RX_IM_LONG, a->rs, a->rd); return true; } =20 @@ -1130,8 +1112,7 @@ static bool trans_FSUB_mr(DisasContext *ctx, arg_FSUB= _mr *a) /* ftoi rs, rd */ static bool trans_FTOI(DisasContext *ctx, arg_FTOI *a) { - prt("ftoi\t"); - operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd); + prt_ldmi(ctx, "ftoi", a->ld, RX_IM_LONG, a->rs, a->rd); return true; } =20 @@ -1146,8 +1127,7 @@ static bool trans_FMUL_ir(DisasContext *ctx, arg_FMUL= _ir *a) /* fmul rs, rd */ static bool trans_FMUL_mr(DisasContext *ctx, arg_FMUL_mr *a) { - prt("fmul\t"); - operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd); + prt_ldmi(ctx, "fmul", a->ld, RX_IM_LONG, a->rs, a->rd); return true; } =20 @@ -1162,8 +1142,7 @@ static bool trans_FDIV_ir(DisasContext *ctx, arg_FDIV= _ir *a) /* fdiv rs, rd */ static bool trans_FDIV_mr(DisasContext *ctx, arg_FDIV_mr *a) { - prt("fdiv\t"); - operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd); + prt_ldmi(ctx, "fdiv", a->ld, RX_IM_LONG, a->rs, a->rd); return true; } =20 @@ -1171,8 +1150,7 @@ static bool trans_FDIV_mr(DisasContext *ctx, arg_FDIV= _mr *a) /* round rs, rd */ static bool trans_ROUND(DisasContext *ctx, arg_ROUND *a) { - prt("round\t"); - operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd); + prt_ldmi(ctx, "round", a->ld, RX_IM_LONG, a->rs, a->rd); return true; } =20 @@ -1180,8 +1158,7 @@ static bool trans_ROUND(DisasContext *ctx, arg_ROUND = *a) /* itof dsp[rs], rd */ static bool trans_ITOF(DisasContext *ctx, arg_ITOF *a) { - prt("itof\t"); - operand(ctx, a->ld, RX_IM_LONG, a->rs, a->rd); + prt_ldmi(ctx, "itof", a->ld, RX_IM_LONG, a->rs, a->rd); return true; } =20 --=20 2.21.1 From nobody Sun May 5 08:48:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[83.59.163.96]) by smtp.gmail.com with ESMTPSA id b202sm4618697wmd.15.2020.03.17.09.36.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Mar 2020 09:36:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1enKsIBdEviq5nykP6LOEgZbSgk5slEBebWoM6e6JJM=; b=Lhu1xL46r5+epPlep0AEbOEjzP7r8OMGtrUbgA9duExYp/Nuc2R/sctwDj64FckOet 620FH2+fM1t/E6ctFqDaoZvhpQJ/r8+dWK8wbSv9q4fHNe1mnMsXZ4EeA9t+1b4yt+wb vwe2RqYpEmUJDOJp42eZ/8dK8I+vQaExsBPV7UMo+cSfTCIYtGpelxg43xNBaE2Mjs0A LHZn7YNpztvSIpx/B/KaWHKHq6Sb8KyPQyfMxRh27jZhFnmyNlsGLw7JEGUQ2LNuy+kR GTkceBV6C6ePaIJ45qOCF0wCwfjn8E72ntCruerJu9YcDduVexi2z8SOZz9V3cBVNSvo 4ejw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=1enKsIBdEviq5nykP6LOEgZbSgk5slEBebWoM6e6JJM=; b=XDe59++A6XIc181msWtarFyHbwC+C3OZGYvYZKpO4EVqwHiRVSUej7jFuOqgzde6Yt m6CKmCT5K5SBGCs5fgWbL/4DOegnBE5lt7R4PCNrkDeInf/oHX119SvP5sXdeF09LhOO oYkN4ihu3j3Jz+tuwc6+UXSflFSwoxXWh0u9R3jPibJuSJB61Jcilyy7feMboxwxBMFV CHjfZutaMr5Y2p7J6fbcfH4jh3aJNqRUfytTw1XHm2lDsnZojZ/rEISsx3aHNl1Wm+iV 6AUkhoJW3N60CdgpC9zj5pyXW31eq0+uc2Sfi3SIEwisio39F7g2uGmDoMSDrNjPL6qn O0mw== X-Gm-Message-State: ANhLgQ1eHNu1Q73vq5eEItKr8YLGhaWasz2L8WCIqf/7ogwoOJYcFAY6 STPKtMh1KNi5X6tISYRdaKAoeQ73 X-Google-Smtp-Source: ADFU+vsyRGk9qajRzf6pq2wSfRqEfyobWWnTR7qX3jFAWhj3NmvWeiG7IQGVJ+vgnAjzzTwFjeJXEg== X-Received: by 2002:a5d:4a10:: with SMTP id m16mr6618622wrq.333.1584462990895; Tue, 17 Mar 2020 09:36:30 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 09/13] target/rx: Use prt_ldmi for XCHG_mr disassembly Date: Tue, 17 Mar 2020 17:36:12 +0100 Message-Id: <20200317163616.30027-10-f4bug@amsat.org> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200317163616.30027-1-f4bug@amsat.org> References: <20200317163616.30027-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::42d X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yoshinori Sato , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Richard Henderson Note that the ld =3D=3D 3 case handled by prt_ldmi is decoded as XCHG_rr and cannot appear here. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Yoshinori Sato Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-Id: <20190531134315.4109-21-richard.henderson@linaro.org> Acked-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/rx/disas.c | 8 +------- 1 file changed, 1 insertion(+), 7 deletions(-) diff --git a/target/rx/disas.c b/target/rx/disas.c index 0c4115669d..a0c444020c 100644 --- a/target/rx/disas.c +++ b/target/rx/disas.c @@ -366,13 +366,7 @@ static bool trans_XCHG_rr(DisasContext *ctx, arg_XCHG_= rr *a) /* xchg dsp[rs].,rd */ static bool trans_XCHG_mr(DisasContext *ctx, arg_XCHG_mr *a) { - static const char msize[][4] =3D { - "b", "w", "l", "ub", "uw", - }; - char dsp[8]; - - rx_index_addr(ctx, dsp, a->ld, a->mi); - prt("xchg\t%s[r%d].%s, r%d", dsp, a->rs, msize[a->mi], a->rd); + prt_ldmi(ctx, "xchg", a->ld, a->mi, a->rs, a->rd); return true; } =20 --=20 2.21.1 From nobody Sun May 5 08:48:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1584463813; cv=none; d=zohomail.com; s=zohoarc; b=eR1OVv3a2ooLTWZ8LeYHaNSmRu2Snu/MpJvsmtngPErKcwwMPtwZ7zITxhhB0/Krlc+gtXqOtSEYtKabOiTViGtCR3R/HANTH7FRIFhNVS4BewcfZWmQFCuyhKZmIWwxT7Oy+1zuVWkiFy+zS1NoHHCqkh7sSKXij1fzwgsxX0E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1584463813; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Yyb54Z5z/ykNOhXoH1gOKUFqMaavHpOhkHDAz9vguSE=; b=PBlhWrBQ/VSeUuC/X4AsYNLSszy4vE1Xfm5rwi4XiYFZAbBMrnv6STqgXCarGgFvZyCdDOoYNmaaedHPpjLIoKbw5KflHsW0PR06FK99J6TKZCVXTC6t7LSSji40DR9GJa/9DMM6U7S4aXE0Nyu7Cg1AEuKWc1FZnoCH1M9FC7Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 158446381360333.11285748838941; Tue, 17 Mar 2020 09:50:13 -0700 (PDT) Received: from localhost ([::1]:36842 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jEFPw-0006nx-DO for importer@patchew.org; Tue, 17 Mar 2020 12:50:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:35963) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jEFCl-0003vW-Ur for qemu-devel@nongnu.org; Tue, 17 Mar 2020 12:36:37 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jEFCk-0003wQ-7T for qemu-devel@nongnu.org; Tue, 17 Mar 2020 12:36:35 -0400 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:37371) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1jEFCj-0003p5-VD for qemu-devel@nongnu.org; Tue, 17 Mar 2020 12:36:34 -0400 Received: by mail-wm1-x344.google.com with SMTP id a141so22755406wme.2 for ; Tue, 17 Mar 2020 09:36:33 -0700 (PDT) Received: from x1w.redhat.com (96.red-83-59-163.dynamicip.rima-tde.net. [83.59.163.96]) by smtp.gmail.com with ESMTPSA id b202sm4618697wmd.15.2020.03.17.09.36.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Mar 2020 09:36:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Yyb54Z5z/ykNOhXoH1gOKUFqMaavHpOhkHDAz9vguSE=; b=XmPpHWY8AVuixOtR7Jk3RVcJQehHWonDGm4s4ahpCkV99AG0nHBngUrUej8ekOScGt 3qFBo2aPFMlgnZVwQAxJLz0De2sqKKVpT3Yo/GilQYizRPs9huD/Tf3EFo+y4X05hPxM xSEiHKtr2OsqPUvSwjPA9XGgHsl0N3S48SwkgdYbuQR2ylolWPliBXUG9fH/MhAdWsDO U1huhqlUFOa8ruyqT7QnLl95GN28Sjg/Gd9X+Uv6ajZww9aB2bsavlOw9/vf7cz6K1M+ Bdnqu9zmYrNTKEqaFrYf/bw4ghy2Kk3BR1PxZaJTcRIQHvQiIfpkdBfI7KVDNpbYKShM upXA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=Yyb54Z5z/ykNOhXoH1gOKUFqMaavHpOhkHDAz9vguSE=; b=RQOePulKvfiFcGgFuat84xFY6v9hkrpLirjuL1GdIXoeeg7ti2yzfo64lE6KgNi+IO m1QwohjRnDsus+MQ0oMRE5jih0hmyACZq7D/k6tFVU+esBzXJa4XJeluu0PQi8lgGbfx uckuFT/yoB+6Gd9V0e0ups32mxxLJdKIBMaIpUdwmkInN5/0ZEhNQZlss71eMfPeaU/3 TnBwoTDoavH23OWkyF5Xg5llbbvHICSgw8MXyK0vbVATpx8OwIIMFnIt1fNPLbtX/8hq 8FjJXuCnXa8p4XnZkxKsKLwRm/rkiOS/T0RUoqfy3/UmxV4BRSngQFpF7c6WS2o9Dx5r zemA== X-Gm-Message-State: ANhLgQ3WdsDRPVg+yNxQ7OLfyfKrHgPIlxRqzeM+O8es4Q6HXKMjJCyM Gj8jeol4dQFPQMwDH7XFsuZGTTP3 X-Google-Smtp-Source: ADFU+vuzYqL++3BHW+1n6N76CohnDXGU4NOmfBe/Cu+GlNvR5+eYfdnTFzXzZT6AfktwxZb2ANgZPA== X-Received: by 2002:a05:600c:214f:: with SMTP id v15mr169207wml.110.1584462992162; Tue, 17 Mar 2020 09:36:32 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 10/13] target/rx: Emit all disassembly in one prt() Date: Tue, 17 Mar 2020 17:36:13 +0100 Message-Id: <20200317163616.30027-11-f4bug@amsat.org> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200317163616.30027-1-f4bug@amsat.org> References: <20200317163616.30027-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yoshinori Sato , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Richard Henderson Many of the multi-part prints have been eliminated by previous patches. Eliminate the rest of them. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Yoshinori Sato Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-Id: <20190531134315.4109-22-richard.henderson@linaro.org> Acked-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/rx/disas.c | 75 ++++++++++++++++++++++++----------------------- 1 file changed, 39 insertions(+), 36 deletions(-) diff --git a/target/rx/disas.c b/target/rx/disas.c index a0c444020c..814ef97480 100644 --- a/target/rx/disas.c +++ b/target/rx/disas.c @@ -228,24 +228,21 @@ static bool trans_MOV_ra(DisasContext *ctx, arg_MOV_r= a *a) /* mov.[bwl] rs,rd */ static bool trans_MOV_mm(DisasContext *ctx, arg_MOV_mm *a) { - char dspd[8], dsps[8]; + char dspd[8], dsps[8], szc =3D size[a->sz]; =20 - prt("mov.%c\t", size[a->sz]); if (a->lds =3D=3D 3 && a->ldd =3D=3D 3) { /* mov.[bwl] rs,rd */ - prt("r%d, r%d", a->rs, a->rd); - return true; - } - if (a->lds =3D=3D 3) { + prt("mov.%c\tr%d, r%d", szc, a->rs, a->rd); + } else if (a->lds =3D=3D 3) { rx_index_addr(ctx, dspd, a->ldd, a->sz); - prt("r%d, %s[r%d]", a->rs, dspd, a->rd); + prt("mov.%c\tr%d, %s[r%d]", szc, a->rs, dspd, a->rd); } else if (a->ldd =3D=3D 3) { rx_index_addr(ctx, dsps, a->lds, a->sz); - prt("%s[r%d], r%d", dsps, a->rs, a->rd); + prt("mov.%c\t%s[r%d], r%d", szc, dsps, a->rs, a->rd); } else { rx_index_addr(ctx, dsps, a->lds, a->sz); rx_index_addr(ctx, dspd, a->ldd, a->sz); - prt("%s[r%d], %s[r%d]", dsps, a->rs, dspd, a->rd); + prt("mov.%c\t%s[r%d], %s[r%d]", szc, dsps, a->rs, dspd, a->rd); } return true; } @@ -254,8 +251,11 @@ static bool trans_MOV_mm(DisasContext *ctx, arg_MOV_mm= *a) /* mov.[bwl] rs,[-rd] */ static bool trans_MOV_rp(DisasContext *ctx, arg_MOV_rp *a) { - prt("mov.%c\tr%d, ", size[a->sz], a->rs); - prt((a->ad =3D=3D 0) ? "[r%d+]" : "[-r%d]", a->rd); + if (a->ad) { + prt("mov.%c\tr%d, [-r%d]", size[a->sz], a->rs, a->rd); + } else { + prt("mov.%c\tr%d, [r%d+]", size[a->sz], a->rs, a->rd); + } return true; } =20 @@ -263,9 +263,11 @@ static bool trans_MOV_rp(DisasContext *ctx, arg_MOV_rp= *a) /* mov.[bwl] [-rd],rs */ static bool trans_MOV_pr(DisasContext *ctx, arg_MOV_pr *a) { - prt("mov.%c\t", size[a->sz]); - prt((a->ad =3D=3D 0) ? "[r%d+]" : "[-r%d]", a->rd); - prt(", r%d", a->rs); + if (a->ad) { + prt("mov.%c\t[-r%d], r%d", size[a->sz], a->rd, a->rs); + } else { + prt("mov.%c\t[r%d+], r%d", size[a->sz], a->rd, a->rs); + } return true; } =20 @@ -299,9 +301,11 @@ static bool trans_MOVU_ar(DisasContext *ctx, arg_MOVU_= ar *a) /* movu.[bw] [-rs],rd */ static bool trans_MOVU_pr(DisasContext *ctx, arg_MOVU_pr *a) { - prt("movu.%c\t", size[a->sz]); - prt((a->ad =3D=3D 0) ? "[r%d+]" : "[-r%d]", a->rd); - prt(", r%d", a->rs); + if (a->ad) { + prt("movu.%c\t[-r%d], r%d", size[a->sz], a->rd, a->rs); + } else { + prt("movu.%c\t[r%d+], r%d", size[a->sz], a->rd, a->rs); + } return true; } =20 @@ -478,11 +482,11 @@ static bool trans_TST_mr(DisasContext *ctx, arg_TST_m= r *a) /* not rs, rd */ static bool trans_NOT_rr(DisasContext *ctx, arg_NOT_rr *a) { - prt("not\t"); if (a->rs !=3D a->rd) { - prt("r%d, ", a->rs); + prt("not\tr%d, r%d", a->rs, a->rd); + } else { + prt("not\tr%d", a->rs); } - prt("r%d", a->rd); return true; } =20 @@ -490,11 +494,11 @@ static bool trans_NOT_rr(DisasContext *ctx, arg_NOT_r= r *a) /* neg rs, rd */ static bool trans_NEG_rr(DisasContext *ctx, arg_NEG_rr *a) { - prt("neg\t"); if (a->rs !=3D a->rd) { - prt("r%d, ", a->rs); + prt("neg\tr%d, r%d", a->rs, a->rd); + } else { + prt("neg\tr%d", a->rs); } - prt("r%d", a->rd); return true; } =20 @@ -606,11 +610,10 @@ static bool trans_SBB_mr(DisasContext *ctx, arg_SBB_m= r *a) /* abs rs, rd */ static bool trans_ABS_rr(DisasContext *ctx, arg_ABS_rr *a) { - prt("abs\t"); - if (a->rs =3D=3D a->rd) { - prt("r%d", a->rd); + if (a->rs !=3D a->rd) { + prt("abs\tr%d, r%d", a->rs, a->rd); } else { - prt("r%d, r%d", a->rs, a->rd); + prt("abs\tr%d", a->rs); } return true; } @@ -733,11 +736,11 @@ static bool trans_DIVU_mr(DisasContext *ctx, arg_DIVU= _mr *a) /* shll #imm:5, rs, rd */ static bool trans_SHLL_irr(DisasContext *ctx, arg_SHLL_irr *a) { - prt("shll\t#%d, ", a->imm); if (a->rs2 !=3D a->rd) { - prt("r%d, ", a->rs2); + prt("shll\t#%d, r%d, r%d", a->imm, a->rs2, a->rd); + } else { + prt("shll\t#%d, r%d", a->imm, a->rd); } - prt("r%d", a->rd); return true; } =20 @@ -752,11 +755,11 @@ static bool trans_SHLL_rr(DisasContext *ctx, arg_SHLL= _rr *a) /* shar #imm:5, rs, rd */ static bool trans_SHAR_irr(DisasContext *ctx, arg_SHAR_irr *a) { - prt("shar\t#%d,", a->imm); if (a->rs2 !=3D a->rd) { - prt("r%d, ", a->rs2); + prt("shar\t#%d, r%d, r%d", a->imm, a->rs2, a->rd); + } else { + prt("shar\t#%d, r%d", a->imm, a->rd); } - prt("r%d", a->rd); return true; } =20 @@ -771,11 +774,11 @@ static bool trans_SHAR_rr(DisasContext *ctx, arg_SHAR= _rr *a) /* shlr #imm:5, rs, rd */ static bool trans_SHLR_irr(DisasContext *ctx, arg_SHLR_irr *a) { - prt("shlr\t#%d, ", a->imm); if (a->rs2 !=3D a->rd) { - prt("r%d, ", a->rs2); + prt("shlr\t#%d, r%d, r%d", a->imm, a->rs2, a->rd); + } else { + prt("shlr\t#%d, r%d", a->imm, a->rd); } - prt("r%d", a->rd); return true; } =20 --=20 2.21.1 From nobody Sun May 5 08:48:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1584463582; cv=none; d=zohomail.com; s=zohoarc; b=Pfeg03nyowNLKsxv95vX34Hw7wkQMs3OqJgaa+pviiiwq4Ksu/P5kxVy/oGdGBFb0fkUPUrFNtCsiUq42V9nezwVDw+ICV2aEk5IkAEAk5F0AhSqpgrD4fk4ad9drGm1eHu2RTzdeWBzVy+Tq4cAF3SrCU+7dGHWhnJSS8fNa4s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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[83.59.163.96]) by smtp.gmail.com with ESMTPSA id b202sm4618697wmd.15.2020.03.17.09.36.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Mar 2020 09:36:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=T0CiFFiWYIaYPKYRBKJcJx8291mmGW0+BGwrLGbj5DM=; b=dVlUAW+bq0fqQaimnqyzzZBO/DO3zzFS0V4nYLEc05tUX9r2CRZEZ7ijYbpJS6s6K7 W9765FKZNyNMlk0THX3LriDxOJ2cCBxsgFfFKLIi8qAZKIg47zI7b1n8zhpZwOrGWdoq YzV8t2N+RbxTA7EsRWGNMsKcO2bz6Pwt7KScCC6VPWsx3d2dCuv/Vx778DxHsIY53/uX QPwiy4F7OPCEgOSMTjaEKqwe2cOaR384QHupu/v5Ve6/DtQoQ702fuRYePN0o3xuq2+F K+gCjDk5BC/0eLnL3WWCLi6NlvYwqcQgVBXarhEVfh+Tz2VN65vdoD12f1VyGt8qkM5s MTGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=T0CiFFiWYIaYPKYRBKJcJx8291mmGW0+BGwrLGbj5DM=; b=ekPOSJxbC1b63ZCgKStZnNP8nvDad2xWcdICH/T0PmEIN6Vq/F5i5lwas8QxhJUe6O DKH1PmgTa2uOi+4yJw7yBI5nAdMo5jboxtCfmewL+dz0SUHoS8AKI5AEiQVDEy0MrQAk qcGnKwHNipFpAs9KUGGqR2nC+4Nr4mi9E+4oLcHejKWp2zgpylub6cEtI/f+HCAoWNVm sStpDKkSEg2rNf0LC3SQ8UGr7dqIwUxhfJ4xy3j7SfV9nMGN41B+2DqxRqYujVdvVoFO st9KR9QmjVFI48jHKQKOXKCd8ijarGiRCJj7rKQZzssdnqu9+FIylr1uhiUWnPZI58zo mjOQ== X-Gm-Message-State: ANhLgQ013OppKrQiWwTq+oWKkUAuSnSwI0z9rdBZ8LIimRKhu8xZEdzH s4Z/xpmiYAIKACUnnANSv5Rds3qZ X-Google-Smtp-Source: ADFU+vvuF0MIbiehFjIvk2RyW9VAOtipQBMe/iSeKTTdSiPULBYopShQ0WSmPqeolN0vy7qmcdPXmg== X-Received: by 2002:a05:600c:14d5:: with SMTP id i21mr167586wmh.82.1584462993256; Tue, 17 Mar 2020 09:36:33 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 11/13] target/rx: Collect all bytes during disassembly Date: Tue, 17 Mar 2020 17:36:14 +0100 Message-Id: <20200317163616.30027-12-f4bug@amsat.org> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200317163616.30027-1-f4bug@amsat.org> References: <20200317163616.30027-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::343 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yoshinori Sato , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Richard Henderson Collected, to be used in the next patch. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Yoshinori Sato Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-Id: <20190531134315.4109-23-richard.henderson@linaro.org> Acked-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/rx/disas.c | 62 ++++++++++++++++++++++++++++++++--------------- 1 file changed, 42 insertions(+), 20 deletions(-) diff --git a/target/rx/disas.c b/target/rx/disas.c index 814ef97480..dcfb7baf99 100644 --- a/target/rx/disas.c +++ b/target/rx/disas.c @@ -25,43 +25,59 @@ typedef struct DisasContext { disassemble_info *dis; uint32_t addr; uint32_t pc; + uint8_t len; + uint8_t bytes[8]; } DisasContext; =20 =20 static uint32_t decode_load_bytes(DisasContext *ctx, uint32_t insn, - int i, int n) + int i, int n) { - bfd_byte buf; + uint32_t addr =3D ctx->addr; + + g_assert(ctx->len =3D=3D i); + g_assert(n <=3D ARRAY_SIZE(ctx->bytes)); + while (++i <=3D n) { - ctx->dis->read_memory_func(ctx->addr++, &buf, 1, ctx->dis); - insn |=3D buf << (32 - i * 8); + ctx->dis->read_memory_func(addr++, &ctx->bytes[i - 1], 1, ctx->dis= ); + insn |=3D ctx->bytes[i - 1] << (32 - i * 8); } + ctx->addr =3D addr; + ctx->len =3D n; + return insn; } =20 static int32_t li(DisasContext *ctx, int sz) { - int32_t addr; - bfd_byte buf[4]; - addr =3D ctx->addr; + uint32_t addr =3D ctx->addr; + uintptr_t len =3D ctx->len; =20 switch (sz) { case 1: + g_assert(len + 1 <=3D ARRAY_SIZE(ctx->bytes)); ctx->addr +=3D 1; - ctx->dis->read_memory_func(addr, buf, 1, ctx->dis); - return (int8_t)buf[0]; + ctx->len +=3D 1; + ctx->dis->read_memory_func(addr, ctx->bytes + len, 1, ctx->dis); + return (int8_t)ctx->bytes[len]; case 2: + g_assert(len + 2 <=3D ARRAY_SIZE(ctx->bytes)); ctx->addr +=3D 2; - ctx->dis->read_memory_func(addr, buf, 2, ctx->dis); - return ldsw_le_p(buf); + ctx->len +=3D 2; + ctx->dis->read_memory_func(addr, ctx->bytes + len, 2, ctx->dis); + return ldsw_le_p(ctx->bytes + len); case 3: + g_assert(len + 3 <=3D ARRAY_SIZE(ctx->bytes)); ctx->addr +=3D 3; - ctx->dis->read_memory_func(addr, buf, 3, ctx->dis); - return (int8_t)buf[2] << 16 | lduw_le_p(buf); + ctx->len +=3D 3; + ctx->dis->read_memory_func(addr, ctx->bytes + len, 3, ctx->dis); + return (int8_t)ctx->bytes[len + 2] << 16 | lduw_le_p(ctx->bytes + = len); case 0: + g_assert(len + 4 <=3D ARRAY_SIZE(ctx->bytes)); ctx->addr +=3D 4; - ctx->dis->read_memory_func(addr, buf, 4, ctx->dis); - return ldl_le_p(buf); + ctx->len +=3D 4; + ctx->dis->read_memory_func(addr, ctx->bytes + len, 4, ctx->dis); + return ldl_le_p(ctx->bytes + len); default: g_assert_not_reached(); } @@ -110,7 +126,7 @@ static const char psw[] =3D { static void rx_index_addr(DisasContext *ctx, char out[8], int ld, int mi) { uint32_t addr =3D ctx->addr; - uint8_t buf[2]; + uintptr_t len =3D ctx->len; uint16_t dsp; =20 switch (ld) { @@ -119,14 +135,18 @@ static void rx_index_addr(DisasContext *ctx, char out= [8], int ld, int mi) out[0] =3D '\0'; return; case 1: + g_assert(len + 1 <=3D ARRAY_SIZE(ctx->bytes)); ctx->addr +=3D 1; - ctx->dis->read_memory_func(addr, buf, 1, ctx->dis); - dsp =3D buf[0]; + ctx->len +=3D 1; + ctx->dis->read_memory_func(addr, ctx->bytes + len, 1, ctx->dis); + dsp =3D ctx->bytes[len]; break; case 2: + g_assert(len + 2 <=3D ARRAY_SIZE(ctx->bytes)); ctx->addr +=3D 2; - ctx->dis->read_memory_func(addr, buf, 2, ctx->dis); - dsp =3D lduw_le_p(buf); + ctx->len +=3D 2; + ctx->dis->read_memory_func(addr, ctx->bytes + len, 2, ctx->dis); + dsp =3D lduw_le_p(ctx->bytes + len); break; default: g_assert_not_reached(); @@ -1392,8 +1412,10 @@ int print_insn_rx(bfd_vma addr, disassemble_info *di= s) DisasContext ctx; uint32_t insn; int i; + ctx.dis =3D dis; ctx.pc =3D ctx.addr =3D addr; + ctx.len =3D 0; =20 insn =3D decode_load(&ctx); if (!decode(&ctx, insn)) { --=20 2.21.1 From nobody Sun May 5 08:48:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[83.59.163.96]) by smtp.gmail.com with ESMTPSA id b202sm4618697wmd.15.2020.03.17.09.36.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Mar 2020 09:36:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mfXBsBn9LUhSN6WgjaxZSay9usosB3zq5/7Zod3QK24=; b=QUEYm0GvgtCTNgoqFK+49ALq0djvwNFe8r0Xv+LW/Ri4C19e9ps7Z2wAGtxu5r//9f ROkmA6VWTsMns3NN2D+6Qs/V5K63h/AxbvmhP5yfgwePIPfFScyJu3flpVE3r5s0ivsF zyHvRq6AKPieVIR50GBCat0tnwWvr3obgCG5jVMtIQWCWtGQnZG5a636A3GX2+vut1i9 mggir+p+4M1U7/gldFuJAfprah/nWk6zRgQ74PRlCekRYFOOPHI3esHYstiM4GpGutfl bvHBsBC1IACsMAnnIAtwxTvkBF8UH1FtIRRhd+RxTshfyK9VdWZr8+QXaYVIK3vHAbaS A9pQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=mfXBsBn9LUhSN6WgjaxZSay9usosB3zq5/7Zod3QK24=; b=EZwKcQbcKhOEJOlyFY4PokuAf3w4zpgJG6PWlN3suTRWbUVG/QCqi2SL8uuUJHMLgH cj0LgRfbSt0PrJLSoBuY7f80B3B3ri5MhNuCuMeCTa7uUcS7R3vPx01wdg+tYsxM4QID yv2AvqDPaAgPgA4OjMuNLlO2g2O5H2viXB3Png0bikIk78ft2iG/Bg98Dq/of00H8Wqm a32z93itv/PyXaQNcMNb4+41qxv0VYemlfUgNizMzVutUvsupGq7lCukjnxZVFP4ZMLr IRktO4+PwUq/8WfDL8y+S1exwB57Fcej2tq6GybZiVpNSQnCsid7fNn0LJOehVE1rWwf PqbQ== X-Gm-Message-State: ANhLgQ1tXiPzUr+qZMmWb6aBwCIYP2kgFR9z2Iz6ucJIaeRK+CsgOG9a LafO/3fXUEmu1/FWoHUrylalSYku X-Google-Smtp-Source: ADFU+vu8MQpL6fMH0lHScUI41zm4gGAnlcUOc+fKFS+r6hLbYszFO5ukKdhCg6U/BkJPmU061awhhQ== X-Received: by 2002:a5d:5342:: with SMTP id t2mr7085696wrv.104.1584462994353; Tue, 17 Mar 2020 09:36:34 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 12/13] target/rx: Dump bytes for each insn during disassembly Date: Tue, 17 Mar 2020 17:36:15 +0100 Message-Id: <20200317163616.30027-13-f4bug@amsat.org> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200317163616.30027-1-f4bug@amsat.org> References: <20200317163616.30027-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::429 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yoshinori Sato , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Richard Henderson There are so many different forms of each RX instruction that it will be very useful to be able to look at the bytes to see on which path a bug may lie. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Yoshinori Sato Tested-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson Message-Id: <20190531134315.4109-24-richard.henderson@linaro.org> Acked-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/rx/disas.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/target/rx/disas.c b/target/rx/disas.c index dcfb7baf99..6dee7a0342 100644 --- a/target/rx/disas.c +++ b/target/rx/disas.c @@ -102,7 +102,21 @@ static int bdsp_s(DisasContext *ctx, int d) /* Include the auto-generated decoder. */ #include "decode.inc.c" =20 -#define prt(...) (ctx->dis->fprintf_func)((ctx->dis->stream), __VA_ARGS__) +static void dump_bytes(DisasContext *ctx) +{ + int i, len =3D ctx->len; + + for (i =3D 0; i < len; ++i) { + ctx->dis->fprintf_func(ctx->dis->stream, "%02x ", ctx->bytes[i]); + } + ctx->dis->fprintf_func(ctx->dis->stream, "%*c", (8 - i) * 3, '\t'); +} + +#define prt(...) \ + do { \ + dump_bytes(ctx); \ + ctx->dis->fprintf_func(ctx->dis->stream, __VA_ARGS__); \ + } while (0) =20 #define RX_MEMORY_BYTE 0 #define RX_MEMORY_WORD 1 --=20 2.21.1 From nobody Sun May 5 08:48:53 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1584464292; cv=none; d=zohomail.com; s=zohoarc; b=JlAvG7kF2emoGAhVnoHGcVhIVU7WRry1p00GtV9+WxP28E9Ix2QK4gHLtweinEctr2bFOZudxYKFXwz9bifJKLiNtXX+wKZ2DK8QqB1K9n8I61zbQZbQ4idW+cIlmQhndb0j3QvMRePHDyLTvJtB4eG0JC2eJUlfUuuqfN5MoUw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1584464292; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=DlkS/lJlVKWDegsd0LArtsnfUSESor37RBYt82J35Yw=; b=f0B/8/8edfHv2oZkyg5Uk9xoqs+ODAV+qMRrN1sl06QCwul+LTwWtm3q+PjLQkZpCLYuwLbm/0oBFZEwtd8qK+HDoldQ3OBmTHtfDHAIl36aUXm468328UX9CgCmU//p+DH9QJsI/djDLNxKdE3Mtv3HD8ubGTMiUEDK42faAlA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1584464292095550.6137645181352; Tue, 17 Mar 2020 09:58:12 -0700 (PDT) Received: from localhost ([::1]:37007 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jEFXe-0003O0-Tz for importer@patchew.org; Tue, 17 Mar 2020 12:58:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36070) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jEFCp-00042x-CW for qemu-devel@nongnu.org; Tue, 17 Mar 2020 12:36:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jEFCn-0004F1-FN for qemu-devel@nongnu.org; Tue, 17 Mar 2020 12:36:39 -0400 Received: from mail-wm1-x344.google.com ([2a00:1450:4864:20::344]:55969) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1jEFCn-00048f-5j for qemu-devel@nongnu.org; Tue, 17 Mar 2020 12:36:37 -0400 Received: by mail-wm1-x344.google.com with SMTP id 6so22193236wmi.5 for ; Tue, 17 Mar 2020 09:36:37 -0700 (PDT) Received: from x1w.redhat.com (96.red-83-59-163.dynamicip.rima-tde.net. [83.59.163.96]) by smtp.gmail.com with ESMTPSA id b202sm4618697wmd.15.2020.03.17.09.36.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 17 Mar 2020 09:36:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=sender:from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DlkS/lJlVKWDegsd0LArtsnfUSESor37RBYt82J35Yw=; b=bxE6A7i+0ViPtVoiqCdCdDrujxlJBXwkn71i2LpXhhXLnuF8qCjH4Ff1qhsXKTieZE eFoo9hrDF/fmtWmH9APLaUXP+U7fYcTeR5dm3Xg2YQ+GEnidoaqh3sVRdvd99T7M23ZX /VnSnJp3Vwn1fnfhBn5Ax8hSBtwZ8EJ6BYwrwGLLwpQMTFvH8STF+l9IKKqKSRUhON2B f/dsNQjaYwcLNMXxwsHyV/cA93l/Y9IwlVNfwBIbWj0FWukWVNqyUxVqd4FF1CvvIXqb Ofx3GlHykva1hZrVV5VFTKIHFc5zvsq2AyQg011mzUFUiytEUVXzC2MZwctSieJQLsYf Gj7w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:sender:from:to:cc:subject:date:message-id :in-reply-to:references:mime-version:content-transfer-encoding; bh=DlkS/lJlVKWDegsd0LArtsnfUSESor37RBYt82J35Yw=; b=TV0NDuN3d/DwbYuh+9O6505OlaaX2FkPUhncDaPG4NQByAzrfRasju54mpauGegaQP 9/qeF3mvbCtIAG+OA1TxcbMhoTXLMbJv1IiBjV1XhNgiQVKOfUzP7Zj/4naLDTM1C3rt ZSPtxcN+RY55wWs1PnhaUOl4JAio9quIgdwLsILx4BB//pUFNfaovCtjcGaZMdKqjj1q +g6mTT25OL4kOTVAcmpyiDEKP6z/JBXq+BWAQbS5PDERKxHvgYhr0Gll44RR4Ufh684U 2uqP3L7Qfsmwe77EgJv1c4Wjtuqa8ApbERRN9zFS6LfPO0DVkQid2s9/tNFC/4qS9k5w fbkg== X-Gm-Message-State: ANhLgQ1rWtzw4PbdK3PkLbBG0JQQnKiuNtmJ+ORMFLcUAlV/6+4enfOn +Tg1j3XiqvNZpuMxmxBBuv+klY8t X-Google-Smtp-Source: ADFU+vuX8EYPXndq3XvjHfi3dSsQu5SHQg1fkgyygrhIJOPHtax7m6Jll5YSku2AFT5NUNxWUP2qNw== X-Received: by 2002:a1c:6a07:: with SMTP id f7mr170913wmc.38.1584462995783; Tue, 17 Mar 2020 09:36:35 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PULL 13/13] Add rx-softmmu Date: Tue, 17 Mar 2020 17:36:16 +0100 Message-Id: <20200317163616.30027-14-f4bug@amsat.org> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200317163616.30027-1-f4bug@amsat.org> References: <20200317163616.30027-1-f4bug@amsat.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2a00:1450:4864:20::344 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Laurent Vivier , Thomas Huth , Eduardo Habkost , Yoshinori Sato , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Markus Armbruster , Paolo Bonzini , Richard Henderson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) From: Yoshinori Sato Tested-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Yoshinori Sato Signed-off-by: Richard Henderson [PMD: Squashed patches from Richard Henderson modifying qapi/common.json and tests/machine-none-test.c] Message-Id: <20200224141923.82118-21-ysato@users.sourceforge.jp> [PMD: Added @since 5.0 tag in SysEmuTarget] Acked-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- configure | 11 ++++++++++- default-configs/rx-softmmu.mak | 2 ++ qapi/machine.json | 4 +++- include/exec/poison.h | 1 + include/sysemu/arch_init.h | 1 + arch_init.c | 2 ++ tests/qtest/machine-none-test.c | 1 + 7 files changed, 20 insertions(+), 2 deletions(-) create mode 100644 default-configs/rx-softmmu.mak diff --git a/configure b/configure index eb49bb6680..f9586cbc34 100755 --- a/configure +++ b/configure @@ -4184,7 +4184,7 @@ fi fdt_required=3Dno for target in $target_list; do case $target in - aarch64*-softmmu|arm*-softmmu|ppc*-softmmu|microblaze*-softmmu|mips64e= l-softmmu|riscv*-softmmu) + aarch64*-softmmu|arm*-softmmu|ppc*-softmmu|microblaze*-softmmu|mips64e= l-softmmu|riscv*-softmmu|rx-softmmu) fdt_required=3Dyes ;; esac @@ -7881,6 +7881,12 @@ case "$target_name" in mttcg=3Dyes gdb_xml_files=3D"riscv-64bit-cpu.xml riscv-32bit-fpu.xml riscv-64bit-f= pu.xml riscv-64bit-csr.xml riscv-64bit-virtual.xml" ;; + rx) + TARGET_ARCH=3Drx + bflt=3D"yes" + target_compiler=3D$cross_cc_rx + gdb_xml_files=3D"rx-core.xml" + ;; sh4|sh4eb) TARGET_ARCH=3Dsh4 bflt=3D"yes" @@ -8062,6 +8068,9 @@ for i in $ARCH $TARGET_BASE_ARCH ; do riscv*) disas_config "RISCV" ;; + rx) + disas_config "RX" + ;; s390*) disas_config "S390" ;; diff --git a/default-configs/rx-softmmu.mak b/default-configs/rx-softmmu.mak new file mode 100644 index 0000000000..7c4eb2c1a0 --- /dev/null +++ b/default-configs/rx-softmmu.mak @@ -0,0 +1,2 @@ +# Default configuration for rx-softmmu + diff --git a/qapi/machine.json b/qapi/machine.json index 6c11e3cf3a..282d247097 100644 --- a/qapi/machine.json +++ b/qapi/machine.json @@ -16,6 +16,8 @@ # individual target constants are not documented here, for the time # being. # +# @rx: since 5.0 +# # Notes: The resulting QMP strings can be appended to the "qemu-system-" # prefix to produce the corresponding QEMU executable name. This # is true even for "qemu-system-x86_64". @@ -26,7 +28,7 @@ 'data' : [ 'aarch64', 'alpha', 'arm', 'cris', 'hppa', 'i386', 'lm32', 'm68k', 'microblaze', 'microblazeel', 'mips', 'mips64', 'mips64el', 'mipsel', 'moxie', 'nios2', 'or1k', 'ppc', - 'ppc64', 'riscv32', 'riscv64', 's390x', 'sh4', + 'ppc64', 'riscv32', 'riscv64', 'rx', 's390x', 'sh4', 'sh4eb', 'sparc', 'sparc64', 'tricore', 'unicore32', 'x86_64', 'xtensa', 'xtensaeb' ] } =20 diff --git a/include/exec/poison.h b/include/exec/poison.h index 955eb863ab..7b9ac361dc 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -26,6 +26,7 @@ #pragma GCC poison TARGET_PPC #pragma GCC poison TARGET_PPC64 #pragma GCC poison TARGET_ABI32 +#pragma GCC poison TARGET_RX #pragma GCC poison TARGET_S390X #pragma GCC poison TARGET_SH4 #pragma GCC poison TARGET_SPARC diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h index 01392dc945..71a7a285ee 100644 --- a/include/sysemu/arch_init.h +++ b/include/sysemu/arch_init.h @@ -24,6 +24,7 @@ enum { QEMU_ARCH_NIOS2 =3D (1 << 17), QEMU_ARCH_HPPA =3D (1 << 18), QEMU_ARCH_RISCV =3D (1 << 19), + QEMU_ARCH_RX =3D (1 << 20), =20 QEMU_ARCH_NONE =3D (1 << 31), }; diff --git a/arch_init.c b/arch_init.c index 705d0b94ad..d9eb0ec1dd 100644 --- a/arch_init.c +++ b/arch_init.c @@ -77,6 +77,8 @@ int graphic_depth =3D 32; #define QEMU_ARCH QEMU_ARCH_PPC #elif defined(TARGET_RISCV) #define QEMU_ARCH QEMU_ARCH_RISCV +#elif defined(TARGET_RX) +#define QEMU_ARCH QEMU_ARCH_RX #elif defined(TARGET_S390X) #define QEMU_ARCH QEMU_ARCH_S390X #elif defined(TARGET_SH4) diff --git a/tests/qtest/machine-none-test.c b/tests/qtest/machine-none-tes= t.c index 5953d31755..8bb54a6360 100644 --- a/tests/qtest/machine-none-test.c +++ b/tests/qtest/machine-none-test.c @@ -56,6 +56,7 @@ static struct arch2cpu cpus_map[] =3D { { "hppa", "hppa" }, { "riscv64", "rv64gcsu-v1.10.0" }, { "riscv32", "rv32gcsu-v1.9.1" }, + { "rx", "rx62n" }, }; =20 static const char *get_cpu_model_by_arch(const char *arch) --=20 2.21.1