From nobody Thu Oct 2 03:23:00 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1584439592; cv=none; d=zohomail.com; s=zohoarc; b=Gp1egRGneT5PPLwtPh7SwS8SMQ1vtMjYDmn6qqp2r9vg/mKXquPxnUPdTs5O1A91W9Ug9cdMXe8sDh0lbRewv4ecfcHTVaANvA0aReD4VTrQIc23s1wszOZ7WFD+g2SCz5ohwK26HLuvw0JxVbKd+jiUA++S3flA5c6GngvCbCU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1584439592; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/qjW9sS7iafnahFTpVEW2o+pyS9SNuO2ndLD5OKIv/Y=; b=l/gn/PsokkEVoKIw7N5gepV7E2tMtZoa5IiyL9ASQHZckg9zz+3SO1eyfrIOnZvcr+FMCe9X3seaFdSOGLbpysn5BS6G1uc9UOFjakaEChvN5ETGtGgZPZrwDW/LHFZoVF3SR1h3z//KpLukMalRLL6Uv1UIUAAAaeIO14lDrPw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1584439592473502.1320237778323; Tue, 17 Mar 2020 03:06:32 -0700 (PDT) Received: from localhost ([::1]:55524 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jE97H-0002xa-91 for importer@patchew.org; Tue, 17 Mar 2020 06:06:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45067) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jE95c-0000oJ-Bf for qemu-devel@nongnu.org; Tue, 17 Mar 2020 06:04:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jE95a-0001s3-EY for qemu-devel@nongnu.org; Tue, 17 Mar 2020 06:04:48 -0400 Received: from ozlabs.org ([203.11.71.1]:45151) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jE95a-0001Go-1L; Tue, 17 Mar 2020 06:04:46 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 48hTKw0bH8z9sSY; Tue, 17 Mar 2020 21:04:35 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1584439476; bh=+B1mCWC4t6yy2Tx65wsvNsRLsoZ3PfvGpSRZfwW2BjM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jAqguzUoPqeepq1qwHglZLEBGJ3/YADqABhhxD6vs11ds2jTCHkiIwW4TM32v4wfG CXEa/2rRxQRakgA7ks6s9C0fMpZaTcTzqAVNM6SxI2DH0j9GrgxmW8Hx++XA3Y57PU nZPFNjz5AfuV3PenC5ET31X7wE52ykX6wRhXesXM= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 07/45] ppc: Remove stub of PPC970 HID4 implementation Date: Tue, 17 Mar 2020 21:03:45 +1100 Message-Id: <20200317100423.622643-8-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200317100423.622643-1-david@gibson.dropbear.id.au> References: <20200317100423.622643-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, mdroth@linux.vnet.ibm.com, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" The PowerPC 970 CPU was a cut-down POWER4, which had hypervisor capability. However, it can be (and often was) strapped into "Apple mode", where the hypervisor capabilities were disabled (essentially putting it always in hypervisor mode). That's actually the only mode of the 970 we support in qemu, and we're unlikely to change that any time soon. However, we do have a partial implementation of the 970's HID4 register which affects things only relevant for hypervisor mode. That stub is also really ugly, since it attempts to duplicate the effects of HID4 by re-encoding it into the LPCR register used in newer CPUs, but in a really confusing way. Just get rid of it. Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Greg Kurz --- target/ppc/mmu-hash64.c | 29 +---------------------------- target/ppc/translate_init.inc.c | 20 ++++++++------------ 2 files changed, 9 insertions(+), 40 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index da8966ccf5..3e0be4d55f 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -1091,33 +1091,6 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong va= l) =20 /* Filter out bits */ switch (env->mmu_model) { - case POWERPC_MMU_64B: /* 970 */ - if (val & 0x40) { - lpcr |=3D LPCR_LPES0; - } - if (val & 0x8000000000000000ull) { - lpcr |=3D LPCR_LPES1; - } - if (val & 0x20) { - lpcr |=3D (0x4ull << LPCR_RMLS_SHIFT); - } - if (val & 0x4000000000000000ull) { - lpcr |=3D (0x2ull << LPCR_RMLS_SHIFT); - } - if (val & 0x2000000000000000ull) { - lpcr |=3D (0x1ull << LPCR_RMLS_SHIFT); - } - env->spr[SPR_RMOR] =3D ((lpcr >> 41) & 0xffffull) << 26; - - /* - * XXX We could also write LPID from HID4 here - * but since we don't tag any translation on it - * it doesn't actually matter - * - * XXX For proper emulation of 970 we also need - * to dig HRMOR out of HID5 - */ - break; case POWERPC_MMU_2_03: /* P5p */ lpcr =3D val & (LPCR_RMLS | LPCR_ILE | LPCR_LPES0 | LPCR_LPES1 | @@ -1154,7 +1127,7 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) } break; default: - ; + g_assert_not_reached(); } env->spr[SPR_LPCR] =3D lpcr; ppc_hash64_update_rmls(cpu); diff --git a/target/ppc/translate_init.inc.c b/target/ppc/translate_init.in= c.c index df3401cf06..aecad96db3 100644 --- a/target/ppc/translate_init.inc.c +++ b/target/ppc/translate_init.inc.c @@ -7895,25 +7895,21 @@ static void spr_write_lpcr(DisasContext *ctx, int s= prn, int gprn) { gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); } - -static void spr_write_970_hid4(DisasContext *ctx, int sprn, int gprn) -{ -#if defined(TARGET_PPC64) - spr_write_generic(ctx, sprn, gprn); - gen_helper_store_lpcr(cpu_env, cpu_gpr[gprn]); -#endif -} - #endif /* !defined(CONFIG_USER_ONLY) */ =20 static void gen_spr_970_lpar(CPUPPCState *env) { #if !defined(CONFIG_USER_ONLY) - /* Logical partitionning */ - /* PPC970: HID4 is effectively the LPCR */ + /* + * PPC970: HID4 covers things later controlled by the LPCR and + * RMOR in later CPUs, but with a different encoding. We only + * support the 970 in "Apple mode" which has all hypervisor + * facilities disabled by strapping, so we can basically just + * ignore it + */ spr_register(env, SPR_970_HID4, "HID4", SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_970_hid4, + &spr_read_generic, &spr_write_generic, 0x00000000); #endif } --=20 2.24.1