From nobody Thu Oct 2 03:25:05 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1584439937; cv=none; d=zohomail.com; s=zohoarc; b=Du5aLUJVAKuDq39fJ3X6aZc1T6SBnZe5/PTbckP3E3niWWSipzf1GZV4zbHyj/fsfoQZdTyyhbC7+1bDly8a+9T3Q7I9zO5tVyGQsD55hb11ePOn5RJU7pWkkRVwrlmyEzXsI27wTXe8McOuSfMtcqks9I15rA0V7F9lA+sEW68= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1584439937; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HAM61olrpqDvBTnYzhUY176bR86ugLgoPW3lIPXFucE=; b=SzU+2x71WO/bLB3AeGUYtzPrej2uNJLZHEEPIncjEe72Os/8dgcy6mXIgJj3D3klizAYN6HRkhCotmd3mXxbijmi4LPaeFCWri6cmiDxUDexZXUpbed7vGrXg1HK/Gsyb95xrLZlWIGiY1uriPtz+HTJIm5V1TSyCfgpODbQR9I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1584439937148193.93959167774574; Tue, 17 Mar 2020 03:12:17 -0700 (PDT) Received: from localhost ([::1]:55622 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jE9Cp-0005xI-UV for importer@patchew.org; Tue, 17 Mar 2020 06:12:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45215) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jE95g-0000wZ-Qm for qemu-devel@nongnu.org; Tue, 17 Mar 2020 06:04:55 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jE95e-0002Q6-Q0 for qemu-devel@nongnu.org; Tue, 17 Mar 2020 06:04:52 -0400 Received: from ozlabs.org ([203.11.71.1]:52181) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jE95e-0001nm-Di; Tue, 17 Mar 2020 06:04:50 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 48hTKw3BL0z9sSj; Tue, 17 Mar 2020 21:04:36 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1584439476; bh=yA5zXTiRWRVp48qt3pq/p1pz/XgyQFx8TgbqmRi8ySQ=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=I44Ecup9eyI1WQ0goKS+6IqVXzcR2OOfmZLK+o/s9zl7/nSbGAiTsRJGuXakPh74t sLqWnC1aHioi3rkP2G9BMh9ajHNnXomPnp9dcp6yp2u6eszhxoYz4TvtErwKV1GH5M o0vwI5Ekhp2PFXKRvob2J7X87r1CO/6LMoLv7rpQ= From: David Gibson To: peter.maydell@linaro.org Subject: [PULL 13/45] target/ppc: Streamline calculation of RMA limit from LPCR[RMLS] Date: Tue, 17 Mar 2020 21:03:51 +1100 Message-Id: <20200317100423.622643-14-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20200317100423.622643-1-david@gibson.dropbear.id.au> References: <20200317100423.622643-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lvivier@redhat.com, aik@ozlabs.ru, mdroth@linux.vnet.ibm.com, qemu-devel@nongnu.org, groug@kaod.org, qemu-ppc@nongnu.org, clg@kaod.org, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Currently we use a big switch statement in ppc_hash64_update_rmls() to work out what the right RMA limit is based on the LPCR[RMLS] field. There's no formula for this - it's just an arbitrary mapping defined by the existing CPU implementations - but we can make it a bit more readable by using a lookup table rather than a switch. In addition we can use the MiB/GiB symbols to make it a bit clearer. While there we add a bit of clarity and rationale to the comment about what happens if the LPCR[RMLS] doesn't contain a valid value. Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Greg Kurz Reviewed-by: Philippe Mathieu-Daud=C3=A9 --- target/ppc/mmu-hash64.c | 63 ++++++++++++++++++----------------------- 1 file changed, 27 insertions(+), 36 deletions(-) diff --git a/target/ppc/mmu-hash64.c b/target/ppc/mmu-hash64.c index 0ef330a614..934989e6d9 100644 --- a/target/ppc/mmu-hash64.c +++ b/target/ppc/mmu-hash64.c @@ -18,6 +18,7 @@ * License along with this library; if not, see . */ #include "qemu/osdep.h" +#include "qemu/units.h" #include "cpu.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" @@ -757,6 +758,31 @@ static void ppc_hash64_set_c(PowerPCCPU *cpu, hwaddr p= tex, uint64_t pte1) stb_phys(CPU(cpu)->as, base + offset, (pte1 & 0xff) | 0x80); } =20 +static target_ulong rmls_limit(PowerPCCPU *cpu) +{ + CPUPPCState *env =3D &cpu->env; + /* + * This is the full 4 bits encoding of POWER8. Previous + * CPUs only support a subset of these but the filtering + * is done when writing LPCR. + * + * Unsupported values mean the OS has shot itself in the + * foot. Return a 0-sized RMA in this case, which we expect + * to trigger an immediate DSI or ISI + */ + static const target_ulong rma_sizes[16] =3D { + [1] =3D 16 * GiB, + [2] =3D 1 * GiB, + [3] =3D 64 * MiB, + [4] =3D 256 * MiB, + [7] =3D 128 * MiB, + [8] =3D 32 * MiB, + }; + target_ulong rmls =3D (env->spr[SPR_LPCR] & LPCR_RMLS) >> LPCR_RMLS_SH= IFT; + + return rma_sizes[rmls]; +} + int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, vaddr eaddr, int rwx, int mmu_idx) { @@ -1006,41 +1032,6 @@ void ppc_hash64_tlb_flush_hpte(PowerPCCPU *cpu, targ= et_ulong ptex, cpu->env.tlb_need_flush =3D TLB_NEED_GLOBAL_FLUSH | TLB_NEED_LOCAL_FLU= SH; } =20 -static void ppc_hash64_update_rmls(PowerPCCPU *cpu) -{ - CPUPPCState *env =3D &cpu->env; - uint64_t lpcr =3D env->spr[SPR_LPCR]; - - /* - * This is the full 4 bits encoding of POWER8. Previous - * CPUs only support a subset of these but the filtering - * is done when writing LPCR - */ - switch ((lpcr & LPCR_RMLS) >> LPCR_RMLS_SHIFT) { - case 0x8: /* 32MB */ - env->rmls =3D 0x2000000ull; - break; - case 0x3: /* 64MB */ - env->rmls =3D 0x4000000ull; - break; - case 0x7: /* 128MB */ - env->rmls =3D 0x8000000ull; - break; - case 0x4: /* 256MB */ - env->rmls =3D 0x10000000ull; - break; - case 0x2: /* 1GB */ - env->rmls =3D 0x40000000ull; - break; - case 0x1: /* 16GB */ - env->rmls =3D 0x400000000ull; - break; - default: - /* What to do here ??? */ - env->rmls =3D 0; - } -} - static void ppc_hash64_update_vrma(PowerPCCPU *cpu) { CPUPPCState *env =3D &cpu->env; @@ -1099,7 +1090,7 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) CPUPPCState *env =3D &cpu->env; =20 env->spr[SPR_LPCR] =3D val & pcc->lpcr_mask; - ppc_hash64_update_rmls(cpu); + env->rmls =3D rmls_limit(cpu); ppc_hash64_update_vrma(cpu); } =20 --=20 2.24.1