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[83.59.163.96]) by smtp.gmail.com with ESMTPSA id a10sm480884wrv.89.2020.03.16.09.06.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:06:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1584374807; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=36JPzoDFwtpu9mZ2fPnU6GKIA7vaoxIQMhsyqosn0aE=; b=UmIE8y0uIJJrTiJcThtamZZ+8P5h2Lg70OZFskITG6CSLicKHTxfEjm76j5to4kPZtk6RP KOt0jdwGmMNIy7imtt3RtXn3nBAh1e3n47ubIRuNfxHqDVi4Spbi1vntVIzHtOUtwhX3Ak I5h390i3Bs3KrIfrB8IHLmHOzKl5Cvo= X-MC-Unique: f_fmdmO2Oj6KH5MlYH8ihg-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WUQmK3jX+ITRgjT53gJOYB77qbIWiqXEgYr8J8FbjTA=; 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charset="utf-8"; text/plain; charset="utf-8" Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/kvm32.c | 10 +++++----- target/arm/kvm64.c | 16 ++++++++-------- 2 files changed, 13 insertions(+), 13 deletions(-) diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index f271181ab8..0ab28b473a 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -22,7 +22,7 @@ #include "internals.h" #include "qemu/log.h" =20 -static inline void set_feature(uint64_t *features, int feature) +static inline void kvm_set_feature(uint64_t *features, int feature) { *features |=3D 1ULL << feature; } @@ -146,14 +146,14 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures= *ahcf) * timers; this in turn implies most of the other feature * bits, but a few must be tested. */ - set_feature(&features, ARM_FEATURE_V7VE); - set_feature(&features, ARM_FEATURE_GENERIC_TIMER); + kvm_set_feature(&features, ARM_FEATURE_V7VE); + kvm_set_feature(&features, ARM_FEATURE_GENERIC_TIMER); =20 if (extract32(id_pfr0, 12, 4) =3D=3D 1) { - set_feature(&features, ARM_FEATURE_THUMB2EE); + kvm_set_feature(&features, ARM_FEATURE_THUMB2EE); } if (extract32(ahcf->isar.mvfr1, 12, 4) =3D=3D 1) { - set_feature(&features, ARM_FEATURE_NEON); + kvm_set_feature(&features, ARM_FEATURE_NEON); } =20 ahcf->features =3D features; diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index be5b31c2b0..ad33e048e4 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -447,12 +447,12 @@ void kvm_arm_pmu_set_irq(CPUState *cs, int irq) } } =20 -static inline void set_feature(uint64_t *features, int feature) +static inline void kvm_set_feature(uint64_t *features, int feature) { *features |=3D 1ULL << feature; } =20 -static inline void unset_feature(uint64_t *features, int feature) +static inline void kvm_unset_feature(uint64_t *features, int feature) { *features &=3D ~(1ULL << feature); } @@ -648,11 +648,11 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures= *ahcf) * with VFPv4+Neon; this in turn implies most of the other * feature bits. */ - set_feature(&features, ARM_FEATURE_V8); - set_feature(&features, ARM_FEATURE_NEON); - set_feature(&features, ARM_FEATURE_AARCH64); - set_feature(&features, ARM_FEATURE_PMU); - set_feature(&features, ARM_FEATURE_GENERIC_TIMER); + kvm_set_feature(&features, ARM_FEATURE_V8); + kvm_set_feature(&features, ARM_FEATURE_NEON); + kvm_set_feature(&features, ARM_FEATURE_AARCH64); + kvm_set_feature(&features, ARM_FEATURE_PMU); + kvm_set_feature(&features, ARM_FEATURE_GENERIC_TIMER); =20 ahcf->features =3D features; =20 @@ -802,7 +802,7 @@ int kvm_arch_init_vcpu(CPUState *cs) if (cpu->has_pmu) { cpu->kvm_init_features[0] |=3D 1 << KVM_ARM_VCPU_PMU_V3; } else { - unset_feature(&env->features, ARM_FEATURE_PMU); + kvm_unset_feature(&env->features, ARM_FEATURE_PMU); } if (cpu_isar_feature(aa64_sve, cpu)) { assert(kvm_arm_sve_supported(cs)); --=20 2.21.1 From nobody Fri May 3 01:46:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[83.59.163.96]) by smtp.gmail.com with ESMTPSA id b15sm498970wru.70.2020.03.16.09.06.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:06:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1584374811; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ecct8qM9CQq9wafb4H/DdqFCaIbWp3zdOza4EOqH9I4=; b=c95YFYMkfCRaVN+sBlJNYP59oneTP5J978NZXe6kzWU3HRPrA/P3U4zustSTbGdWNutv5b sgYuvGmUSLdYOiFirMRDqrhWZXDMwMco8kL9PNTjZRJHwhgf/nKflkvQUDySM3o0D3C9Qi tfIVR2tThEqfzXrE/P9RffEtaOvRnqc= X-MC-Unique: rzMu8fKaP4yUuOEYnCjtqg-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZypQ8Ym2m02m1znfiemKRznaDVP8zp+ewV5H3Kv12cs=; b=Pu+1WT24zTyLapclgmNBderSbNeukXFqL28mgw5s0v+joY3cHZ3DI02FtZSX4kJzvq 26efF8EOjXuBb06OTgyr2mlOhQSe6xb1Qw+ge1Q1ytmHsGQ06aZJHIDi96gt6DHTIcVg VEdFqZqeimvwAKn63OmA9ypfH6bkQpDhPVTaPftc5WOA48qa/Rf5lNP0iUd8WiFvlWdd gKRws6nIstMIWJQ4dMTs7/ZwcYOqOx3LUrwIl7kAIIvmDQ5j2blvOoRvc0xwSBSsfK8/ w1NFgX75cNGe0Asv/xktsHpv+dl4lHEqjNi42caS+BxpXX8KOLJk1cg+SWrauLjPdqSx 477Q== X-Gm-Message-State: ANhLgQ1jTHCD/haRe/vahwrjubZXt3RbwdTtFV16NbK1A4KTBdWzR5AP d/fzICShVXPJLVG6V8qPMKOuChEB1/n1bo4flf1Jq2qNaDu69EDnocaof1ELgsO4ukV7mIHw+Qg cmxoXpKX0OwpaJ9Y= X-Received: by 2002:a5d:6287:: with SMTP id k7mr52980wru.195.1584374808596; Mon, 16 Mar 2020 09:06:48 -0700 (PDT) X-Google-Smtp-Source: ADFU+vvIxEdXRN1Eb4UdNMtDRQaogZc63ozPayx+X/+0N08mn+FZQszGY+8INmM9VEIFVn95PP+ZPA== X-Received: by 2002:a5d:6287:: with SMTP id k7mr52955wru.195.1584374808384; Mon, 16 Mar 2020 09:06:48 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 02/19] target/arm: Make set_feature() available for other files Date: Mon, 16 Mar 2020 17:06:17 +0100 Message-Id: <20200316160634.3386-3-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 216.205.24.74 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Peter Maydell , Thomas Huth , kvm@vger.kernel.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , Eric Auger , qemu-arm@nongnu.org, Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8"; text/plain; charset="utf-8" From: Thomas Huth Move the common set_feature() and unset_feature() functions from cpu.c and cpu64.c to internals.h. Signed-off-by: Thomas Huth Reviewed-by: Richard Henderson Reviewed-by: Eric Auger Message-ID: <20190921150420.30743-2-thuth@redhat.com> [PMD: Split Thomas's patch in two: set_feature, cpu_register (later)] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/internals.h | 10 ++++++++++ target/arm/cpu.c | 10 ---------- target/arm/cpu64.c | 11 +---------- 3 files changed, 11 insertions(+), 20 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index e633aff36e..7341848e1d 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -27,6 +27,16 @@ =20 #include "hw/registerfields.h" =20 +static inline void set_feature(CPUARMState *env, int feature) +{ + env->features |=3D 1ULL << feature; +} + +static inline void unset_feature(CPUARMState *env, int feature) +{ + env->features &=3D ~(1ULL << feature); +} + /* register banks for CPU modes */ #define BANK_USRSYS 0 #define BANK_SVC 1 diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 3623ecefbd..c074364542 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -723,16 +723,6 @@ static bool arm_cpu_virtio_is_big_endian(CPUState *cs) =20 #endif =20 -static inline void set_feature(CPUARMState *env, int feature) -{ - env->features |=3D 1ULL << feature; -} - -static inline void unset_feature(CPUARMState *env, int feature) -{ - env->features &=3D ~(1ULL << feature); -} - static int print_insn_thumb1(bfd_vma pc, disassemble_info *info) { diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 62d36f9e8d..622082eae2 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -21,6 +21,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "cpu.h" +#include "internals.h" #include "qemu/module.h" #if !defined(CONFIG_USER_ONLY) #include "hw/loader.h" @@ -29,16 +30,6 @@ #include "kvm_arm.h" #include "qapi/visitor.h" =20 -static inline void set_feature(CPUARMState *env, int feature) -{ - env->features |=3D 1ULL << feature; -} - -static inline void unset_feature(CPUARMState *env, int feature) -{ - env->features &=3D ~(1ULL << feature); -} - #ifndef CONFIG_USER_ONLY static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *= ri) { --=20 2.21.1 From nobody Fri May 3 01:46:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[83.59.163.96]) by smtp.gmail.com with ESMTPSA id b12sm483914wro.66.2020.03.16.09.06.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:06:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1584374817; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dGhG21x/brBabH+9g/T50LsdW2AZT9lQa/ZmuQmYRQ4=; b=AXqD2tugI4Tsn2zG9QneSgw7jcj09LZbkgwZARX9KXNzAbPg7yPm8HdroyKmeCJ4WGbTgP yNbfFrd9+4E215dnxu0DUB2DVdicBZQxbeFEj9BVv9kjflYGHUfL0DkX/285ZokZnv7kJJ j7DFc9JcFlmqNXBAxSuL5Jwu506bmzg= X-MC-Unique: o5XWOx81NjCCbkZtuNet4Q-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=va3NBmW9VPeLqbh+njzNv2dIJgLWDq461h5IT9vGT6A=; b=B4IXl4fK0V0DkW5jI/uUDJ2f3zd6K7LsKvMUyUgTaVzcech9axy4wcqlwYlFXA28mf 8JBsBUVx4YOzO+fcrP9sJS1PJsYQv/A/msif0IT+0+Hfx5p8ZvjT7enMiDEGwYKpdmSr wC/UyFBfaW8zAvGdR761W2COYWeauLpmvi973qRU5XfZMC2s49r+wfM2OaMmqDw/iFfD gXSxRctaFMaJlfjKEZnTwLHaTxJ1brHLNWlWO/3TKgj/6fy2LhIvSmv6KUVJ9+wuHKEt avXExhnREoq5/D+PUtXUEVsYmdmNRabh001WIYPY1m0jVBFWMHkQBo5WiQFmD34wg6U7 qNTg== X-Gm-Message-State: ANhLgQ0ZCKCYnBXGsvHqI8PFSgwPGP6mqE9HC8h5lBtYjAjyrIZX1JDi Qh9+25BIIY4zcUbB7ZFeoq/oVLLPOdLmVZq9HKyCreWKLZx85LfJfYdxcFSwwItQB+lJcjwITAQ WZiSHclEP/FPKunY= X-Received: by 2002:adf:e28b:: with SMTP id v11mr59301wri.229.1584374813953; Mon, 16 Mar 2020 09:06:53 -0700 (PDT) X-Google-Smtp-Source: ADFU+vsw+1a9QL9jAQlQpFFxDwzh9qiZwTfMeMpXHBQWjLbwXCSV+9K1X0BxvHZoZJuaTV1SZQZCVA== X-Received: by 2002:adf:e28b:: with SMTP id v11mr59285wri.229.1584374813809; Mon, 16 Mar 2020 09:06:53 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 03/19] target/arm: Restrict DC-CVAP instruction to TCG accel Date: Mon, 16 Mar 2020 17:06:18 +0100 Message-Id: <20200316160634.3386-4-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 63.128.21.74 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Peter Maydell , Thomas Huth , kvm@vger.kernel.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , qemu-arm@nongnu.org, Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8"; text/plain; charset="utf-8" Under KVM the 'Data or unified Cache line Clean by VA to PoP' instruction will trap. Fixes: 0d57b4999 ("Add support for DC CVAP & DC CVADP ins") Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/helper.c | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index b61ee73d18..924deffd65 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6777,7 +6777,7 @@ static const ARMCPRegInfo rndr_reginfo[] =3D { REGINFO_SENTINEL }; =20 -#ifndef CONFIG_USER_ONLY +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) static void dccvap_writefn(CPUARMState *env, const ARMCPRegInfo *opaque, uint64_t value) { @@ -6820,9 +6820,9 @@ static const ARMCPRegInfo dcpodp_reg[] =3D { .accessfn =3D aa64_cacheop_poc_access, .writefn =3D dccvap_writefn }, REGINFO_SENTINEL }; -#endif /*CONFIG_USER_ONLY*/ +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ =20 -#endif +#endif /* TARGET_AARCH64 */ =20 static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo = *ri, bool isread) @@ -7929,7 +7929,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_rndr, cpu)) { define_arm_cp_regs(cpu, rndr_reginfo); } -#ifndef CONFIG_USER_ONLY +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) /* Data Cache clean instructions up to PoP */ if (cpu_isar_feature(aa64_dcpop, cpu)) { define_one_arm_cp_reg(cpu, dcpop_reg); @@ -7938,8 +7938,8 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, dcpodp_reg); } } -#endif /*CONFIG_USER_ONLY*/ -#endif +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ +#endif /* TARGET_AARCH64 */ =20 if (cpu_isar_feature(any_predinv, cpu)) { define_arm_cp_regs(cpu, predinv_reginfo); --=20 2.21.1 From nobody Fri May 3 01:46:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1584379583; cv=none; d=zohomail.com; s=zohoarc; b=gaD+EgEMujKNODmt/MgzUMEXlZ3pYcb6v5C0dXGkhyevL2ueXhEomGU6JTy+6oPBrNtvxwm7w1vZ0sw1kSrWprPrgo7FjFaem6Vvj3PT2oi1HIZZKJe8GWTmqM/0nxQSTlQyr9iqDLPaEjPFdEySQAdlJki7Sf4AabpKi47nAfM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1584379583; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=j2NQUGK1oGWALaGzXfEtj8AM5490glkq1or09z6B8W8=; b=ja+NKkrehjZnhr9MDFa2+82e0tdDkSX0T2laGw0RTOZQiuKjOk7W4aDy669LWKHN1qKvcTbBwAyDWhI/gMZI3BcajH8igJCAFZY8+V7fJGr4UvZnGvxHvQqjKQr4pRM3bVTJAU376rqGp1f09kKpGuPc7Q/Sh4iVPo4nX/gPgSI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1584379583752721.0947801569044; Mon, 16 Mar 2020 10:26:23 -0700 (PDT) Received: from localhost ([::1]:44074 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jDtVO-0007YP-G6 for importer@patchew.org; Mon, 16 Mar 2020 13:26:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53561) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jDsGe-0004Ap-Ag for qemu-devel@nongnu.org; Mon, 16 Mar 2020 12:07:06 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jDsGd-0008DL-1G for qemu-devel@nongnu.org; Mon, 16 Mar 2020 12:07:04 -0400 Received: from us-smtp-delivery-74.mimecast.com ([216.205.24.74]:39869) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jDsGc-0008CR-T8 for qemu-devel@nongnu.org; Mon, 16 Mar 2020 12:07:02 -0400 Received: from mail-wr1-f72.google.com (mail-wr1-f72.google.com [209.85.221.72]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-111-iZVhGtFkMxiy6byJlrL-qg-1; Mon, 16 Mar 2020 12:07:01 -0400 Received: by mail-wr1-f72.google.com with SMTP id v6so9173910wrg.22 for ; Mon, 16 Mar 2020 09:07:00 -0700 (PDT) Received: from localhost.localdomain (96.red-83-59-163.dynamicip.rima-tde.net. [83.59.163.96]) by smtp.gmail.com with ESMTPSA id y5sm166058wmi.34.2020.03.16.09.06.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:06:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1584374822; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=j2NQUGK1oGWALaGzXfEtj8AM5490glkq1or09z6B8W8=; b=Zf0DNZHiVI4eFg98LAkhJz0J9cbICvHiZpIgeiQ5fXtSrrichYZ+Lcyzg1fRnNtlk7QRdS 8Dt9TK/Sn0RkecrD1tTwHNf/rLpZybQ4Q8RSOQCJncrGDnDjIJ2FkI6Zmn9EybnAcIky65 uAPpaqoDm5uZvQGAv3vPJDY0AVn517I= X-MC-Unique: iZVhGtFkMxiy6byJlrL-qg-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=x1weIqYNF3Fo5tV0WZvC7V944GYiMwvqowZHCwqs/e8=; b=rXzFifaKD0RQWuCwEmemOHWYgq8aQOmn/tlatIwMzKTNYa4dqoDggH1OUdJJs3tquB 02g5kO1fX7E7Edid19wha/SK43PJE320k/qO/iborihh2az1yrpRccdC5orqGKqEWn8l 704/azvHKZAtTuSVnMT8jKWOwvif2+NrjCCBzsFMIHdIEkfdupF/PA578hBYDldErPIi 1Ef4VjT2ZjxnIDMi74JOfmBFr+2+YONI32hIbVFFBo3Rh0NoJ54+2Mt88W3VKdRgxCGQ zTiw1y5QMuZ2WRlS9em/HJOgw6pg7vv9qK4hkhaHEks2+ocGIeModriCaEpLBslMoyka Zjzg== X-Gm-Message-State: ANhLgQ129fPiIgcAFGnC9yat1db4yeoeLhHHCbgojgcMXaxGEFOeUxp4 dfG8+JHZpgBUvvgwud56CJCL+rc++gJ8RgpjWoFtj1ymvLuC7YzumaKAeo2nTV1LSCG66CudeJQ j0dyaljUTthotmLk= X-Received: by 2002:a1c:6385:: with SMTP id x127mr28120927wmb.141.1584374819495; Mon, 16 Mar 2020 09:06:59 -0700 (PDT) X-Google-Smtp-Source: ADFU+vsfX0n8OJNrHnrM7slMemare5ZJPKg4uT9S5KNvko7zVE1qXAD/IK5hEDswewh2HAjGFyl3Zg== X-Received: by 2002:a1c:6385:: with SMTP id x127mr28120897wmb.141.1584374819229; Mon, 16 Mar 2020 09:06:59 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 04/19] target/arm: Restric the Address Translate operations to TCG accel Date: Mon, 16 Mar 2020 17:06:19 +0100 Message-Id: <20200316160634.3386-5-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 216.205.24.74 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Peter Maydell , Thomas Huth , kvm@vger.kernel.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , qemu-arm@nongnu.org, Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8"; text/plain; charset="utf-8" Under KVM the ATS instruction will trap. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/helper.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 924deffd65..a5280c091b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3322,7 +3322,7 @@ static void par_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) } } =20 -#ifndef CONFIG_USER_ONLY +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) /* get_phys_addr() isn't present for user-mode-only targets */ =20 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3631,7 +3631,7 @@ static void ats_write64(CPUARMState *env, const ARMCP= RegInfo *ri, =20 env->cp15.par_el[1] =3D do_ats_write(env, value, access_type, mmu_idx); } -#endif +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ =20 static const ARMCPRegInfo vapa_cp_reginfo[] =3D { { .name =3D "PAR", .cp =3D 15, .crn =3D 7, .crm =3D 4, .opc1 =3D 0, .o= pc2 =3D 0, @@ -3639,7 +3639,7 @@ static const ARMCPRegInfo vapa_cp_reginfo[] =3D { .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.par_s), offsetoflow32(CPUARMState, cp15.par_ns) }, .writefn =3D par_write }, -#ifndef CONFIG_USER_ONLY +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) /* This underdecoding is safe because the reginfo is NO_RAW. */ { .name =3D "ATS", .cp =3D 15, .crn =3D 7, .crm =3D 8, .opc1 =3D 0, .o= pc2 =3D CP_ANY, .access =3D PL1_W, .accessfn =3D ats_access, @@ -4880,7 +4880,8 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 6, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, .writefn =3D tlbi_aa64_alle1is_write }, -#ifndef CONFIG_USER_ONLY + +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) /* 64 bit address translation operations */ { .name =3D "AT_S1E1R", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 8, .opc2 =3D 0, @@ -4929,7 +4930,8 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .access =3D PL1_RW, .resetvalue =3D 0, .fieldoffset =3D offsetof(CPUARMState, cp15.par_el[1]), .writefn =3D par_write }, -#endif +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ + /* TLB invalidate last level of translation table walk */ { .name =3D "TLBIMVALIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 5, .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, @@ -5536,7 +5538,7 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, .writefn =3D tlbi_aa64_vae2is_write }, -#ifndef CONFIG_USER_ONLY +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) /* Unlike the other EL2-related AT operations, these must * UNDEF from EL3 if EL2 is not implemented, which is why we * define them here rather than with the rest of the AT ops. @@ -6992,7 +6994,7 @@ static const ARMCPRegInfo vhe_reginfo[] =3D { REGINFO_SENTINEL }; =20 -#ifndef CONFIG_USER_ONLY +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) static const ARMCPRegInfo ats1e1_reginfo[] =3D { { .name =3D "AT_S1E1R", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 0, @@ -7894,14 +7896,14 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_pan, cpu)) { define_one_arm_cp_reg(cpu, &pan_reginfo); } -#ifndef CONFIG_USER_ONLY +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) if (cpu_isar_feature(aa64_ats1e1, cpu)) { define_arm_cp_regs(cpu, ats1e1_reginfo); } if (cpu_isar_feature(aa32_ats1e1, cpu)) { define_arm_cp_regs(cpu, ats1cp_reginfo); } -#endif +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ if (cpu_isar_feature(aa64_uao, cpu)) { define_one_arm_cp_reg(cpu, &uao_reginfo); } --=20 2.21.1 From nobody Fri May 3 01:46:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[83.59.163.96]) by smtp.gmail.com with ESMTPSA id 31sm14913edc.26.2020.03.16.09.07.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:07:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1584374833; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Qw8ssmMAy8/C4B18gVc/ltfDqHgs0GK3VzA8PNnWZBA=; b=NiluiQQRhy4IsibDxDeQRpgGakY/VfVxrjGRCUpxCkHthbJc/hEf+L8czJIXB+4EXQYyDK oO/u4VbYXvk/xpYn+n6/RnAz7/sutYKANSd2E+HFEi3qYMFTg3RX8LTMgXHrdTsv1yNiHl im8iRCfT2c5GVxfCiCLpDWnbYqNfPqI= X-MC-Unique: D_eaYjCJN3eWzZyezs1ITQ-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ro+HCuhG/U1g3lYErsu/yY3mato6cTL6YgdKcF/Jx28=; b=daztEUmy8pwYFdMpN5r+2Qk22MfXuwTzzArr+rVJlBeQ4W9tlOI364E2E4jb62pLz1 UqRNDpQ5AKT9YBtNfIGROSHXAuaqex0dB+59KHCAgxLaRUukLKGlKSQ6FgFJZTJt1bMT 8f0fAsduT8q6u8WQUfJGLrgI+l0GyfIq07GTfbQ+mjVqK1Sp14pBK0CkaYv+vpWokaW2 Uerhbi7rDBOnodhNkZ4bbdJvGJHU8nkQht9Wyq3AuMGQPSjuC5UvzaJvJp7d7p+LqaQ6 mwJw6wGovZ9Qr0MOxAsgWHrPYAwR6jNrMrS0szmn0JnQVOiLaTLIqJrdb2eqED3Ft3ny hd1Q== X-Gm-Message-State: ANhLgQ1KBsr2VU9Hq33SYZjkuSf8V3mgLjAHuvTV/iICqPQWur0+bY/6 +dvFiIR+/9JJNlK1gohQGmARUdeyGEfmfmAVkS/tdbDXppnVZ9ouApq1lFw/mTD0K+/L/45B/Rg 41eGhzSRP8JMgDdI= X-Received: by 2002:a17:906:33d0:: with SMTP id w16mr19391061eja.257.1584374825528; Mon, 16 Mar 2020 09:07:05 -0700 (PDT) X-Google-Smtp-Source: ADFU+vtV7veg30cCQ3j3SAt9xjtSLJOa94Pxt9UeVCoRu/dTyjd6KIDS5xdnx353O9uNorBrl6JTdw== X-Received: by 2002:a17:906:33d0:: with SMTP id w16mr19391034eja.257.1584374825290; Mon, 16 Mar 2020 09:07:05 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 05/19] target/arm: Restrict Virtualization Host Extensions instructions to TCG Date: Mon, 16 Mar 2020 17:06:20 +0100 Message-Id: <20200316160634.3386-6-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 216.205.24.74 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Peter Maydell , Thomas Huth , kvm@vger.kernel.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , qemu-arm@nongnu.org, Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8"; text/plain; charset="utf-8" Under KVM the ARMv8.1-VHE instruction will trap. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/helper.c | 22 ++++++++++++---------- 1 file changed, 12 insertions(+), 10 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index a5280c091b..ce6778283d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -2897,16 +2897,6 @@ static void gt_virt_ctl_write(CPUARMState *env, cons= t ARMCPRegInfo *ri, gt_ctl_write(env, ri, GTIMER_VIRT, value); } =20 -static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value) -{ - ARMCPU *cpu =3D env_archcpu(env); - - trace_arm_gt_cntvoff_write(value); - raw_write(env, ri, value); - gt_recalc_timer(cpu, GTIMER_VIRT); -} - static uint64_t gt_virt_redir_cval_read(CPUARMState *env, const ARMCPRegInfo *ri) { @@ -2949,6 +2939,17 @@ static void gt_virt_redir_ctl_write(CPUARMState *env= , const ARMCPRegInfo *ri, gt_ctl_write(env, ri, timeridx, value); } =20 +#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG) +static void gt_cntvoff_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + ARMCPU *cpu =3D env_archcpu(env); + + trace_arm_gt_cntvoff_write(value); + raw_write(env, ri, value); + gt_recalc_timer(cpu, GTIMER_VIRT); +} + static void gt_hyp_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) { gt_timer_reset(env, ri, GTIMER_HYP); @@ -2976,6 +2977,7 @@ static void gt_hyp_ctl_write(CPUARMState *env, const = ARMCPRegInfo *ri, { gt_ctl_write(env, ri, GTIMER_HYP, value); } +#endif /* !CONFIG_USER_ONLY && CONFIG_TCG */ =20 static void gt_sec_timer_reset(CPUARMState *env, const ARMCPRegInfo *ri) { --=20 2.21.1 From nobody Fri May 3 01:46:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1584377904; cv=none; d=zohomail.com; s=zohoarc; b=PU/RgvWWI8u/JduhlvsA57gni+RY2m1z60iT5FwWZ4njALeh/TeP3WZhKtOO2/EmWeKNE3moM9SZxVDMhHt7jhapZFjU4nwG85jvdooosypuRZ0d4GvasHrgHkC7d0Tao1OtPlMWlT0y0QWa6i41gzM5LSMXTzFHvIVP+RJ2Ru4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1584377904; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Yx+2IyWJnz1cKAJOo8cGVs9d/ga02LGh5bedgLQz1Rc=; b=I5US1H+2v2RsJ4NMgBTbm7Crp5/vNoVIGIuMN4shvAr7ntAeALFJe9h2loNuAWZcBYhtWh1b1o4/KDWcF7KpHxXdu2w1l1EzR8Usa8wlqw1H1oKZ/Ag4zhwcdhmz1d4yt1gUQ3Ew61ZOycTsk75O/tW0juhhfNFWhBCsk/RXEfA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 158437790401391.38951865751551; Mon, 16 Mar 2020 09:58:24 -0700 (PDT) Received: from localhost ([::1]:42930 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jDt4I-0007ny-U7 for importer@patchew.org; Mon, 16 Mar 2020 12:58:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54012) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jDsGp-0004Gm-RV for qemu-devel@nongnu.org; Mon, 16 Mar 2020 12:07:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jDsGo-00012G-PZ for qemu-devel@nongnu.org; Mon, 16 Mar 2020 12:07:15 -0400 Received: from us-smtp-delivery-74.mimecast.com ([63.128.21.74]:46771) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jDsGo-0000y2-Kc for qemu-devel@nongnu.org; Mon, 16 Mar 2020 12:07:14 -0400 Received: from mail-wr1-f70.google.com (mail-wr1-f70.google.com [209.85.221.70]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-38-imvQ3ASVMAKZBsYHPJjGrw-1; Mon, 16 Mar 2020 12:07:12 -0400 Received: by mail-wr1-f70.google.com with SMTP id p2so6715001wrw.8 for ; Mon, 16 Mar 2020 09:07:12 -0700 (PDT) Received: from localhost.localdomain (96.red-83-59-163.dynamicip.rima-tde.net. [83.59.163.96]) by smtp.gmail.com with ESMTPSA id p8sm552349wrw.19.2020.03.16.09.07.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:07:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1584374834; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Yx+2IyWJnz1cKAJOo8cGVs9d/ga02LGh5bedgLQz1Rc=; b=fCFe26G5ukrvsFodtoKddSJi0ijLxfDTdthG7C3jXHgasHc+jyhk8csgPb7lCoyA6yqt+h wLjNmDx1/IzYD+j2pCVFOOfKv4TOt0DxIOtdmrUDIuV2rmgXb8iYcwXrqdx82S7Ukoq/BH cIFqPiTbUIIFWq6khNefda0ihGx8Ddk= X-MC-Unique: imvQ3ASVMAKZBsYHPJjGrw-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yxNTHu0Y9BXexKmUFsNlCCh8LSzlOCW9yO82fm58I4s=; b=Gpn1fIzmNKu5EQPn2A2OR4KPACCU1fC+uV+n86BDoOzcyuFjR4UCxHnOxLxYThBQtC TVxj4keYWLWFraCriz8nGSik/mlz2kxvg/1ZEahoIavpYwkuxP+oVR4rtIhaOK27JF4A qm/SV85zAWL7n8UgX30jwkyGZG+CMwMICUpfYQrTXH0q56o6m9kSablV+fKRre2lUecS qsb0WvSTJFnG7+3tLU9mHB+GErivLep61Svr8ETubMOFowaWVTcckB8nLbWIuWwuWQZx pYCvu+UAAw0MfOrdFfe7Ayh6wsaJ7Uuli8YlQbTjCdKsVnCO/3BIGzUV1rOv7qT007ie l5Gg== X-Gm-Message-State: ANhLgQ3eCyhV/xYFgrk6cuAsQJFYi8OlXaRpV+E5IqO2OF8aCOG+Zqq4 d/P85H2L9gHFgpTn2oFrvOzwxxXmrlt3poQJ/A44YmPEzzeUyID2HIL1qCRsLZaVjAhqa8ba3X6 /03oRtgQ15GR7xo4= X-Received: by 2002:a7b:c5cd:: with SMTP id n13mr28456591wmk.172.1584374830945; Mon, 16 Mar 2020 09:07:10 -0700 (PDT) X-Google-Smtp-Source: ADFU+vs7IJfPb/lnQB6VsT1fXs4khiy3iYFUFjrhDCacWI//Wr03P/OMBnlYg0XoQf+8TAXToOGQKQ== X-Received: by 2002:a7b:c5cd:: with SMTP id n13mr28456569wmk.172.1584374830787; Mon, 16 Mar 2020 09:07:10 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 06/19] target/arm: Move Makefile variable restricted to CONFIG_TCG Date: Mon, 16 Mar 2020 17:06:21 +0100 Message-Id: <20200316160634.3386-7-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 63.128.21.74 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Peter Maydell , Thomas Huth , kvm@vger.kernel.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , qemu-arm@nongnu.org, Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8"; text/plain; charset="utf-8" Simple code movement which simplifies next commits. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/Makefile.objs | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index cf26c16f5f..0c6f8c248d 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -1,4 +1,3 @@ -obj-$(CONFIG_TCG) +=3D arm-semi.o obj-y +=3D helper.o vfp_helper.o obj-y +=3D cpu.o gdbstub.o obj-$(TARGET_AARCH64) +=3D cpu64.o gdbstub64.o @@ -56,6 +55,12 @@ target/arm/translate.o: target/arm/decode-a32-uncond.inc= .c target/arm/translate.o: target/arm/decode-t32.inc.c target/arm/translate.o: target/arm/decode-t16.inc.c =20 +ifeq ($(CONFIG_TCG),y) + +obj-y +=3D arm-semi.o + +endif # CONFIG_TCG + obj-y +=3D tlb_helper.o debug_helper.o obj-y +=3D translate.o op_helper.o obj-y +=3D crypto_helper.o --=20 2.21.1 From nobody Fri May 3 01:46:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1584381027; cv=none; d=zohomail.com; s=zohoarc; b=TPYHvY3JyV9hH5H/HDEgd5+lhRHRgqL53Rwl1IgmMf7t2Tv3NJGb3EfHwPhNcJvrq1jAX+FafmF/FXVW/onNCvFZnCFHvMwQVotspbf5oS+N44uSJ31L/1X5GuMZu6AFdyusLciI+M8A/tDFuXu8957pY4/2lvxK1wrGBGPwKAo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1584381027; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bL2VrSLFEXUirQF2ArCcrNoQCZwZW3hELnT927BBnbQ=; b=CR7m/Q4UBK29K/hH5bBQETz/+WXQQnWz5Wiixqf9zHUSnaDlR/MvIUW4JaDXLt5ivc77LhkkOvNON3oj5xtQeVj4HVd1Gh00wM27mDAu/DEKJYp9e6PLxps1/6ARwLal8M+Dnwg8y5oadB3i/bC6VtJb16lkIt9Hb6ctFaNpsNM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1584381027773700.411564320563; Mon, 16 Mar 2020 10:50:27 -0700 (PDT) Received: from localhost ([::1]:44834 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jDtsg-00009f-C1 for importer@patchew.org; Mon, 16 Mar 2020 13:50:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54250) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jDsH2-0004Lt-Rq for qemu-devel@nongnu.org; Mon, 16 Mar 2020 12:07:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jDsH1-0001XT-Lh for qemu-devel@nongnu.org; Mon, 16 Mar 2020 12:07:28 -0400 Received: from us-smtp-delivery-74.mimecast.com ([63.128.21.74]:35756) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jDsH1-0001Tv-HT for qemu-devel@nongnu.org; Mon, 16 Mar 2020 12:07:27 -0400 Received: from mail-wr1-f70.google.com (mail-wr1-f70.google.com [209.85.221.70]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-146-1e58OSg2OVOeFAojKjp9QA-1; Mon, 16 Mar 2020 12:07:19 -0400 Received: by mail-wr1-f70.google.com with SMTP id p2so6715134wrw.8 for ; Mon, 16 Mar 2020 09:07:18 -0700 (PDT) Received: from localhost.localdomain (96.red-83-59-163.dynamicip.rima-tde.net. [83.59.163.96]) by smtp.gmail.com with ESMTPSA id y7sm22973551wmd.1.2020.03.16.09.07.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:07:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1584374840; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=bL2VrSLFEXUirQF2ArCcrNoQCZwZW3hELnT927BBnbQ=; b=NOYwMHWvsc5J8eSRREa8Ikv8XGatGP3EXLFJlOiqP1Udf4rJe45WIJ0jxd7d+XXUh+JXiJ XxxvhdSRFaUX/o3SHOt5l+kmfM0NZlm/7Hg+xZzE6l/pQSZHDgb2NcGu2cNdK+1C6cALt2 u6cqt+kPE3xF/L7GHfk2aaS7DUQf66Q= X-MC-Unique: 1e58OSg2OVOeFAojKjp9QA-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=r1sJ64QkUjojSCH6EGfhYUMESaCKLhSIpdoia+8OdJA=; b=iEyo8mcJuftS/OK+jGxs2bZJ/YTiI9w9LaN6a0z4EHpazgzboT/8I1EeqcHvq3GjDH niV0u2mYTFCDzpoho0+iWfjBNJfyKVBo5CNySfGhR3lL5vYRgyAcXbbfvNpX/kP04T7C KfRrcwPcsWaiJzME8RiK2eyILFIuYuGYOVEIfB9ZqGmz60OFKTVZOeJpi/2f7DxWwj4/ SsHZkDVo9V4mVRDc5YJMvvm2cvdqA3kDnAm6/0WGyz6/Eh8RdnOA6St+BG8qbD4TP53A zqCRb+OdyAvtZ8AcCHsRxNVI37kN2lhy4B2/AJdGDqnBLiWh4h0ArvxCjtQgFJYd9VPQ lRVg== X-Gm-Message-State: ANhLgQ2Tu7gDh/fVc9/zf3psV1IxT0K4F6AEz4UcagKhzdvLbzp9gUoQ NBXpIdjQ7jefip83KqmEKj5SaheeQLgUrcPQPD6X559+fHeyuhwJFv5KzwKzaR8YEDFdUln4G0W k3m6I+OhX7wJDr1c= X-Received: by 2002:a05:6000:d0:: with SMTP id q16mr77281wrx.71.1584374836483; Mon, 16 Mar 2020 09:07:16 -0700 (PDT) X-Google-Smtp-Source: ADFU+vuudPESzx7lkwiv+yf4OA/xliD4IQtL8C5kEgXeePSGNU/JOytk/Z7I5CpK3n1RCITbf/5TOg== X-Received: by 2002:a05:6000:d0:: with SMTP id q16mr77257wrx.71.1584374836307; Mon, 16 Mar 2020 09:07:16 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 07/19] target/arm: Make cpu_register() available for other files Date: Mon, 16 Mar 2020 17:06:22 +0100 Message-Id: <20200316160634.3386-8-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 63.128.21.74 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Peter Maydell , Thomas Huth , kvm@vger.kernel.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , Eric Auger , qemu-arm@nongnu.org, Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8"; text/plain; charset="utf-8" From: Thomas Huth Make cpu_register() (renamed to arm_cpu_register()) available from internals.h so we can register CPUs also from other files in the future. Signed-off-by: Thomas Huth Reviewed-by: Richard Henderson Reviewed-by: Eric Auger Message-ID: <20190921150420.30743-2-thuth@redhat.com> [PMD: Split Thomas's patch in two: set_feature (earlier), cpu_register] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/cpu-qom.h | 9 ++++++++- target/arm/cpu.c | 10 ++-------- target/arm/cpu64.c | 8 +------- 3 files changed, 11 insertions(+), 16 deletions(-) diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index 3a9d31ea9d..29c5e2f2c9 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -35,7 +35,14 @@ struct arm_boot_info; =20 #define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU =20 -typedef struct ARMCPUInfo ARMCPUInfo; +typedef struct ARMCPUInfo { + const char *name; + void (*initfn)(Object *obj); + void (*class_init)(ObjectClass *oc, void *data); +} ARMCPUInfo; + +void arm_cpu_register(const ARMCPUInfo *info); +void aarch64_cpu_register(const ARMCPUInfo *info); =20 /** * ARMCPUClass: diff --git a/target/arm/cpu.c b/target/arm/cpu.c index c074364542..d2813eb81a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2698,12 +2698,6 @@ static void arm_max_initfn(Object *obj) =20 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */ =20 -struct ARMCPUInfo { - const char *name; - void (*initfn)(Object *obj); - void (*class_init)(ObjectClass *oc, void *data); -}; - static const ARMCPUInfo arm_cpus[] =3D { #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) { .name =3D "arm926", .initfn =3D arm926_initfn }, @@ -2869,7 +2863,7 @@ static void cpu_register_class_init(ObjectClass *oc, = void *data) acc->info =3D data; } =20 -static void cpu_register(const ARMCPUInfo *info) +void arm_cpu_register(const ARMCPUInfo *info) { TypeInfo type_info =3D { .parent =3D TYPE_ARM_CPU, @@ -2910,7 +2904,7 @@ static void arm_cpu_register_types(void) type_register_static(&idau_interface_type_info); =20 while (info->name) { - cpu_register(info); + arm_cpu_register(info); info++; } =20 diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 622082eae2..e89388378b 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -728,12 +728,6 @@ static void aarch64_max_initfn(Object *obj) cpu_max_set_sve_max_vq, NULL, NULL, &error_fatal); } =20 -struct ARMCPUInfo { - const char *name; - void (*initfn)(Object *obj); - void (*class_init)(ObjectClass *oc, void *data); -}; - static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a57", .initfn =3D aarch64_a57_initfn }, { .name =3D "cortex-a53", .initfn =3D aarch64_a53_initfn }, @@ -816,7 +810,7 @@ static void cpu_register_class_init(ObjectClass *oc, vo= id *data) acc->info =3D data; } =20 -static void aarch64_cpu_register(const ARMCPUInfo *info) +void aarch64_cpu_register(const ARMCPUInfo *info) { TypeInfo type_info =3D { .parent =3D TYPE_AARCH64_CPU, --=20 2.21.1 From nobody Fri May 3 01:46:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[83.59.163.96]) by smtp.gmail.com with ESMTPSA id u204sm185104wmg.40.2020.03.16.09.07.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:07:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1584374844; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=5MseejxD/7No0UFmjuvYKtOzc/OHo7duv42MWn+BaII=; b=dIFqx6bcN6gIN9lCWEwEEgHDgZr36/wLikByEnPkQYHARlskNueM2llvlUByMmigSaC035 LOlULgAdH44dtNYrzJueQyRiZmD9s+Y10JCgKusSol8OhkVJuOHdyLy/DQjqO41mJbyO4W pea9f1VZAAFIboxKyVMlndAHVY1eOPs= X-MC-Unique: aK5BX1ZhN9GlviFBOtor6Q-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CXjQwOZg5TRrzV2gPeofWVxsNWA85AadaVJBm5vW278=; b=jSAUUcU6nD/y2K1BDwAL22W+brDUlGIj8Juix1WZ00rfq1X5nw+YSyVLwCpyZ4Ch1F 116Vky7Z7gzIyNj1JPwfuj32Saof5NaoCbhArN9snC95GUr+qEasnu/ee66fPo8dYtbV BeSA2EJiJKFCG2yFESqPsVHe9RWU8HFV9frvk9tsvdJfKFeeyGePC1LGl6yaP8Rb9fos GUldH3NJXyyBMVTvap8t3jWMoBcTTPJXwjLPjw8UObx/hCwvXbWkwmaGVrXDNMjEACVo +hTn12KvKqip7t1hGbLw5vE/j91yW+d3MuS00DxQg6HEBn2GnCt1yxW/D/B1qzU4p2xn qFeA== X-Gm-Message-State: ANhLgQ1uzdaegp17rA3atQd6CjuajS1Ycjh/ZL0V3H24bzfAaOqX06xt FK9fMqMI8vpAU/ZrpvSYwUT089b7vDqB+GQdOAX76a+Zz4qngA4ZnUSZEfPI/hT+oR186BBPJMn 3DPp9Rmlz0KhZN9o= X-Received: by 2002:adf:dd8f:: with SMTP id x15mr63154wrl.201.1584374841785; Mon, 16 Mar 2020 09:07:21 -0700 (PDT) X-Google-Smtp-Source: ADFU+vsxe/KqUgpqRGockZFKDs2m6WInFJ38H8FHOWfbUrTbCQq4cCk2UoU+Cb7vY3P51wmSj99eAw== X-Received: by 2002:adf:dd8f:: with SMTP id x15mr63130wrl.201.1584374841621; Mon, 16 Mar 2020 09:07:21 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 08/19] target/arm: Add semihosting stub to allow building without TCG Date: Mon, 16 Mar 2020 17:06:23 +0100 Message-Id: <20200316160634.3386-9-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 63.128.21.74 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Peter Maydell , Thomas Huth , kvm@vger.kernel.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , qemu-arm@nongnu.org, Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8"; text/plain; charset="utf-8" Semihosting requires TCG. When configured with --disable-tcg, the build fails because the 'do_arm_semihosting' is missing. Instead of adding more few more #ifdeffery to the helper code, add a stub. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/arm-semi-stub.c | 13 +++++++++++++ target/arm/Makefile.objs | 3 ++- 2 files changed, 15 insertions(+), 1 deletion(-) create mode 100644 target/arm/arm-semi-stub.c diff --git a/target/arm/arm-semi-stub.c b/target/arm/arm-semi-stub.c new file mode 100644 index 0000000000..47d042f942 --- /dev/null +++ b/target/arm/arm-semi-stub.c @@ -0,0 +1,13 @@ +/* + * Arm "Angel" semihosting syscalls stubs + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/osdep.h" +#include "cpu.h" +#include "hw/semihosting/semihost.h" + +target_ulong do_arm_semihosting(CPUARMState *env) +{ + abort(); +} diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 0c6f8c248d..fa278bb4c1 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -57,7 +57,8 @@ target/arm/translate.o: target/arm/decode-t16.inc.c =20 ifeq ($(CONFIG_TCG),y) =20 -obj-y +=3D arm-semi.o +obj-$(CONFIG_SEMIHOSTING) +=3D arm-semi.o +obj-$(call lnot,$(CONFIG_SEMIHOSTING)) +=3D arm-semi-stub.o =20 endif # CONFIG_TCG =20 --=20 2.21.1 From nobody Fri May 3 01:46:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1584379808; cv=none; d=zohomail.com; s=zohoarc; b=cp5QpA+luFqYzVbZp4RyA94apUkHa9cYEhPE1BKmTv77XO7rYHa6GDWA8afwiUSNSaabK6eslqF5TFKaCVkKqcOYrE9FO5lWUzaZwI3G69fYKp67rRmc85ZmtDTRXrlxp4AVbZmYtVBVSDlCSfcnqaJYFnsl8NDMMidAAsFICVk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1584379808; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vKQK/gk4+Rfzeay1FIA++WnEXh1sOGPFugrslQ2WqSM=; b=ieZVKcQ27D9IYL2U/EhVe0IUy4ic7n/S2eDq+CZ8s9Rgf6KqS/mrSPkri6xgRfU9+lJGY9CVsY/4gcEhwMcgayIVSRE4ZFD6YSJHkNUY8+k1F60es7FLBronOGuxpDHvKiZF1vUASoeCVADaLwdJGbqOo7gBxTYbgW1eJBHMd6s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1584379808302700.9666252129158; Mon, 16 Mar 2020 10:30:08 -0700 (PDT) Received: from localhost ([::1]:44302 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jDtZ0-0005de-Fc for importer@patchew.org; Mon, 16 Mar 2020 13:30:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54464) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jDsH7-0004PO-Qs for qemu-devel@nongnu.org; Mon, 16 Mar 2020 12:07:35 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jDsH6-00025f-MM for qemu-devel@nongnu.org; Mon, 16 Mar 2020 12:07:33 -0400 Received: from us-smtp-delivery-74.mimecast.com ([216.205.24.74]:57715) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jDsH6-00022r-HH for qemu-devel@nongnu.org; Mon, 16 Mar 2020 12:07:32 -0400 Received: from mail-wr1-f72.google.com (mail-wr1-f72.google.com [209.85.221.72]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-185-E1xAdKtEOoiRFvGSgVZy_g-1; Mon, 16 Mar 2020 12:07:28 -0400 Received: by mail-wr1-f72.google.com with SMTP id l16so8540364wrr.6 for ; Mon, 16 Mar 2020 09:07:28 -0700 (PDT) Received: from localhost.localdomain (96.red-83-59-163.dynamicip.rima-tde.net. [83.59.163.96]) by smtp.gmail.com with ESMTPSA id k5sm221948wmj.18.2020.03.16.09.07.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:07:26 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1584374852; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=vKQK/gk4+Rfzeay1FIA++WnEXh1sOGPFugrslQ2WqSM=; b=Au1jdn9OdAoljJHMLjmhRtQUBMryFuISLxuJr6JYVwhQ8SGcb4Lgbf8h7d+5D70iEqoYNJ oRiXz672D2fmuHXPIYkMMGfxsu64yxVOom2bLs4LW5b8WzKGeNjXXtWFp0WuPq13TW+zik 1fEERVOlANiw/pdCywY4ngNmGipFR5U= X-MC-Unique: E1xAdKtEOoiRFvGSgVZy_g-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZbHLr8MN7Y181YkXNU9q35GGyibM63M9cMs0mFzNFC4=; b=RP6/lUU4ttC2PWYu8FSfGYO5Xo9P44jNd/eqeL5iM0S9Kg17rgm+b/Lthz2j7INaiI ruY2rlkj2+ufWtXCZO+QB3TeSbQ8vvRgX7s9SmFNzINTsuf9MEHK3CGq6/FigbspW5Rm CT7ihxBpAUM4PLjPYKiBwmkrCLmuK36tTNNfOoonhAuEoVsA7TTxa1HfpjhMUxMtJgIO 8nnmtHIPc0oDErGQEsYtspAf0wQi4euFjI3fDrouigSZYvn5hnk00/UPAH4IVvGFB/XR 9aiymxNTPGUuGwWxT9o92BfMeV7OgAclpFKyCnmTtqCnxs1I50o6623zE5ASXaVWUGW2 ZPbw== X-Gm-Message-State: ANhLgQ0IBQQsBk1lQjC7XCPUlZOU6p6w/JwAjoLCWLKKLmxWWbfSAvMr o5RwwXqMBp3DAwJiyPCAGbRDP9BpEvC4oPW/icTVeAXeHreQNAKmNDrse7ZTx1hRnt0tNPB/W3L +l3+EBHtJepFcTIQ= X-Received: by 2002:a1c:de82:: with SMTP id v124mr27908592wmg.70.1584374847192; Mon, 16 Mar 2020 09:07:27 -0700 (PDT) X-Google-Smtp-Source: ADFU+vvmhZSbs8NzLKXqUjgdCfW3w9WctLHdMyXVqEBO9jZ0UEFAr0Le+jcnqG4RZo4FMyA5CMMs0Q== X-Received: by 2002:a1c:de82:: with SMTP id v124mr27908565wmg.70.1584374846997; Mon, 16 Mar 2020 09:07:26 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 09/19] target/arm: Move ARM_V7M Kconfig from hw/ to target/ Date: Mon, 16 Mar 2020 17:06:24 +0100 Message-Id: <20200316160634.3386-10-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 216.205.24.74 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Peter Maydell , Thomas Huth , kvm@vger.kernel.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , qemu-arm@nongnu.org, Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8"; text/plain; charset="utf-8" ARM_V7M is a concept tied to the architecture. Move it to the target/arm/ directory to keep the hardware/architecture separation clearer. Signed-off-by: Philippe Mathieu-Daud=C3=A9 Acked-by: Richard Henderson --- hw/arm/Kconfig | 3 --- target/Kconfig | 2 +- target/arm/Kconfig | 2 ++ 3 files changed, 3 insertions(+), 4 deletions(-) create mode 100644 target/arm/Kconfig diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index e5a876c8d1..e3d7e7694a 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -285,9 +285,6 @@ config ZYNQ select XILINX_SPIPS select ZYNQ_DEVCFG =20 -config ARM_V7M - bool - config ALLWINNER_A10 bool select AHCI diff --git a/target/Kconfig b/target/Kconfig index 8b13789179..130d0c7a85 100644 --- a/target/Kconfig +++ b/target/Kconfig @@ -1 +1 @@ - +source arm/Kconfig diff --git a/target/arm/Kconfig b/target/arm/Kconfig new file mode 100644 index 0000000000..e68c71a6ff --- /dev/null +++ b/target/arm/Kconfig @@ -0,0 +1,2 @@ +config ARM_V7M + bool --=20 2.21.1 From nobody Fri May 3 01:46:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1584380143; cv=none; d=zohomail.com; s=zohoarc; b=ToDMBKPXUrPMfj2yCTzjwxGXSJ40HHY7k/30aCWafDY9diSEy74waO4TaX5Xw4Y4bgIzw7bugxcWf6Wo+se1TLsSI4HXyzqQM4PsCsZTDxCcJbCiP7oa/p1s6iL81zjU/puHZ+RtCrfI2CQ4alapoyrx8SBCVKxBWurZrxFvW14= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1584380143; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=dh0QaW36S0ly7XnA717+46Hg5QZjkgBSBDC6x6/CnNM=; b=V3KQxsbCcrQ1NjZ83F8QlcJblp1YVOKTTs6NjzsEr+QbcFGOzsxUmkZPWYYr9H8S1QEL7yPkFk/3yz73hxO2PcFcvTNoiWGxsmXQnHpM+dOX5f60qiBlKZLUSTKaGJxP8InKlgd5ED/p9BcvceOiTfxhdL/KZcyMM7GnNkKELy4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1584380143027231.98483459448096; Mon, 16 Mar 2020 10:35:43 -0700 (PDT) Received: from localhost ([::1]:44420 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jDteQ-0006WN-1V for importer@patchew.org; Mon, 16 Mar 2020 13:35:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54814) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jDsHF-0004ST-Tc for qemu-devel@nongnu.org; Mon, 16 Mar 2020 12:07:44 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jDsHE-0002yk-EJ for qemu-devel@nongnu.org; Mon, 16 Mar 2020 12:07:41 -0400 Received: from us-smtp-delivery-74.mimecast.com ([63.128.21.74]:48196) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jDsHE-0002wL-8t for qemu-devel@nongnu.org; Mon, 16 Mar 2020 12:07:40 -0400 Received: from mail-wr1-f72.google.com (mail-wr1-f72.google.com [209.85.221.72]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-444-3ZXJcEZrNi2aLV9VfC1icQ-1; Mon, 16 Mar 2020 12:07:37 -0400 Received: by mail-wr1-f72.google.com with SMTP id f13so3057397wro.23 for ; Mon, 16 Mar 2020 09:07:37 -0700 (PDT) Received: from localhost.localdomain (96.red-83-59-163.dynamicip.rima-tde.net. [83.59.163.96]) by smtp.gmail.com with ESMTPSA id 127sm68345wmd.38.2020.03.16.09.07.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:07:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1584374859; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=dh0QaW36S0ly7XnA717+46Hg5QZjkgBSBDC6x6/CnNM=; b=XLvEtcP3djM/EwRFZXMnkMCBA9PLnfwK8oZfHsM1vLY4XIAp8bBDviek9d58jBKXUK2WLn G4kidsEC7erYNb24rLz8CJyyad5uglewPMqcc+vkoSYFipDRVByffg2aVlzj8YjHj8jl8O ffbtyG/b2Ayr1zdZf7J4Ehzy4jCNIB0= X-MC-Unique: 3ZXJcEZrNi2aLV9VfC1icQ-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3HJ4BPrTTJoaZ0DIQ+Bm5OwC5QHXxR7lFDDNNHr42oA=; b=HGp0jtzujKECIiF7zQDTGXOenwiwnUA1MjKFl+xWFiI9XA+bQ2iXQRP5uufE5L4VV6 yjYKJSVlJaOUtHAOdjCMckKKpHMe120gD4lFMopbvakr/UVpG/Lyq9jkBcq/NjfGILNN iH/bAU6cCIZ/o/m3axuUVwUfbx/3vqCGc6bj3pn+LeRjKK+XCMmNuSatLgrJ8PyBuWxw qv4DMzdz2geUCKOFP6erAy51JhFFxFtQ7GqYWrONnT8wyGEQw9+M3dkPzOT7wUreGlOh T8tRihsLy30E6Tj3sDb5bnxHwqbDZEOGE5Q5ATGV4gAvPZLublORHVKscpvwgKnD3XSs bY2Q== X-Gm-Message-State: ANhLgQ2ztolXtQLz742NIiER94Lsc07lzR2pGWpI+VpsGuDVOzLS84UF ISwih4XtwUQ+U86B0BWEDsIDckPjNFnSMxMQvAnWAt2p3kcwvyOBz9nvm5cvFA2OC8aUbJCGQly Q5lNpX7G1cLZA4Ok= X-Received: by 2002:a5d:69c1:: with SMTP id s1mr47288wrw.351.1584374852711; Mon, 16 Mar 2020 09:07:32 -0700 (PDT) X-Google-Smtp-Source: ADFU+vtrKaxBzOd8Im5SmvT1u80g+l61wwRhiOvBIE54mUu/WaIr9u73VUZDQPx9shnTaY32+aclQQ== X-Received: by 2002:a5d:69c1:: with SMTP id s1mr47263wrw.351.1584374852435; Mon, 16 Mar 2020 09:07:32 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 10/19] target/arm: Restrict ARMv4 cpus to TCG accel Date: Mon, 16 Mar 2020 17:06:25 +0100 Message-Id: <20200316160634.3386-11-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 63.128.21.74 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Peter Maydell , Thomas Huth , kvm@vger.kernel.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , qemu-arm@nongnu.org, Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8"; text/plain; charset="utf-8" KVM requires a cpu based on (at least) the ARMv7 architecture. Only enable the following ARMv4 CPUs when TCG is available: - StrongARM (SA1100/1110) - OMAP1510 (TI925T) Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- default-configs/arm-softmmu.mak | 2 - target/arm/cpu.c | 33 ----------------- target/arm/cpu_v4.c | 65 +++++++++++++++++++++++++++++++++ hw/arm/Kconfig | 2 + target/arm/Kconfig | 4 ++ target/arm/Makefile.objs | 2 + 6 files changed, 73 insertions(+), 35 deletions(-) create mode 100644 target/arm/cpu_v4.c diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.= mak index 8b89d8c4c0..0652396296 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -17,8 +17,6 @@ CONFIG_INTEGRATOR=3Dy CONFIG_FSL_IMX31=3Dy CONFIG_MUSICPAL=3Dy CONFIG_MUSCA=3Dy -CONFIG_CHEETAH=3Dy -CONFIG_SX1=3Dy CONFIG_NSERIES=3Dy CONFIG_STELLARIS=3Dy CONFIG_REALVIEW=3Dy diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d2813eb81a..b08b6933be 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2459,36 +2459,6 @@ static void cortex_a15_initfn(Object *obj) define_arm_cp_regs(cpu, cortexa15_cp_reginfo); } =20 -static void ti925t_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - set_feature(&cpu->env, ARM_FEATURE_V4T); - set_feature(&cpu->env, ARM_FEATURE_OMAPCP); - cpu->midr =3D ARM_CPUID_TI925T; - cpu->ctr =3D 0x5109149; - cpu->reset_sctlr =3D 0x00000070; -} - -static void sa1100_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "intel,sa1100"; - set_feature(&cpu->env, ARM_FEATURE_STRONGARM); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - cpu->midr =3D 0x4401A11B; - cpu->reset_sctlr =3D 0x00000070; -} - -static void sa1110_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - set_feature(&cpu->env, ARM_FEATURE_STRONGARM); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - cpu->midr =3D 0x6901B119; - cpu->reset_sctlr =3D 0x00000070; -} - static void pxa250_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -2727,9 +2697,6 @@ static const ARMCPUInfo arm_cpus[] =3D { { .name =3D "cortex-a8", .initfn =3D cortex_a8_initfn }, { .name =3D "cortex-a9", .initfn =3D cortex_a9_initfn }, { .name =3D "cortex-a15", .initfn =3D cortex_a15_initfn }, - { .name =3D "ti925t", .initfn =3D ti925t_initfn }, - { .name =3D "sa1100", .initfn =3D sa1100_initfn }, - { .name =3D "sa1110", .initfn =3D sa1110_initfn }, { .name =3D "pxa250", .initfn =3D pxa250_initfn }, { .name =3D "pxa255", .initfn =3D pxa255_initfn }, { .name =3D "pxa260", .initfn =3D pxa260_initfn }, diff --git a/target/arm/cpu_v4.c b/target/arm/cpu_v4.c new file mode 100644 index 0000000000..1de00a03ee --- /dev/null +++ b/target/arm/cpu_v4.c @@ -0,0 +1,65 @@ +/* + * ARM generic helpers. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" + +/* CPU models. These are not needed for the AArch64 linux-user build. */ +#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) + +static void ti925t_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V4T); + set_feature(&cpu->env, ARM_FEATURE_OMAPCP); + cpu->midr =3D ARM_CPUID_TI925T; + cpu->ctr =3D 0x5109149; + cpu->reset_sctlr =3D 0x00000070; +} + +static void sa1100_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "intel,sa1100"; + set_feature(&cpu->env, ARM_FEATURE_STRONGARM); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + cpu->midr =3D 0x4401A11B; + cpu->reset_sctlr =3D 0x00000070; +} + +static void sa1110_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_STRONGARM); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + cpu->midr =3D 0x6901B119; + cpu->reset_sctlr =3D 0x00000070; +} + +static const ARMCPUInfo arm_v4_cpus[] =3D { + { .name =3D "ti925t", .initfn =3D ti925t_initfn }, + { .name =3D "sa1100", .initfn =3D sa1100_initfn }, + { .name =3D "sa1110", .initfn =3D sa1110_initfn }, + { .name =3D NULL } +}; + +static void arm_v4_cpu_register_types(void) +{ + const ARMCPUInfo *info =3D arm_v4_cpus; + + while (info->name) { + arm_cpu_register(info); + info++; + } +} + +type_init(arm_v4_cpu_register_types) + +#endif diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index e3d7e7694a..7fc0cff776 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -28,6 +28,7 @@ config ARM_VIRT =20 config CHEETAH bool + select ARM_V4 select OMAP select TSC210X =20 @@ -242,6 +243,7 @@ config COLLIE =20 config SX1 bool + select ARM_V4 select OMAP =20 config VERSATILE diff --git a/target/arm/Kconfig b/target/arm/Kconfig index e68c71a6ff..0d496d318a 100644 --- a/target/arm/Kconfig +++ b/target/arm/Kconfig @@ -1,2 +1,6 @@ +config ARM_V4 + depends on TCG + bool + config ARM_V7M bool diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index fa278bb4c1..bc0f63ebbc 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -68,6 +68,8 @@ obj-y +=3D crypto_helper.o obj-y +=3D iwmmxt_helper.o vec_helper.o neon_helper.o obj-y +=3D m_helper.o =20 +obj-$(CONFIG_ARM_V4) +=3D cpu_v4.o + obj-$(CONFIG_SOFTMMU) +=3D psci.o =20 obj-$(TARGET_AARCH64) +=3D translate-a64.o helper-a64.o --=20 2.21.1 From nobody Fri May 3 01:46:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[83.59.163.96]) by smtp.gmail.com with ESMTPSA id w204sm241548wma.1.2020.03.16.09.07.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:07:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1584374862; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=E6imTlgemnO4l8fO3+EjkoMb/LcYFsVXBVbYJMCxv6M=; b=JrzWGe6kAuWn3DbWvMkrComqzbM6EKxXhl3Dl7TenCr1GFADXPMFEtI/YD5KHRDY3ukHq6 8edHrnXs7d9En5dhGxcddt+esn7nYCS9GwAJ0+0ikswRW7/CQSHudh9k+MfFukS/+bzG1T 7Yz6LZtCQZJfwOF79KN5K2B5B2CYSR4= X-MC-Unique: iDQR470NOsSB0Pey8mx7NQ-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UM67HGSwESPGxRuh3RiuHLraRXWOuFjnUtJ3FzN+nLQ=; b=ImcAXNTwyaSF63u4czkMkU0DT/BQ2nrj465lMuvkxndPNjUCakWcuhlQEU7EtybfkQ OhzjGj2Upq1pDPaFQMUSBtamAdLcgJ0YtEuna/rHO1x1nHXfU5Icbp70mx6VwJ9fa8vg rmzSsTF6ydnnADL2AfdGoxZFMD1iyvqUDMIcQZhELL8r0uMJKh358X03vqKAl3oiLuVU eIGgIHjH+WQuebmWZxZtiOooyX15Qov0QfbhomT7xo1rpSmM1hZeXFCJtTkUFqGP+rXO 6HVBk7Bap3Fdg4MwoHrxpkbl6NCd9fY+nbLvCsnj67w5R714qi/HwXWUuZU4F7xWMrv+ z+Hg== X-Gm-Message-State: ANhLgQ2L5U71VodUl32oTNDLa1UkfweIH7vaX/7kFZvTC8PYUUqmyCnA 4Qnk83Ds4kxhnrvHDEJuB0i7luaNsThY5CFlHWIZNG/usOYcJQYMS/ejP78x0W3bg+xeDmoTyUt PNv6HrKPXLBQeN3M= X-Received: by 2002:adf:83c4:: with SMTP id 62mr73131wre.105.1584374858397; Mon, 16 Mar 2020 09:07:38 -0700 (PDT) X-Google-Smtp-Source: ADFU+vtXZX9N7W7nmymhGKQDv0dc2RHYo7/YhqqMhSWsSZSwUHWK8VJ3cRt1paRdEbEfaNcAsNZgcg== X-Received: by 2002:adf:83c4:: with SMTP id 62mr73091wre.105.1584374857928; Mon, 16 Mar 2020 09:07:37 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 11/19] target/arm: Restrict ARMv5 cpus to TCG accel Date: Mon, 16 Mar 2020 17:06:26 +0100 Message-Id: <20200316160634.3386-12-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 63.128.21.74 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Peter Maydell , Thomas Huth , kvm@vger.kernel.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , qemu-arm@nongnu.org, Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8"; text/plain; charset="utf-8" KVM requires a cpu based on (at least) the ARMv7 architecture. Only enable the following ARMv5 CPUs when TCG is available: - ARM926 - ARM946 - ARM1026 - XScale (PXA250/255/260/261/262/270) Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- default-configs/arm-softmmu.mak | 12 -- target/arm/cpu.c | 234 ---------------------------- target/arm/cpu_v5.c | 266 ++++++++++++++++++++++++++++++++ hw/arm/Kconfig | 7 + target/arm/Kconfig | 4 + target/arm/Makefile.objs | 1 + 6 files changed, 278 insertions(+), 246 deletions(-) create mode 100644 target/arm/cpu_v5.c diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.= mak index 0652396296..f176a98296 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -13,32 +13,20 @@ CONFIG_ARM_VIRT=3Dy CONFIG_CUBIEBOARD=3Dy CONFIG_EXYNOS4=3Dy CONFIG_HIGHBANK=3Dy -CONFIG_INTEGRATOR=3Dy CONFIG_FSL_IMX31=3Dy -CONFIG_MUSICPAL=3Dy CONFIG_MUSCA=3Dy CONFIG_NSERIES=3Dy CONFIG_STELLARIS=3Dy CONFIG_REALVIEW=3Dy -CONFIG_VERSATILE=3Dy CONFIG_VEXPRESS=3Dy CONFIG_ZYNQ=3Dy -CONFIG_MAINSTONE=3Dy -CONFIG_GUMSTIX=3Dy -CONFIG_SPITZ=3Dy -CONFIG_TOSA=3Dy -CONFIG_Z2=3Dy -CONFIG_COLLIE=3Dy -CONFIG_ASPEED_SOC=3Dy CONFIG_NETDUINO2=3Dy CONFIG_NETDUINOPLUS2=3Dy CONFIG_MPS2=3Dy CONFIG_RASPI=3Dy -CONFIG_DIGIC=3Dy CONFIG_SABRELITE=3Dy CONFIG_EMCRAFT_SF2=3Dy CONFIG_MICROBIT=3Dy -CONFIG_FSL_IMX25=3Dy CONFIG_FSL_IMX7=3Dy CONFIG_FSL_IMX6UL=3Dy CONFIG_ALLWINNER_H3=3Dy diff --git a/target/arm/cpu.c b/target/arm/cpu.c index b08b6933be..f1d1ba8451 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1834,86 +1834,6 @@ static ObjectClass *arm_cpu_class_by_name(const char= *cpu_model) /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) =20 -static void arm926_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,arm926"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); - cpu->midr =3D 0x41069265; - cpu->reset_fpsid =3D 0x41011090; - cpu->ctr =3D 0x1dd20d2; - cpu->reset_sctlr =3D 0x00090078; - - /* - * ARMv5 does not have the ID_ISAR registers, but we can still - * set the field to indicate Jazelle support within QEMU. - */ - cpu->isar.id_isar1 =3D FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELL= E, 1); - /* - * Similarly, we need to set MVFR0 fields to enable vfp and short vect= or - * support even though ARMv5 doesn't have this register. - */ - cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); - cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); - cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); -} - -static void arm946_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,arm946"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_PMSA); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - cpu->midr =3D 0x41059461; - cpu->ctr =3D 0x0f004006; - cpu->reset_sctlr =3D 0x00000078; -} - -static void arm1026_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,arm1026"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_AUXCR); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); - cpu->midr =3D 0x4106a262; - cpu->reset_fpsid =3D 0x410110a0; - cpu->ctr =3D 0x1dd20d2; - cpu->reset_sctlr =3D 0x00090078; - cpu->reset_auxcr =3D 1; - - /* - * ARMv5 does not have the ID_ISAR registers, but we can still - * set the field to indicate Jazelle support within QEMU. - */ - cpu->isar.id_isar1 =3D FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELL= E, 1); - /* - * Similarly, we need to set MVFR0 fields to enable vfp and short vect= or - * support even though ARMv5 doesn't have this register. - */ - cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); - cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); - cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); - - { - /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0= ,2 */ - ARMCPRegInfo ifar =3D { - .name =3D "IFAR", .cp =3D 15, .crn =3D 6, .crm =3D 0, .opc1 = =3D 0, .opc2 =3D 1, - .access =3D PL1_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.ifar_ns), - .resetvalue =3D 0 - }; - define_one_arm_cp_reg(cpu, &ifar); - } -} - static void arm1136_r2_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -2459,144 +2379,6 @@ static void cortex_a15_initfn(Object *obj) define_arm_cp_regs(cpu, cortexa15_cp_reginfo); } =20 -static void pxa250_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - cpu->midr =3D 0x69052100; - cpu->ctr =3D 0xd172172; - cpu->reset_sctlr =3D 0x00000078; -} - -static void pxa255_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - cpu->midr =3D 0x69052d00; - cpu->ctr =3D 0xd172172; - cpu->reset_sctlr =3D 0x00000078; -} - -static void pxa260_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - cpu->midr =3D 0x69052903; - cpu->ctr =3D 0xd172172; - cpu->reset_sctlr =3D 0x00000078; -} - -static void pxa261_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - cpu->midr =3D 0x69052d05; - cpu->ctr =3D 0xd172172; - cpu->reset_sctlr =3D 0x00000078; -} - -static void pxa262_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - cpu->midr =3D 0x69052d06; - cpu->ctr =3D 0xd172172; - cpu->reset_sctlr =3D 0x00000078; -} - -static void pxa270a0_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - set_feature(&cpu->env, ARM_FEATURE_IWMMXT); - cpu->midr =3D 0x69054110; - cpu->ctr =3D 0xd172172; - cpu->reset_sctlr =3D 0x00000078; -} - -static void pxa270a1_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - set_feature(&cpu->env, ARM_FEATURE_IWMMXT); - cpu->midr =3D 0x69054111; - cpu->ctr =3D 0xd172172; - cpu->reset_sctlr =3D 0x00000078; -} - -static void pxa270b0_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - set_feature(&cpu->env, ARM_FEATURE_IWMMXT); - cpu->midr =3D 0x69054112; - cpu->ctr =3D 0xd172172; - cpu->reset_sctlr =3D 0x00000078; -} - -static void pxa270b1_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - set_feature(&cpu->env, ARM_FEATURE_IWMMXT); - cpu->midr =3D 0x69054113; - cpu->ctr =3D 0xd172172; - cpu->reset_sctlr =3D 0x00000078; -} - -static void pxa270c0_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - set_feature(&cpu->env, ARM_FEATURE_IWMMXT); - cpu->midr =3D 0x69054114; - cpu->ctr =3D 0xd172172; - cpu->reset_sctlr =3D 0x00000078; -} - -static void pxa270c5_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "marvell,xscale"; - set_feature(&cpu->env, ARM_FEATURE_V5); - set_feature(&cpu->env, ARM_FEATURE_XSCALE); - set_feature(&cpu->env, ARM_FEATURE_IWMMXT); - cpu->midr =3D 0x69054117; - cpu->ctr =3D 0xd172172; - cpu->reset_sctlr =3D 0x00000078; -} - #ifndef TARGET_AARCH64 /* -cpu max: if KVM is enabled, like -cpu host (best possible with this ho= st); * otherwise, a CPU with as many features enabled as our emulation support= s. @@ -2670,9 +2452,6 @@ static void arm_max_initfn(Object *obj) =20 static const ARMCPUInfo arm_cpus[] =3D { #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) - { .name =3D "arm926", .initfn =3D arm926_initfn }, - { .name =3D "arm946", .initfn =3D arm946_initfn }, - { .name =3D "arm1026", .initfn =3D arm1026_initfn }, /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an * older core than plain "arm1136". In particular this does not * have the v6K features. @@ -2697,19 +2476,6 @@ static const ARMCPUInfo arm_cpus[] =3D { { .name =3D "cortex-a8", .initfn =3D cortex_a8_initfn }, { .name =3D "cortex-a9", .initfn =3D cortex_a9_initfn }, { .name =3D "cortex-a15", .initfn =3D cortex_a15_initfn }, - { .name =3D "pxa250", .initfn =3D pxa250_initfn }, - { .name =3D "pxa255", .initfn =3D pxa255_initfn }, - { .name =3D "pxa260", .initfn =3D pxa260_initfn }, - { .name =3D "pxa261", .initfn =3D pxa261_initfn }, - { .name =3D "pxa262", .initfn =3D pxa262_initfn }, - /* "pxa270" is an alias for "pxa270-a0" */ - { .name =3D "pxa270", .initfn =3D pxa270a0_initfn }, - { .name =3D "pxa270-a0", .initfn =3D pxa270a0_initfn }, - { .name =3D "pxa270-a1", .initfn =3D pxa270a1_initfn }, - { .name =3D "pxa270-b0", .initfn =3D pxa270b0_initfn }, - { .name =3D "pxa270-b1", .initfn =3D pxa270b1_initfn }, - { .name =3D "pxa270-c0", .initfn =3D pxa270c0_initfn }, - { .name =3D "pxa270-c5", .initfn =3D pxa270c5_initfn }, #ifndef TARGET_AARCH64 { .name =3D "max", .initfn =3D arm_max_initfn }, #endif diff --git a/target/arm/cpu_v5.c b/target/arm/cpu_v5.c new file mode 100644 index 0000000000..7a231ef649 --- /dev/null +++ b/target/arm/cpu_v5.c @@ -0,0 +1,266 @@ +/* + * ARM generic helpers. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" + +/* CPU models. These are not needed for the AArch64 linux-user build. */ +#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) + +static void arm926_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,arm926"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); + cpu->midr =3D 0x41069265; + cpu->reset_fpsid =3D 0x41011090; + cpu->ctr =3D 0x1dd20d2; + cpu->reset_sctlr =3D 0x00090078; + + /* + * ARMv5 does not have the ID_ISAR registers, but we can still + * set the field to indicate Jazelle support within QEMU. + */ + cpu->isar.id_isar1 =3D FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELL= E, 1); + /* + * Similarly, we need to set MVFR0 fields to enable vfp and short vect= or + * support even though ARMv5 doesn't have this register. + */ + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); +} + +static void arm946_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,arm946"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_PMSA); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + cpu->midr =3D 0x41059461; + cpu->ctr =3D 0x0f004006; + cpu->reset_sctlr =3D 0x00000078; +} + +static void arm1026_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,arm1026"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_AUXCR); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN); + cpu->midr =3D 0x4106a262; + cpu->reset_fpsid =3D 0x410110a0; + cpu->ctr =3D 0x1dd20d2; + cpu->reset_sctlr =3D 0x00090078; + cpu->reset_auxcr =3D 1; + + /* + * ARMv5 does not have the ID_ISAR registers, but we can still + * set the field to indicate Jazelle support within QEMU. + */ + cpu->isar.id_isar1 =3D FIELD_DP32(cpu->isar.id_isar1, ID_ISAR1, JAZELL= E, 1); + /* + * Similarly, we need to set MVFR0 fields to enable vfp and short vect= or + * support even though ARMv5 doesn't have this register. + */ + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSP, 1); + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPDP, 1); + + { + /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0= ,2 */ + ARMCPRegInfo ifar =3D { + .name =3D "IFAR", .cp =3D 15, .crn =3D 6, .crm =3D 0, .opc1 = =3D 0, .opc2 =3D 1, + .access =3D PL1_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.ifar_ns), + .resetvalue =3D 0 + }; + define_one_arm_cp_reg(cpu, &ifar); + } +} + +static void pxa250_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "marvell,xscale"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + cpu->midr =3D 0x69052100; + cpu->ctr =3D 0xd172172; + cpu->reset_sctlr =3D 0x00000078; +} + +static void pxa255_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "marvell,xscale"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + cpu->midr =3D 0x69052d00; + cpu->ctr =3D 0xd172172; + cpu->reset_sctlr =3D 0x00000078; +} + +static void pxa260_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "marvell,xscale"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + cpu->midr =3D 0x69052903; + cpu->ctr =3D 0xd172172; + cpu->reset_sctlr =3D 0x00000078; +} + +static void pxa261_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "marvell,xscale"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + cpu->midr =3D 0x69052d05; + cpu->ctr =3D 0xd172172; + cpu->reset_sctlr =3D 0x00000078; +} + +static void pxa262_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "marvell,xscale"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + cpu->midr =3D 0x69052d06; + cpu->ctr =3D 0xd172172; + cpu->reset_sctlr =3D 0x00000078; +} + +static void pxa270a0_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "marvell,xscale"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + set_feature(&cpu->env, ARM_FEATURE_IWMMXT); + cpu->midr =3D 0x69054110; + cpu->ctr =3D 0xd172172; + cpu->reset_sctlr =3D 0x00000078; +} + +static void pxa270a1_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "marvell,xscale"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + set_feature(&cpu->env, ARM_FEATURE_IWMMXT); + cpu->midr =3D 0x69054111; + cpu->ctr =3D 0xd172172; + cpu->reset_sctlr =3D 0x00000078; +} + +static void pxa270b0_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "marvell,xscale"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + set_feature(&cpu->env, ARM_FEATURE_IWMMXT); + cpu->midr =3D 0x69054112; + cpu->ctr =3D 0xd172172; + cpu->reset_sctlr =3D 0x00000078; +} + +static void pxa270b1_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "marvell,xscale"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + set_feature(&cpu->env, ARM_FEATURE_IWMMXT); + cpu->midr =3D 0x69054113; + cpu->ctr =3D 0xd172172; + cpu->reset_sctlr =3D 0x00000078; +} + +static void pxa270c0_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "marvell,xscale"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + set_feature(&cpu->env, ARM_FEATURE_IWMMXT); + cpu->midr =3D 0x69054114; + cpu->ctr =3D 0xd172172; + cpu->reset_sctlr =3D 0x00000078; +} + +static void pxa270c5_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "marvell,xscale"; + set_feature(&cpu->env, ARM_FEATURE_V5); + set_feature(&cpu->env, ARM_FEATURE_XSCALE); + set_feature(&cpu->env, ARM_FEATURE_IWMMXT); + cpu->midr =3D 0x69054117; + cpu->ctr =3D 0xd172172; + cpu->reset_sctlr =3D 0x00000078; +} + +static const ARMCPUInfo arm_v5_cpus[] =3D { + { .name =3D "arm926", .initfn =3D arm926_initfn }, + { .name =3D "arm946", .initfn =3D arm946_initfn }, + { .name =3D "arm1026", .initfn =3D arm1026_initfn }, + { .name =3D "pxa250", .initfn =3D pxa250_initfn }, + { .name =3D "pxa255", .initfn =3D pxa255_initfn }, + { .name =3D "pxa260", .initfn =3D pxa260_initfn }, + { .name =3D "pxa261", .initfn =3D pxa261_initfn }, + { .name =3D "pxa262", .initfn =3D pxa262_initfn }, + /* "pxa270" is an alias for "pxa270-a0" */ + { .name =3D "pxa270", .initfn =3D pxa270a0_initfn }, + { .name =3D "pxa270-a0", .initfn =3D pxa270a0_initfn }, + { .name =3D "pxa270-a1", .initfn =3D pxa270a1_initfn }, + { .name =3D "pxa270-b0", .initfn =3D pxa270b0_initfn }, + { .name =3D "pxa270-b1", .initfn =3D pxa270b1_initfn }, + { .name =3D "pxa270-c0", .initfn =3D pxa270c0_initfn }, + { .name =3D "pxa270-c5", .initfn =3D pxa270c5_initfn }, + { .name =3D NULL } +}; + +static void arm_v5_cpu_register_types(void) +{ + const ARMCPUInfo *info =3D arm_v5_cpus; + + while (info->name) { + arm_cpu_register(info); + info++; + } +} + +type_init(arm_v5_cpu_register_types) + +#endif diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 7fc0cff776..3b78471de0 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -38,6 +38,7 @@ config CUBIEBOARD =20 config DIGIC bool + select ARM_V5 select PTIMER select PFLASH_CFI02 =20 @@ -67,6 +68,7 @@ config HIGHBANK =20 config INTEGRATOR bool + select ARM_V5 select ARM_TIMER select INTEGRATOR_DEBUG select PL011 # UART @@ -93,6 +95,7 @@ config MUSCA =20 config MUSICPAL bool + select ARM_V5 select BITBANG_I2C select MARVELL_88W8618 select PTIMER @@ -132,6 +135,7 @@ config OMAP =20 config PXA2XX bool + select ARM_V5 select FRAMEBUFFER select I2C select SERIAL @@ -248,6 +252,7 @@ config SX1 =20 config VERSATILE bool + select ARM_V5 select ARM_TIMER # sp804 select PFLASH_CFI01 select LSI_SCSI_PCI @@ -354,6 +359,7 @@ config XLNX_VERSAL =20 config FSL_IMX25 bool + select ARM_V5 select IMX select IMX_FEC select IMX_I2C @@ -376,6 +382,7 @@ config FSL_IMX6 =20 config ASPEED_SOC bool + select ARM_V5 select DS1338 select FTGMAC100 select I2C diff --git a/target/arm/Kconfig b/target/arm/Kconfig index 0d496d318a..028d8382fe 100644 --- a/target/arm/Kconfig +++ b/target/arm/Kconfig @@ -2,5 +2,9 @@ config ARM_V4 depends on TCG bool =20 +config ARM_V5 + depends on TCG + bool + config ARM_V7M bool diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index bc0f63ebbc..f66f7f1158 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -69,6 +69,7 @@ obj-y +=3D iwmmxt_helper.o vec_helper.o neon_helper.o obj-y +=3D m_helper.o =20 obj-$(CONFIG_ARM_V4) +=3D cpu_v4.o +obj-$(CONFIG_ARM_V5) +=3D cpu_v5.o =20 obj-$(CONFIG_SOFTMMU) +=3D psci.o =20 --=20 2.21.1 From nobody Fri May 3 01:46:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[83.59.163.96]) by smtp.gmail.com with ESMTPSA id 96sm549814wrm.63.2020.03.16.09.07.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:07:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1584375167; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=Bev69B8UQo4K2rDxR5YSrNIDlGaBvtKUt0JmYj+W6cM=; b=fSG72dvjhenKG5ofuczfpjETTanNmTQTyTEZWe8LJ1zi9h6a0hdzuWqflFIoomMCCt5cyH 9MYWQ0XGR5eMqFk1GTnBY7Vra7tmTL0XQICBjqOvHITHU+7pLfBfYOOZFKTgwgv69myu7X MAACXcgQXgzttkw6SDlDW9kWjcU0ygM= X-MC-Unique: tkO4lIOdMyygnQ2TsPg9yQ-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wL60xHob88fQ7VIPeFS5XLuacMMTzsdimp2PvDIHEac=; b=C4/6YJpCNrkCEwvXaiZYE9nIzbS8KoL8HXDPSc32ZOiBberrMCwdIxLkUJ5JBH0cOU DZ683YEX/dXjTWPbC2VytRktiSSO0JbD3JL9LenksRdeLdp+rq8AfPvN9eFTB7I0cb4o U+5hGzDOFscA3CwNlmxPmmA/XXZpo/ULwn62957/tNybaIPYWmwWjcFTSeQpRF/w1mt4 487y4tPhTa9Kb0yNVhFJ83ZFc2Jd0NaB45HhC2rjajbmbAwYTLsiSNA48MfqXpqybmEU iTxxWL4bFBaaoJlKnqWT0/i+scyQsfceXwpKgTFv2p+TAODjyR34YfPaSUVXTHKtHklm vwzA== X-Gm-Message-State: ANhLgQ1rGrVP1x93iCe6aH8XRMlfLthEhDCn18sOwzAOi/3JmDAWhiup axjLNaF5ddL3cBeIgOLVUd/Sv7Yt13tjH77IRRf1El7fei5g+v3Ng5y9KI2gW9gzMMiW9iX0bIc /SgW8mgXc9JrNmHM= X-Received: by 2002:a1c:7e57:: with SMTP id z84mr27973263wmc.148.1584374863911; Mon, 16 Mar 2020 09:07:43 -0700 (PDT) X-Google-Smtp-Source: ADFU+vuuel+IgN0ODwNbK6ZFzKt+p1vYcd4ktsX8FiFd1ybGIsy2EPitjEqzcxIwOwndB4N0aPiXAg== X-Received: by 2002:a1c:7e57:: with SMTP id z84mr27973218wmc.148.1584374863467; Mon, 16 Mar 2020 09:07:43 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 12/19] target/arm: Restrict ARMv6 cpus to TCG accel Date: Mon, 16 Mar 2020 17:06:27 +0100 Message-Id: <20200316160634.3386-13-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 216.205.24.74 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Peter Maydell , Thomas Huth , kvm@vger.kernel.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , qemu-arm@nongnu.org, Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8"; text/plain; charset="utf-8" KVM requires a cpu based on (at least) the ARMv7 architecture. Only enable the following ARMv6 CPUs when TCG is available: - ARM1136 - ARM1176 - ARM11MPCore - Cortex-M0 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- default-configs/arm-softmmu.mak | 2 - target/arm/cpu.c | 137 ------------------------- target/arm/cpu_v6.c | 171 ++++++++++++++++++++++++++++++++ hw/arm/Kconfig | 2 + target/arm/Kconfig | 4 + target/arm/Makefile.objs | 1 + 6 files changed, 178 insertions(+), 139 deletions(-) create mode 100644 target/arm/cpu_v6.c diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.= mak index f176a98296..3aa27f3b40 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -13,9 +13,7 @@ CONFIG_ARM_VIRT=3Dy CONFIG_CUBIEBOARD=3Dy CONFIG_EXYNOS4=3Dy CONFIG_HIGHBANK=3Dy -CONFIG_FSL_IMX31=3Dy CONFIG_MUSCA=3Dy -CONFIG_NSERIES=3Dy CONFIG_STELLARIS=3Dy CONFIG_REALVIEW=3Dy CONFIG_VEXPRESS=3Dy diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f1d1ba8451..34908828a0 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1834,135 +1834,6 @@ static ObjectClass *arm_cpu_class_by_name(const cha= r *cpu_model) /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) =20 -static void arm1136_r2_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an - * older core than plain "arm1136". In particular this does not - * have the v6K features. - * These ID register values are correct for 1136 but may be wrong - * for 1136_r2 (in particular r0p2 does not actually implement most - * of the ID registers). - */ - - cpu->dtb_compatible =3D "arm,arm1136"; - set_feature(&cpu->env, ARM_FEATURE_V6); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); - set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); - cpu->midr =3D 0x4107b362; - cpu->reset_fpsid =3D 0x410120b4; - cpu->isar.mvfr0 =3D 0x11111111; - cpu->isar.mvfr1 =3D 0x00000000; - cpu->ctr =3D 0x1dd20d2; - cpu->reset_sctlr =3D 0x00050078; - cpu->id_pfr0 =3D 0x111; - cpu->id_pfr1 =3D 0x1; - cpu->isar.id_dfr0 =3D 0x2; - cpu->id_afr0 =3D 0x3; - cpu->isar.id_mmfr0 =3D 0x01130003; - cpu->isar.id_mmfr1 =3D 0x10030302; - cpu->isar.id_mmfr2 =3D 0x01222110; - cpu->isar.id_isar0 =3D 0x00140011; - cpu->isar.id_isar1 =3D 0x12002111; - cpu->isar.id_isar2 =3D 0x11231111; - cpu->isar.id_isar3 =3D 0x01102131; - cpu->isar.id_isar4 =3D 0x141; - cpu->reset_auxcr =3D 7; -} - -static void arm1136_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,arm1136"; - set_feature(&cpu->env, ARM_FEATURE_V6K); - set_feature(&cpu->env, ARM_FEATURE_V6); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); - set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); - cpu->midr =3D 0x4117b363; - cpu->reset_fpsid =3D 0x410120b4; - cpu->isar.mvfr0 =3D 0x11111111; - cpu->isar.mvfr1 =3D 0x00000000; - cpu->ctr =3D 0x1dd20d2; - cpu->reset_sctlr =3D 0x00050078; - cpu->id_pfr0 =3D 0x111; - cpu->id_pfr1 =3D 0x1; - cpu->isar.id_dfr0 =3D 0x2; - cpu->id_afr0 =3D 0x3; - cpu->isar.id_mmfr0 =3D 0x01130003; - cpu->isar.id_mmfr1 =3D 0x10030302; - cpu->isar.id_mmfr2 =3D 0x01222110; - cpu->isar.id_isar0 =3D 0x00140011; - cpu->isar.id_isar1 =3D 0x12002111; - cpu->isar.id_isar2 =3D 0x11231111; - cpu->isar.id_isar3 =3D 0x01102131; - cpu->isar.id_isar4 =3D 0x141; - cpu->reset_auxcr =3D 7; -} - -static void arm1176_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,arm1176"; - set_feature(&cpu->env, ARM_FEATURE_V6K); - set_feature(&cpu->env, ARM_FEATURE_VAPA); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); - set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); - set_feature(&cpu->env, ARM_FEATURE_EL3); - cpu->midr =3D 0x410fb767; - cpu->reset_fpsid =3D 0x410120b5; - cpu->isar.mvfr0 =3D 0x11111111; - cpu->isar.mvfr1 =3D 0x00000000; - cpu->ctr =3D 0x1dd20d2; - cpu->reset_sctlr =3D 0x00050078; - cpu->id_pfr0 =3D 0x111; - cpu->id_pfr1 =3D 0x11; - cpu->isar.id_dfr0 =3D 0x33; - cpu->id_afr0 =3D 0; - cpu->isar.id_mmfr0 =3D 0x01130003; - cpu->isar.id_mmfr1 =3D 0x10030302; - cpu->isar.id_mmfr2 =3D 0x01222100; - cpu->isar.id_isar0 =3D 0x0140011; - cpu->isar.id_isar1 =3D 0x12002111; - cpu->isar.id_isar2 =3D 0x11231121; - cpu->isar.id_isar3 =3D 0x01102131; - cpu->isar.id_isar4 =3D 0x01141; - cpu->reset_auxcr =3D 7; -} - -static void arm11mpcore_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cpu->dtb_compatible =3D "arm,arm11mpcore"; - set_feature(&cpu->env, ARM_FEATURE_V6K); - set_feature(&cpu->env, ARM_FEATURE_VAPA); - set_feature(&cpu->env, ARM_FEATURE_MPIDR); - set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); - cpu->midr =3D 0x410fb022; - cpu->reset_fpsid =3D 0x410120b4; - cpu->isar.mvfr0 =3D 0x11111111; - cpu->isar.mvfr1 =3D 0x00000000; - cpu->ctr =3D 0x1d192992; /* 32K icache 32K dcache */ - cpu->id_pfr0 =3D 0x111; - cpu->id_pfr1 =3D 0x1; - cpu->isar.id_dfr0 =3D 0; - cpu->id_afr0 =3D 0x2; - cpu->isar.id_mmfr0 =3D 0x01100103; - cpu->isar.id_mmfr1 =3D 0x10020302; - cpu->isar.id_mmfr2 =3D 0x01222000; - cpu->isar.id_isar0 =3D 0x00100011; - cpu->isar.id_isar1 =3D 0x12002111; - cpu->isar.id_isar2 =3D 0x11221011; - cpu->isar.id_isar3 =3D 0x01102131; - cpu->isar.id_isar4 =3D 0x141; - cpu->reset_auxcr =3D 1; -} - static void cortex_m0_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -2452,14 +2323,6 @@ static void arm_max_initfn(Object *obj) =20 static const ARMCPUInfo arm_cpus[] =3D { #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) - /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an - * older core than plain "arm1136". In particular this does not - * have the v6K features. - */ - { .name =3D "arm1136-r2", .initfn =3D arm1136_r2_initfn }, - { .name =3D "arm1136", .initfn =3D arm1136_initfn }, - { .name =3D "arm1176", .initfn =3D arm1176_initfn }, - { .name =3D "arm11mpcore", .initfn =3D arm11mpcore_initfn }, { .name =3D "cortex-m0", .initfn =3D cortex_m0_initfn, .class_init =3D arm_v7m_class_init }, { .name =3D "cortex-m3", .initfn =3D cortex_m3_initfn, diff --git a/target/arm/cpu_v6.c b/target/arm/cpu_v6.c new file mode 100644 index 0000000000..1c73c881f3 --- /dev/null +++ b/target/arm/cpu_v6.c @@ -0,0 +1,171 @@ +/* + * ARM generic helpers. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" + +/* CPU models. These are not needed for the AArch64 linux-user build. */ +#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) + +static void arm1136_r2_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + /* + * What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an + * older core than plain "arm1136". In particular this does not + * have the v6K features. + * These ID register values are correct for 1136 but may be wrong + * for 1136_r2 (in particular r0p2 does not actually implement most + * of the ID registers). + */ + + cpu->dtb_compatible =3D "arm,arm1136"; + set_feature(&cpu->env, ARM_FEATURE_V6); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); + set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); + cpu->midr =3D 0x4107b362; + cpu->reset_fpsid =3D 0x410120b4; + cpu->isar.mvfr0 =3D 0x11111111; + cpu->isar.mvfr1 =3D 0x00000000; + cpu->ctr =3D 0x1dd20d2; + cpu->reset_sctlr =3D 0x00050078; + cpu->id_pfr0 =3D 0x111; + cpu->id_pfr1 =3D 0x1; + cpu->isar.id_dfr0 =3D 0x2; + cpu->id_afr0 =3D 0x3; + cpu->isar.id_mmfr0 =3D 0x01130003; + cpu->isar.id_mmfr1 =3D 0x10030302; + cpu->isar.id_mmfr2 =3D 0x01222110; + cpu->isar.id_isar0 =3D 0x00140011; + cpu->isar.id_isar1 =3D 0x12002111; + cpu->isar.id_isar2 =3D 0x11231111; + cpu->isar.id_isar3 =3D 0x01102131; + cpu->isar.id_isar4 =3D 0x141; + cpu->reset_auxcr =3D 7; +} + +static void arm1136_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,arm1136"; + set_feature(&cpu->env, ARM_FEATURE_V6K); + set_feature(&cpu->env, ARM_FEATURE_V6); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); + set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); + cpu->midr =3D 0x4117b363; + cpu->reset_fpsid =3D 0x410120b4; + cpu->isar.mvfr0 =3D 0x11111111; + cpu->isar.mvfr1 =3D 0x00000000; + cpu->ctr =3D 0x1dd20d2; + cpu->reset_sctlr =3D 0x00050078; + cpu->id_pfr0 =3D 0x111; + cpu->id_pfr1 =3D 0x1; + cpu->isar.id_dfr0 =3D 0x2; + cpu->id_afr0 =3D 0x3; + cpu->isar.id_mmfr0 =3D 0x01130003; + cpu->isar.id_mmfr1 =3D 0x10030302; + cpu->isar.id_mmfr2 =3D 0x01222110; + cpu->isar.id_isar0 =3D 0x00140011; + cpu->isar.id_isar1 =3D 0x12002111; + cpu->isar.id_isar2 =3D 0x11231111; + cpu->isar.id_isar3 =3D 0x01102131; + cpu->isar.id_isar4 =3D 0x141; + cpu->reset_auxcr =3D 7; +} + +static void arm1176_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,arm1176"; + set_feature(&cpu->env, ARM_FEATURE_V6K); + set_feature(&cpu->env, ARM_FEATURE_VAPA); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG); + set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS); + set_feature(&cpu->env, ARM_FEATURE_EL3); + cpu->midr =3D 0x410fb767; + cpu->reset_fpsid =3D 0x410120b5; + cpu->isar.mvfr0 =3D 0x11111111; + cpu->isar.mvfr1 =3D 0x00000000; + cpu->ctr =3D 0x1dd20d2; + cpu->reset_sctlr =3D 0x00050078; + cpu->id_pfr0 =3D 0x111; + cpu->id_pfr1 =3D 0x11; + cpu->isar.id_dfr0 =3D 0x33; + cpu->id_afr0 =3D 0; + cpu->isar.id_mmfr0 =3D 0x01130003; + cpu->isar.id_mmfr1 =3D 0x10030302; + cpu->isar.id_mmfr2 =3D 0x01222100; + cpu->isar.id_isar0 =3D 0x0140011; + cpu->isar.id_isar1 =3D 0x12002111; + cpu->isar.id_isar2 =3D 0x11231121; + cpu->isar.id_isar3 =3D 0x01102131; + cpu->isar.id_isar4 =3D 0x01141; + cpu->reset_auxcr =3D 7; +} + +static void arm11mpcore_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,arm11mpcore"; + set_feature(&cpu->env, ARM_FEATURE_V6K); + set_feature(&cpu->env, ARM_FEATURE_VAPA); + set_feature(&cpu->env, ARM_FEATURE_MPIDR); + set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS); + cpu->midr =3D 0x410fb022; + cpu->reset_fpsid =3D 0x410120b4; + cpu->isar.mvfr0 =3D 0x11111111; + cpu->isar.mvfr1 =3D 0x00000000; + cpu->ctr =3D 0x1d192992; /* 32K icache 32K dcache */ + cpu->id_pfr0 =3D 0x111; + cpu->id_pfr1 =3D 0x1; + cpu->isar.id_dfr0 =3D 0; + cpu->id_afr0 =3D 0x2; + cpu->isar.id_mmfr0 =3D 0x01100103; + cpu->isar.id_mmfr1 =3D 0x10020302; + cpu->isar.id_mmfr2 =3D 0x01222000; + cpu->isar.id_isar0 =3D 0x00100011; + cpu->isar.id_isar1 =3D 0x12002111; + cpu->isar.id_isar2 =3D 0x11221011; + cpu->isar.id_isar3 =3D 0x01102131; + cpu->isar.id_isar4 =3D 0x141; + cpu->reset_auxcr =3D 1; +} + +static const ARMCPUInfo arm_v6_cpus[] =3D { + /* + * What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. + * an older core than plain "arm1136". In particular this does + * not have the v6K features. + */ + { .name =3D "arm1136-r2", .initfn =3D arm1136_r2_initfn }, + { .name =3D "arm1136", .initfn =3D arm1136_initfn }, + { .name =3D "arm1176", .initfn =3D arm1176_initfn }, + { .name =3D "arm11mpcore", .initfn =3D arm11mpcore_initfn }, + { .name =3D NULL } +}; + +static void arm_v6_cpu_register_types(void) +{ + const ARMCPUInfo *info =3D arm_v6_cpus; + + while (info->name) { + arm_cpu_register(info); + info++; + } +} + +type_init(arm_v6_cpu_register_types) + +#endif diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 3b78471de0..e87dd611f2 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -113,6 +113,7 @@ config NETDUINOPLUS2 =20 config NSERIES bool + select ARM_V6 select OMAP select TMP105 # tempature sensor select BLIZZARD # LCD/TV controller @@ -367,6 +368,7 @@ config FSL_IMX25 =20 config FSL_IMX31 bool + select ARM_V6 select SERIAL select IMX select IMX_I2C diff --git a/target/arm/Kconfig b/target/arm/Kconfig index 028d8382fe..df5f8dff42 100644 --- a/target/arm/Kconfig +++ b/target/arm/Kconfig @@ -6,5 +6,9 @@ config ARM_V5 depends on TCG bool =20 +config ARM_V6 + depends on TCG + bool + config ARM_V7M bool diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index f66f7f1158..0473c559c6 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -70,6 +70,7 @@ obj-y +=3D m_helper.o =20 obj-$(CONFIG_ARM_V4) +=3D cpu_v4.o obj-$(CONFIG_ARM_V5) +=3D cpu_v5.o +obj-$(CONFIG_ARM_V6) +=3D cpu_v6.o =20 obj-$(CONFIG_SOFTMMU) +=3D psci.o =20 --=20 2.21.1 From nobody Fri May 3 01:46:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1584378179; cv=none; d=zohomail.com; s=zohoarc; b=TuNq5JWUjeUMyQkQ5d8hpSrencG2tryHQNzaIQc1mQeilEZMDIWXd9FdBkWZUKhRY7eLw/Ldvz3o8K+RRCRHMcZvzDO98SLAu0BoP3uZQmeWGNM0XAc0MPP3HsEcEJCSLyyD1euNEM4pRLh15OYw3YHATk9pRHXE+5eQ40djg/s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1584378179; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=x0ZyIeVBAofuqhcgRt+fU6Yvdf8+u5Qk+4HNNCwjbvc=; b=NsSkvveCtPT3uf6mrqcrdiq0tI0byRmkpU8JsJVWQi3plPPNElZ806qs14F3F97eTbtxxgu8aMUfWA4Tvwh31yEzfuDZmso9kwEl+Rhk8xgUpg/wIPntM3kwicmqRB4h9SnyedmHMB9Pcagq3sn3zJH7gGSorkMuBchfHFiQPEQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1584378179961383.7752201711718; Mon, 16 Mar 2020 10:02:59 -0700 (PDT) Received: from localhost ([::1]:43032 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jDt8k-0006yB-Oq for importer@patchew.org; Mon, 16 Mar 2020 13:02:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55261) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jDsHS-0004YR-ML for qemu-devel@nongnu.org; Mon, 16 Mar 2020 12:07:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jDsHQ-0004MW-Sm for qemu-devel@nongnu.org; Mon, 16 Mar 2020 12:07:54 -0400 Received: from us-smtp-delivery-74.mimecast.com ([216.205.24.74]:45528) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jDsHQ-0004LB-P3 for qemu-devel@nongnu.org; Mon, 16 Mar 2020 12:07:52 -0400 Received: from mail-wm1-f69.google.com (mail-wm1-f69.google.com [209.85.128.69]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-435-EyY_75xvMzmits6HaBNj3A-1; Mon, 16 Mar 2020 12:07:50 -0400 Received: by mail-wm1-f69.google.com with SMTP id g26so4804654wmk.6 for ; Mon, 16 Mar 2020 09:07:50 -0700 (PDT) Received: from localhost.localdomain (96.red-83-59-163.dynamicip.rima-tde.net. [83.59.163.96]) by smtp.gmail.com with ESMTPSA id k9sm494508wrd.74.2020.03.16.09.07.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:07:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1584374872; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=x0ZyIeVBAofuqhcgRt+fU6Yvdf8+u5Qk+4HNNCwjbvc=; b=Pld/OcLA5s/WReK1Vy782jEtty3WCM4FxSyowyXF/e89gtNQtCEcuzXW+seq4q0PZ1wk7s l+unScBAC3CoyBLG2iNRSF0f28dmqrJXIqLnQ6xnMPObhDPUOmqnEEdEwriUUm1PYZrTH2 O40Jv9es/V+NGUDg7hQhHSrilCYTSmg= X-MC-Unique: EyY_75xvMzmits6HaBNj3A-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ruq5flSyrIJQ0ARl8BHVFpMVJrCuW/pkqeZBiZJSNHg=; b=OghQSfNwaqTBETvS6qaoadskNMNCV5q1MdglUBlmONWAOtaFpgUV5uaazsNgV3D2fM 8XWa8b0sy1VFdEeo/+gpnDuFpMXM5evwR4cSuF8dz19XHWrelCblEZawpcn0dgwof1Jw TXy8habVTSGS4JvFvUEFPL1kE5oPF3oJZhsUfwB+i+zoCxuhwlJt4ZlVbrCrXm0bOUDk dAZV7n5ncNy+nxhi/juw5AFH4Jen4jZjO5FA1frsmExaILwOanQguYuvE+I5swJyx39M vfGbO0REsHROnuMb538u07vU43aDLppeY+HqmOYX2jiM6/ZfmziztBSsyuqjIwOaXZ2Y BSMw== X-Gm-Message-State: ANhLgQ07J8BZ0ATaaMrX4Rk6voa/svspUW0NHQhbsztgYpA4ZSyasNgv 3BruclEMIZh4ow0XwVCxkFZgPnYFkzLpV3tFi5NI23j2t9q2hLs6aPT09tKFFTSwqCyQdMTTQmv 63i1e6Qse/gpBf9I= X-Received: by 2002:a5d:5089:: with SMTP id a9mr63915wrt.187.1584374869132; Mon, 16 Mar 2020 09:07:49 -0700 (PDT) X-Google-Smtp-Source: ADFU+vsH9erD+/AzduZt6/2G1VOVoVwqiEnP7oEPNYJjE5gdXKGGdo2hHizz2wb54XtGoBPo2ebMbQ== X-Received: by 2002:a5d:5089:: with SMTP id a9mr63883wrt.187.1584374868815; Mon, 16 Mar 2020 09:07:48 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 13/19] target/arm: Restrict ARMv7 R-profile cpus to TCG accel Date: Mon, 16 Mar 2020 17:06:28 +0100 Message-Id: <20200316160634.3386-14-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 216.205.24.74 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Peter Maydell , Thomas Huth , kvm@vger.kernel.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , qemu-arm@nongnu.org, Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8"; text/plain; charset="utf-8" A KVM-only build won't be able to run R-profile cpus. Only enable the following ARMv7 R-Profile CPUs when TCG is available: - Cortex-R5 - Cortex-R5F Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- default-configs/aarch64-softmmu.mak | 1 - target/arm/cpu.c | 51 ------------------ target/arm/cpu_v7r.c | 83 +++++++++++++++++++++++++++++ hw/arm/Kconfig | 1 + target/arm/Kconfig | 4 ++ target/arm/Makefile.objs | 1 + 6 files changed, 89 insertions(+), 52 deletions(-) create mode 100644 target/arm/cpu_v7r.c diff --git a/default-configs/aarch64-softmmu.mak b/default-configs/aarch64-= softmmu.mak index 958b1e08e4..a4202f5681 100644 --- a/default-configs/aarch64-softmmu.mak +++ b/default-configs/aarch64-softmmu.mak @@ -3,6 +3,5 @@ # We support all the 32 bit boards so need all their config include arm-softmmu.mak =20 -CONFIG_XLNX_ZYNQMP_ARM=3Dy CONFIG_XLNX_VERSAL=3Dy CONFIG_SBSA_REF=3Dy diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 34908828a0..84be8792f6 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1975,55 +1975,6 @@ static void arm_v7m_class_init(ObjectClass *oc, void= *data) cc->cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt; } =20 -static const ARMCPRegInfo cortexr5_cp_reginfo[] =3D { - /* Dummy the TCM region regs for the moment */ - { .name =3D "ATCM", .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 1, .= opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_CONST }, - { .name =3D "BTCM", .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 1, .= opc2 =3D 1, - .access =3D PL1_RW, .type =3D ARM_CP_CONST }, - { .name =3D "DCACHE_INVAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 15, .crm= =3D 5, - .opc2 =3D 0, .access =3D PL1_W, .type =3D ARM_CP_NOP }, - REGINFO_SENTINEL -}; - -static void cortex_r5_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_V7MP); - set_feature(&cpu->env, ARM_FEATURE_PMSA); - set_feature(&cpu->env, ARM_FEATURE_PMU); - cpu->midr =3D 0x411fc153; /* r1p3 */ - cpu->id_pfr0 =3D 0x0131; - cpu->id_pfr1 =3D 0x001; - cpu->isar.id_dfr0 =3D 0x010400; - cpu->id_afr0 =3D 0x0; - cpu->isar.id_mmfr0 =3D 0x0210030; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x01200000; - cpu->isar.id_mmfr3 =3D 0x0211; - cpu->isar.id_isar0 =3D 0x02101111; - cpu->isar.id_isar1 =3D 0x13112111; - cpu->isar.id_isar2 =3D 0x21232141; - cpu->isar.id_isar3 =3D 0x01112131; - cpu->isar.id_isar4 =3D 0x0010142; - cpu->isar.id_isar5 =3D 0x0; - cpu->isar.id_isar6 =3D 0x0; - cpu->mp_is_up =3D true; - cpu->pmsav7_dregion =3D 16; - define_arm_cp_regs(cpu, cortexr5_cp_reginfo); -} - -static void cortex_r5f_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - cortex_r5_initfn(obj); - cpu->isar.mvfr0 =3D 0x10110221; - cpu->isar.mvfr1 =3D 0x00000011; -} - static const ARMCPRegInfo cortexa8_cp_reginfo[] =3D { { .name =3D "L2LOCKDOWN", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 = =3D 1, .opc2 =3D 0, .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, @@ -2333,8 +2284,6 @@ static const ARMCPUInfo arm_cpus[] =3D { .class_init =3D arm_v7m_class_init }, { .name =3D "cortex-m33", .initfn =3D cortex_m33_initfn, .class_init =3D arm_v7m_class_init }, - { .name =3D "cortex-r5", .initfn =3D cortex_r5_initfn }, - { .name =3D "cortex-r5f", .initfn =3D cortex_r5f_initfn }, { .name =3D "cortex-a7", .initfn =3D cortex_a7_initfn }, { .name =3D "cortex-a8", .initfn =3D cortex_a8_initfn }, { .name =3D "cortex-a9", .initfn =3D cortex_a9_initfn }, diff --git a/target/arm/cpu_v7r.c b/target/arm/cpu_v7r.c new file mode 100644 index 0000000000..9576844b5c --- /dev/null +++ b/target/arm/cpu_v7r.c @@ -0,0 +1,83 @@ +/* + * ARM generic helpers. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" + +/* CPU models. These are not needed for the AArch64 linux-user build. */ +#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) + +static const ARMCPRegInfo cortexr5_cp_reginfo[] =3D { + /* Dummy the TCM region regs for the moment */ + { .name =3D "ATCM", .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 1, .= opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST }, + { .name =3D "BTCM", .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 1, .= opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_CONST }, + { .name =3D "DCACHE_INVAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 15, .crm= =3D 5, + .opc2 =3D 0, .access =3D PL1_W, .type =3D ARM_CP_NOP }, + REGINFO_SENTINEL +}; + +static void cortex_r5_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_V7MP); + set_feature(&cpu->env, ARM_FEATURE_PMSA); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->midr =3D 0x411fc153; /* r1p3 */ + cpu->id_pfr0 =3D 0x0131; + cpu->id_pfr1 =3D 0x001; + cpu->isar.id_dfr0 =3D 0x010400; + cpu->id_afr0 =3D 0x0; + cpu->isar.id_mmfr0 =3D 0x0210030; + cpu->isar.id_mmfr1 =3D 0x00000000; + cpu->isar.id_mmfr2 =3D 0x01200000; + cpu->isar.id_mmfr3 =3D 0x0211; + cpu->isar.id_isar0 =3D 0x02101111; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232141; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x0010142; + cpu->isar.id_isar5 =3D 0x0; + cpu->isar.id_isar6 =3D 0x0; + cpu->mp_is_up =3D true; + cpu->pmsav7_dregion =3D 16; + define_arm_cp_regs(cpu, cortexr5_cp_reginfo); +} + +static void cortex_r5f_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cortex_r5_initfn(obj); + cpu->isar.mvfr0 =3D 0x10110221; + cpu->isar.mvfr1 =3D 0x00000011; +} + +static const ARMCPUInfo arm_v7r_cpus[] =3D { + { .name =3D "cortex-r5", .initfn =3D cortex_r5_initfn }, + { .name =3D "cortex-r5f", .initfn =3D cortex_r5f_initfn }, + { .name =3D NULL } +}; + +static void arm_v7r_cpu_register_types(void) +{ + const ARMCPUInfo *info =3D arm_v7r_cpus; + + while (info->name) { + arm_cpu_register(info); + info++; + } +} + +type_init(arm_v7r_cpu_register_types) + +#endif diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index e87dd611f2..d0903d8544 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -340,6 +340,7 @@ config XLNX_ZYNQMP_ARM bool select AHCI select ARM_GIC + select ARM_V7R select CADENCE select DDC select DPCD diff --git a/target/arm/Kconfig b/target/arm/Kconfig index df5f8dff42..9768f9180f 100644 --- a/target/arm/Kconfig +++ b/target/arm/Kconfig @@ -10,5 +10,9 @@ config ARM_V6 depends on TCG bool =20 +config ARM_V7R + depends on TCG + bool + config ARM_V7M bool diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 0473c559c6..a2508f0655 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -71,6 +71,7 @@ obj-y +=3D m_helper.o obj-$(CONFIG_ARM_V4) +=3D cpu_v4.o obj-$(CONFIG_ARM_V5) +=3D cpu_v5.o obj-$(CONFIG_ARM_V6) +=3D cpu_v6.o +obj-$(CONFIG_ARM_V7R) +=3D cpu_v7r.o =20 obj-$(CONFIG_SOFTMMU) +=3D psci.o =20 --=20 2.21.1 From nobody Fri May 3 01:46:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[83.59.163.96]) by smtp.gmail.com with ESMTPSA id u25sm215843wml.17.2020.03.16.09.07.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:07:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1584374880; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=xvIh8Ri8MGdsRwEuM5pCIZMdFKEO3pS7XtCgO8xIIro=; b=ER7wfCAgUGkDTZE6uCX3kipzu5rBhYubmpOkWOnZKZkJP+XAUFQBdYrepDuorHzuwsxv2h zvd4Ep/AXuLI1p8TcyQBTCDo2Ebr5AjmW/beFJspaumYFqOmAqOJY4OMrdirm4xop1Etq/ blfkk0sidDyQiA3HcgqbSnI/FwBn+Vw= X-MC-Unique: zncu3tFzMMS6pFlXzATcxA-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2dfDnran3E3vJVzOwh1qQwExgfNmDOU0PLsSJKRIuHk=; b=AiRlv/valUDKoUTzhRssNxGds1JXXFWs0zwnXYfujDQgZEnO/k6hRpn7j52JhQVpuW yTMGowzMZrChsRRHMWLGh1/UwP48QGfcJpqIui176bn6A/wE66t2raj2MDY/2Ma374DC vwd7/TEQj5VfmxBbbw9p7RMqyE5imq5ErVCqZVqoa8NYz+eCwrN+1VuIF4E7WZxXVS9P y4yy/PNmatJe96FSjRoKrczxMePWP8A8cd/3Vc0wGu+GxTxkKcU9Ss21n3t/iKSlocv7 egBQ7J2jhggncJxI7BgyN4CS+iKnhLYW/YU+nEx4cCnmnNYiwDNGHJq+O7ei+jnFkbuj 2hAw== X-Gm-Message-State: ANhLgQ28fWBzGtoh9SwB8k0X8T+DdDG55KFEzpDMwR+1a82atsYMyyV6 1IvYXo1g9V15W+sbE3q3YC8CMGO99YoVp96RDcjiiLlu+g3YcmNqh3vLPPRh5sIb601ILn6pF0T aKWtFpen1DzaWLbg= X-Received: by 2002:a1c:a70f:: with SMTP id q15mr29224306wme.66.1584374875542; Mon, 16 Mar 2020 09:07:55 -0700 (PDT) X-Google-Smtp-Source: ADFU+vvvUsowZLHDxnYfDB3bDiW71se1HIHUXOcWI+nMKioBIiFsS1gl8oiiU5/RpwkxKCUDyY8mEA== X-Received: by 2002:a1c:a70f:: with SMTP id q15mr29224211wme.66.1584374874213; Mon, 16 Mar 2020 09:07:54 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 14/19] target/arm: Restrict ARMv7 M-profile cpus to TCG accel Date: Mon, 16 Mar 2020 17:06:29 +0100 Message-Id: <20200316160634.3386-15-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 63.128.21.74 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Peter Maydell , Thomas Huth , kvm@vger.kernel.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , qemu-arm@nongnu.org, Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8"; text/plain; charset="utf-8" A KVM-only build won't be able to run M-profile cpus. Only enable the following ARMv7 M-Profile CPUs when TCG is available: - Cortex-M3 - Cortex-M4 - Cortex-M33 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- default-configs/arm-softmmu.mak | 8 -- target/arm/cpu.c | 176 --------------------------- target/arm/cpu_v7m.c | 207 ++++++++++++++++++++++++++++++++ target/arm/Kconfig | 1 + target/arm/Makefile.objs | 1 + 5 files changed, 209 insertions(+), 184 deletions(-) create mode 100644 target/arm/cpu_v7m.c diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.= mak index 3aa27f3b40..511d74da58 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -12,19 +12,11 @@ CONFIG_ARM_V7M=3Dy CONFIG_ARM_VIRT=3Dy CONFIG_CUBIEBOARD=3Dy CONFIG_EXYNOS4=3Dy -CONFIG_HIGHBANK=3Dy -CONFIG_MUSCA=3Dy -CONFIG_STELLARIS=3Dy CONFIG_REALVIEW=3Dy CONFIG_VEXPRESS=3Dy CONFIG_ZYNQ=3Dy -CONFIG_NETDUINO2=3Dy -CONFIG_NETDUINOPLUS2=3Dy -CONFIG_MPS2=3Dy CONFIG_RASPI=3Dy CONFIG_SABRELITE=3Dy -CONFIG_EMCRAFT_SF2=3Dy -CONFIG_MICROBIT=3Dy CONFIG_FSL_IMX7=3Dy CONFIG_FSL_IMX6UL=3Dy CONFIG_ALLWINNER_H3=3Dy diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 84be8792f6..dfa7e64c7e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -573,31 +573,6 @@ bool arm_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) return true; } =20 -#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) -static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) -{ - CPUClass *cc =3D CPU_GET_CLASS(cs); - ARMCPU *cpu =3D ARM_CPU(cs); - CPUARMState *env =3D &cpu->env; - bool ret =3D false; - - /* ARMv7-M interrupt masking works differently than -A or -R. - * There is no FIQ/IRQ distinction. Instead of I and F bits - * masking FIQ and IRQ interrupts, an exception is taken only - * if it is higher priority than the current execution priority - * (which depends on state like BASEPRI, FAULTMASK and the - * currently active exception). - */ - if (interrupt_request & CPU_INTERRUPT_HARD - && (armv7m_nvic_can_take_pending_exception(env->nvic))) { - cs->exception_index =3D EXCP_IRQ; - cc->do_interrupt(cs); - ret =3D true; - } - return ret; -} -#endif - void arm_cpu_update_virq(ARMCPU *cpu) { /* @@ -1834,147 +1809,6 @@ static ObjectClass *arm_cpu_class_by_name(const cha= r *cpu_model) /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) =20 -static void cortex_m0_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - set_feature(&cpu->env, ARM_FEATURE_V6); - set_feature(&cpu->env, ARM_FEATURE_M); - - cpu->midr =3D 0x410cc200; -} - -static void cortex_m3_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_M); - set_feature(&cpu->env, ARM_FEATURE_M_MAIN); - cpu->midr =3D 0x410fc231; - cpu->pmsav7_dregion =3D 8; - cpu->id_pfr0 =3D 0x00000030; - cpu->id_pfr1 =3D 0x00000200; - cpu->isar.id_dfr0 =3D 0x00100000; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x00000030; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x00000000; - cpu->isar.id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01141110; - cpu->isar.id_isar1 =3D 0x02111000; - cpu->isar.id_isar2 =3D 0x21112231; - cpu->isar.id_isar3 =3D 0x01111110; - cpu->isar.id_isar4 =3D 0x01310102; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; -} - -static void cortex_m4_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_M); - set_feature(&cpu->env, ARM_FEATURE_M_MAIN); - set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); - cpu->midr =3D 0x410fc240; /* r0p0 */ - cpu->pmsav7_dregion =3D 8; - cpu->isar.mvfr0 =3D 0x10110021; - cpu->isar.mvfr1 =3D 0x11000011; - cpu->isar.mvfr2 =3D 0x00000000; - cpu->id_pfr0 =3D 0x00000030; - cpu->id_pfr1 =3D 0x00000200; - cpu->isar.id_dfr0 =3D 0x00100000; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x00000030; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x00000000; - cpu->isar.id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01141110; - cpu->isar.id_isar1 =3D 0x02111000; - cpu->isar.id_isar2 =3D 0x21112231; - cpu->isar.id_isar3 =3D 0x01111110; - cpu->isar.id_isar4 =3D 0x01310102; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; -} - -static void cortex_m7_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - set_feature(&cpu->env, ARM_FEATURE_V7); - set_feature(&cpu->env, ARM_FEATURE_M); - set_feature(&cpu->env, ARM_FEATURE_M_MAIN); - set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); - cpu->midr =3D 0x411fc272; /* r1p2 */ - cpu->pmsav7_dregion =3D 8; - cpu->isar.mvfr0 =3D 0x10110221; - cpu->isar.mvfr1 =3D 0x12000011; - cpu->isar.mvfr2 =3D 0x00000040; - cpu->id_pfr0 =3D 0x00000030; - cpu->id_pfr1 =3D 0x00000200; - cpu->isar.id_dfr0 =3D 0x00100000; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x00100030; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x01000000; - cpu->isar.id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01101110; - cpu->isar.id_isar1 =3D 0x02112000; - cpu->isar.id_isar2 =3D 0x20232231; - cpu->isar.id_isar3 =3D 0x01111131; - cpu->isar.id_isar4 =3D 0x01310132; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; -} - -static void cortex_m33_initfn(Object *obj) -{ - ARMCPU *cpu =3D ARM_CPU(obj); - - set_feature(&cpu->env, ARM_FEATURE_V8); - set_feature(&cpu->env, ARM_FEATURE_M); - set_feature(&cpu->env, ARM_FEATURE_M_MAIN); - set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); - set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); - cpu->midr =3D 0x410fd213; /* r0p3 */ - cpu->pmsav7_dregion =3D 16; - cpu->sau_sregion =3D 8; - cpu->isar.mvfr0 =3D 0x10110021; - cpu->isar.mvfr1 =3D 0x11000011; - cpu->isar.mvfr2 =3D 0x00000040; - cpu->id_pfr0 =3D 0x00000030; - cpu->id_pfr1 =3D 0x00000210; - cpu->isar.id_dfr0 =3D 0x00200000; - cpu->id_afr0 =3D 0x00000000; - cpu->isar.id_mmfr0 =3D 0x00101F40; - cpu->isar.id_mmfr1 =3D 0x00000000; - cpu->isar.id_mmfr2 =3D 0x01000000; - cpu->isar.id_mmfr3 =3D 0x00000000; - cpu->isar.id_isar0 =3D 0x01101110; - cpu->isar.id_isar1 =3D 0x02212000; - cpu->isar.id_isar2 =3D 0x20232232; - cpu->isar.id_isar3 =3D 0x01111131; - cpu->isar.id_isar4 =3D 0x01310132; - cpu->isar.id_isar5 =3D 0x00000000; - cpu->isar.id_isar6 =3D 0x00000000; - cpu->clidr =3D 0x00000000; - cpu->ctr =3D 0x8000c000; -} - -static void arm_v7m_class_init(ObjectClass *oc, void *data) -{ - ARMCPUClass *acc =3D ARM_CPU_CLASS(oc); - CPUClass *cc =3D CPU_CLASS(oc); - - acc->info =3D data; -#ifndef CONFIG_USER_ONLY - cc->do_interrupt =3D arm_v7m_cpu_do_interrupt; -#endif - - cc->cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt; -} - static const ARMCPRegInfo cortexa8_cp_reginfo[] =3D { { .name =3D "L2LOCKDOWN", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 = =3D 1, .opc2 =3D 0, .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, @@ -2274,16 +2108,6 @@ static void arm_max_initfn(Object *obj) =20 static const ARMCPUInfo arm_cpus[] =3D { #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) - { .name =3D "cortex-m0", .initfn =3D cortex_m0_initfn, - .class_init =3D arm_v7m_class_init }, - { .name =3D "cortex-m3", .initfn =3D cortex_m3_initfn, - .class_init =3D arm_v7m_class_init }, - { .name =3D "cortex-m4", .initfn =3D cortex_m4_initfn, - .class_init =3D arm_v7m_class_init }, - { .name =3D "cortex-m7", .initfn =3D cortex_m7_initfn, - .class_init =3D arm_v7m_class_init }, - { .name =3D "cortex-m33", .initfn =3D cortex_m33_initfn, - .class_init =3D arm_v7m_class_init }, { .name =3D "cortex-a7", .initfn =3D cortex_a7_initfn }, { .name =3D "cortex-a8", .initfn =3D cortex_a8_initfn }, { .name =3D "cortex-a9", .initfn =3D cortex_a9_initfn }, diff --git a/target/arm/cpu_v7m.c b/target/arm/cpu_v7m.c new file mode 100644 index 0000000000..529259b9cd --- /dev/null +++ b/target/arm/cpu_v7m.c @@ -0,0 +1,207 @@ +/* + * ARM generic helpers. + * + * This code is licensed under the GNU GPL v2 or later. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internals.h" + +/* CPU models. These are not needed for the AArch64 linux-user build. */ +#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) + +static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + CPUClass *cc =3D CPU_GET_CLASS(cs); + ARMCPU *cpu =3D ARM_CPU(cs); + CPUARMState *env =3D &cpu->env; + bool ret =3D false; + + /* + * ARMv7-M interrupt masking works differently than -A or -R. + * There is no FIQ/IRQ distinction. Instead of I and F bits + * masking FIQ and IRQ interrupts, an exception is taken only + * if it is higher priority than the current execution priority + * (which depends on state like BASEPRI, FAULTMASK and the + * currently active exception). + */ + if (interrupt_request & CPU_INTERRUPT_HARD + && (armv7m_nvic_can_take_pending_exception(env->nvic))) { + cs->exception_index =3D EXCP_IRQ; + cc->do_interrupt(cs); + ret =3D true; + } + return ret; +} + +static void cortex_m0_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V6); + set_feature(&cpu->env, ARM_FEATURE_M); + + cpu->midr =3D 0x410cc200; +} + +static void cortex_m3_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); + cpu->midr =3D 0x410fc231; + cpu->pmsav7_dregion =3D 8; + cpu->id_pfr0 =3D 0x00000030; + cpu->id_pfr1 =3D 0x00000200; + cpu->isar.id_dfr0 =3D 0x00100000; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x00000030; + cpu->isar.id_mmfr1 =3D 0x00000000; + cpu->isar.id_mmfr2 =3D 0x00000000; + cpu->isar.id_mmfr3 =3D 0x00000000; + cpu->isar.id_isar0 =3D 0x01141110; + cpu->isar.id_isar1 =3D 0x02111000; + cpu->isar.id_isar2 =3D 0x21112231; + cpu->isar.id_isar3 =3D 0x01111110; + cpu->isar.id_isar4 =3D 0x01310102; + cpu->isar.id_isar5 =3D 0x00000000; + cpu->isar.id_isar6 =3D 0x00000000; +} + +static void cortex_m4_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); + cpu->midr =3D 0x410fc240; /* r0p0 */ + cpu->pmsav7_dregion =3D 8; + cpu->isar.mvfr0 =3D 0x10110021; + cpu->isar.mvfr1 =3D 0x11000011; + cpu->isar.mvfr2 =3D 0x00000000; + cpu->id_pfr0 =3D 0x00000030; + cpu->id_pfr1 =3D 0x00000200; + cpu->isar.id_dfr0 =3D 0x00100000; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x00000030; + cpu->isar.id_mmfr1 =3D 0x00000000; + cpu->isar.id_mmfr2 =3D 0x00000000; + cpu->isar.id_mmfr3 =3D 0x00000000; + cpu->isar.id_isar0 =3D 0x01141110; + cpu->isar.id_isar1 =3D 0x02111000; + cpu->isar.id_isar2 =3D 0x21112231; + cpu->isar.id_isar3 =3D 0x01111110; + cpu->isar.id_isar4 =3D 0x01310102; + cpu->isar.id_isar5 =3D 0x00000000; + cpu->isar.id_isar6 =3D 0x00000000; +} + +static void cortex_m7_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + set_feature(&cpu->env, ARM_FEATURE_V7); + set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); + cpu->midr =3D 0x411fc272; /* r1p2 */ + cpu->pmsav7_dregion =3D 8; + cpu->isar.mvfr0 =3D 0x10110221; + cpu->isar.mvfr1 =3D 0x12000011; + cpu->isar.mvfr2 =3D 0x00000040; + cpu->id_pfr0 =3D 0x00000030; + cpu->id_pfr1 =3D 0x00000200; + cpu->isar.id_dfr0 =3D 0x00100000; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x00100030; + cpu->isar.id_mmfr1 =3D 0x00000000; + cpu->isar.id_mmfr2 =3D 0x01000000; + cpu->isar.id_mmfr3 =3D 0x00000000; + cpu->isar.id_isar0 =3D 0x01101110; + cpu->isar.id_isar1 =3D 0x02112000; + cpu->isar.id_isar2 =3D 0x20232231; + cpu->isar.id_isar3 =3D 0x01111131; + cpu->isar.id_isar4 =3D 0x01310132; + cpu->isar.id_isar5 =3D 0x00000000; + cpu->isar.id_isar6 =3D 0x00000000; +} + +static void cortex_m33_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_M); + set_feature(&cpu->env, ARM_FEATURE_M_MAIN); + set_feature(&cpu->env, ARM_FEATURE_M_SECURITY); + set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP); + cpu->midr =3D 0x410fd213; /* r0p3 */ + cpu->pmsav7_dregion =3D 16; + cpu->sau_sregion =3D 8; + cpu->isar.mvfr0 =3D 0x10110021; + cpu->isar.mvfr1 =3D 0x11000011; + cpu->isar.mvfr2 =3D 0x00000040; + cpu->id_pfr0 =3D 0x00000030; + cpu->id_pfr1 =3D 0x00000210; + cpu->isar.id_dfr0 =3D 0x00200000; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x00101F40; + cpu->isar.id_mmfr1 =3D 0x00000000; + cpu->isar.id_mmfr2 =3D 0x01000000; + cpu->isar.id_mmfr3 =3D 0x00000000; + cpu->isar.id_isar0 =3D 0x01101110; + cpu->isar.id_isar1 =3D 0x02212000; + cpu->isar.id_isar2 =3D 0x20232232; + cpu->isar.id_isar3 =3D 0x01111131; + cpu->isar.id_isar4 =3D 0x01310132; + cpu->isar.id_isar5 =3D 0x00000000; + cpu->isar.id_isar6 =3D 0x00000000; + cpu->clidr =3D 0x00000000; + cpu->ctr =3D 0x8000c000; +} + +static void arm_v7m_class_init(ObjectClass *oc, void *data) +{ + ARMCPUClass *acc =3D ARM_CPU_CLASS(oc); + CPUClass *cc =3D CPU_CLASS(oc); + + acc->info =3D data; +#ifndef CONFIG_USER_ONLY + cc->do_interrupt =3D arm_v7m_cpu_do_interrupt; +#endif + + cc->cpu_exec_interrupt =3D arm_v7m_cpu_exec_interrupt; +} + +static const ARMCPUInfo arm_v7m_cpus[] =3D { + { .name =3D "cortex-m0", .initfn =3D cortex_m0_initfn, + .class_init =3D arm_v7m_class_init }, + { .name =3D "cortex-m3", .initfn =3D cortex_m3_initfn, + .class_init =3D arm_v7m_class_init }, + { .name =3D "cortex-m4", .initfn =3D cortex_m4_initfn, + .class_init =3D arm_v7m_class_init }, + { .name =3D "cortex-m7", .initfn =3D cortex_m7_initfn, + .class_init =3D arm_v7m_class_init }, + { .name =3D "cortex-m33", .initfn =3D cortex_m33_initfn, + .class_init =3D arm_v7m_class_init }, + { .name =3D NULL } +}; + +static void arm_v7m_cpu_register_types(void) +{ + const ARMCPUInfo *info =3D arm_v7m_cpus; + + while (info->name) { + arm_cpu_register(info); + info++; + } +} + +type_init(arm_v7m_cpu_register_types) + +#endif diff --git a/target/arm/Kconfig b/target/arm/Kconfig index 9768f9180f..929e252d89 100644 --- a/target/arm/Kconfig +++ b/target/arm/Kconfig @@ -15,4 +15,5 @@ config ARM_V7R bool =20 config ARM_V7M + depends on TCG bool diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index a2508f0655..a0df58526b 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -72,6 +72,7 @@ obj-$(CONFIG_ARM_V4) +=3D cpu_v4.o obj-$(CONFIG_ARM_V5) +=3D cpu_v5.o obj-$(CONFIG_ARM_V6) +=3D cpu_v6.o obj-$(CONFIG_ARM_V7R) +=3D cpu_v7r.o +obj-$(CONFIG_ARM_V7M) +=3D cpu_v7m.o =20 obj-$(CONFIG_SOFTMMU) +=3D psci.o =20 --=20 2.21.1 From nobody Fri May 3 01:46:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[83.59.163.96]) by smtp.gmail.com with ESMTPSA id f203sm206459wmf.18.2020.03.16.09.07.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:07:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1584374885; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=ui04JwX7OiOXq/laFXLsBkQhZYSQ3MHjobkDuHeSfV0=; b=CEqpVH6AccFgE6OyyCvobv1P6Su+fxjdCjaDOipj+K1FNLRVvgp9YvCfFihycQxI/Tfo6F xz9i3oVdcgBOA4GL/CuoQYTAkOEVTH8EQUSecp0VpqqROHpmHtc3qIb56liFb/HcBZ3w9f XOf/H6Wpj+6COyfhAqaOudmA1ae+h8Q= X-MC-Unique: -hHRivwnPAGm3piGG9OKrA-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sJ9bxuRVskXYC2aJKl03+Z9cSr20F7Dbm9JRwxmo2e4=; b=QyEyovdQNVYULHVvN0tHBMkbt1rWR145B9b7oYnXwh6BpOe2zWiwUEQYMcMCUte8dA UCoR1yhLv9JCec7VNioJsGkHj69q/MfM9N+n2op/gk2iIVA9iU5VDOYJTXjAZi6u913b +5WnaJKfeJ/y+huDACR8gPEcB82Mkf7ZoxGXe9HLOQNvw41W+qt9CbUq+rcPCfJrIl87 cAv104wweUGtZG9JTMRO9uImu+OgcyVLMRnQa/Q0Eue7D+Rdrwc+OJf0wTk7RqyERpD6 d11gwpPvOiQ95QbM4lxNaypfz0PTPz1nGmnnsH567mflcTzZlGjzUvMbbrVC/lYbqe0Q cX5Q== X-Gm-Message-State: ANhLgQ0eG9/TQE1lXsM+qAxi1CCeylr+ezoVBw6OOWV0/NVcafTf2Zd+ sk1+NZEbuwSzPdS+EfVip2zjeKuuUq66b2nmpvasNndf6WQ5xSevhNg/2Y4c/lbbt4cHTaEcCyd njCUjAFwPnij53M8= X-Received: by 2002:a5d:4488:: with SMTP id j8mr96058wrq.306.1584374879941; Mon, 16 Mar 2020 09:07:59 -0700 (PDT) X-Google-Smtp-Source: ADFU+vsZjM9PYbzB11qOc3TO2Yn7YNmN1hMQ0DyCXu0fd112HXe4vZCCLfxIEsZneEmH7TNa6quBUA== X-Received: by 2002:a5d:4488:: with SMTP id j8mr96041wrq.306.1584374879656; Mon, 16 Mar 2020 09:07:59 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 15/19] target/arm: Make m_helper.c optional via CONFIG_ARM_V7M Date: Mon, 16 Mar 2020 17:06:30 +0100 Message-Id: <20200316160634.3386-16-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 216.205.24.74 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Peter Maydell , Thomas Huth , kvm@vger.kernel.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , qemu-arm@nongnu.org, Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8"; text/plain; charset="utf-8" From: Thomas Huth We've already got the CONFIG_ARM_V7M switch, but it currently can not be disabled yet. The m_helper.c code should not be compiled into the binary if the switch is not enabled. We also have to provide some stubs in a separate file to make sure that we still can link the other code without CONFIG_ARM_V7M. Signed-off-by: Thomas Huth Message-Id: <20190903154810.27365-4-thuth@redhat.com> [PMD: add write_v7m_exception() stub when not using TCG, remove CONFIG_ARM_V7M=3Dy in default-configs/arm-softmmu.mak] Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson --- default-configs/arm-softmmu.mak | 6 ---- target/arm/cpu.h | 7 ++++ target/arm/m_helper-stub.c | 59 +++++++++++++++++++++++++++++++++ target/arm/Makefile.objs | 3 +- 4 files changed, 68 insertions(+), 7 deletions(-) create mode 100644 target/arm/m_helper-stub.c diff --git a/default-configs/arm-softmmu.mak b/default-configs/arm-softmmu.= mak index 511d74da58..7ae8006556 100644 --- a/default-configs/arm-softmmu.mak +++ b/default-configs/arm-softmmu.mak @@ -1,11 +1,5 @@ # Default configuration for arm-softmmu =20 -# CONFIG_SEMIHOSTING is always required on this architecture -CONFIG_SEMIHOSTING=3Dy - -# TODO: ARM_V7M is currently always required - make this more flexible! -CONFIG_ARM_V7M=3Dy - # CONFIG_PCI_DEVICES=3Dn # CONFIG_TEST_DEVICES=3Dn =20 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4ffd991b6f..84e14ce5a9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1278,7 +1278,14 @@ void pmu_init(ARMCPU *cpu); /* Write a new value to v7m.exception, thus transitioning into or out * of Handler mode; this may result in a change of active stack pointer. */ +#if !defined(CONFIG_TCG) +static inline void write_v7m_exception(CPUARMState *env, uint32_t new_exc) +{ + g_assert_not_reached(); +} +#else void write_v7m_exception(CPUARMState *env, uint32_t new_exc); +#endif =20 /* Map EL and handler into a PSTATE_MODE. */ static inline unsigned int aarch64_pstate_mode(unsigned int el, bool handl= er) diff --git a/target/arm/m_helper-stub.c b/target/arm/m_helper-stub.c new file mode 100644 index 0000000000..9316a9995b --- /dev/null +++ b/target/arm/m_helper-stub.c @@ -0,0 +1,59 @@ +/* + * ARM V7M related stubs. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/helper-proto.h" +#include "internals.h" + +void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) +{ + abort(); +} + +void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) +{ + abort(); +} + +uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg) +{ + abort(); +} + +void HELPER(v7m_msr)(CPUARMState *env, uint32_t maskreg, uint32_t val) +{ + abort(); +} + +uint32_t HELPER(v7m_tt)(CPUARMState *env, uint32_t addr, uint32_t op) +{ + abort(); +} + +void HELPER(v7m_preserve_fp_state)(CPUARMState *env) +{ + abort(); +} + +void write_v7m_exception(CPUARMState *env, uint32_t new_exc) +{ + abort(); +} + +void HELPER(v7m_vlldm)(CPUARMState *env, uint32_t fptr) +{ + abort(); +} + +void HELPER(v7m_vlstm)(CPUARMState *env, uint32_t fptr) +{ + abort(); +} + +ARMMMUIdx arm_v7m_mmu_idx_for_secstate(CPUARMState *env, bool secstate) +{ + abort(); +} diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index a0df58526b..993899d731 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -66,7 +66,8 @@ obj-y +=3D tlb_helper.o debug_helper.o obj-y +=3D translate.o op_helper.o obj-y +=3D crypto_helper.o obj-y +=3D iwmmxt_helper.o vec_helper.o neon_helper.o -obj-y +=3D m_helper.o +obj-$(CONFIG_ARM_V7M) +=3D m_helper.o +obj-$(call lnot,$(CONFIG_ARM_V7M)) +=3D m_helper-stub.o =20 obj-$(CONFIG_ARM_V4) +=3D cpu_v4.o obj-$(CONFIG_ARM_V5) +=3D cpu_v5.o --=20 2.21.1 From nobody Fri May 3 01:46:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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[83.59.163.96]) by smtp.gmail.com with ESMTPSA id o23sm553874wro.23.2020.03.16.09.08.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:08:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1584374892; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=MKKYJuqMYf+Eg6JeKj/mCe9oLeCOkHxBA5J4VpCzxs8=; b=ReduTQCNiNxNPuCFaS2x3o37CNyxUb9WW4SLYgWvb3/9/wGql6qQlOoi+CXfXPjMVa909p sbjavOG49rmGtuv5tFkIcvcqzNPcMUneiNYUy1r827tzAaFA1vRKE5YdP5ahHLFSODaY3p UHZNi7EZsU57Pi+NgDTiNHnrcNuuJks= X-MC-Unique: ZD3IcRPTM2WqvlWypaNIsw-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QDZzTTq3ryTffSf3hGL4Htu3pk7V1G5isiblOtOvRc0=; b=UdiNfy7Lri1vzsNQoSWA8H4N+zi6ZfMkNz0ConPJzSmmkOPo7D2CQ4RHDTSGY/ZhVK jRNcbi7tUOlBk8O84enGBmLIUWmDq7ooESdL/4QA/gW0YKM1xqJ7ERvWDebCnOLgRDvw LZVF61byUqNrqLysUvV73K/5EOFxFXK/Xa2QEwdHnGyErnuH1mjJtvbF1pI5WWLt1J0Y EmBHZRtUT+y1lRX2CpgpPl+SRXwePY14cSW61jq5fRMfMaj2xhNSUPB4Kzf5X7tVE8ry J0y7dor2jTwnwOtknzm3whHsN9k2CO5RrpqAGoAyQa8NluOX6Np6n+m4ZjH/LjH+mDUT pZrw== X-Gm-Message-State: ANhLgQ36Fx8x5WXOzmKkLEKMFJExL2QuuXeFlLG+kaoczV6IAEzWyGch xztKcrIVCVeXTja6R2j7+HAnJrTHl1jZ6L4b5V/J1G6MgjGCEZbNmiDOJm/kRjozJ6TdP8VivaS MfoNxz011U0RtKec= X-Received: by 2002:adf:ed85:: with SMTP id c5mr82542wro.41.1584374885380; Mon, 16 Mar 2020 09:08:05 -0700 (PDT) X-Google-Smtp-Source: ADFU+vtsr6U360K/odsCSzAC+mklkWuyn4n54yHB+Y2LZqv/r6/8LWfd199gkdpJvQ01dxn7hcEgzQ== X-Received: by 2002:adf:ed85:: with SMTP id c5mr82517wro.41.1584374885204; Mon, 16 Mar 2020 09:08:05 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 16/19] target/arm: Do not build TCG objects when TCG is off Date: Mon, 16 Mar 2020 17:06:31 +0100 Message-Id: <20200316160634.3386-17-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 216.205.24.74 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Peter Maydell , Thomas Huth , Samuel Ortiz , kvm@vger.kernel.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , qemu-arm@nongnu.org, Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8"; text/plain; charset="utf-8" From: Samuel Ortiz We can now safely turn all TCG dependent build off when CONFIG_TCG is off. This allows building ARM binaries with --disable-tcg. Signed-off-by: Samuel Ortiz [PMD: Heavily rebased during 18 months] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/arm/Makefile.objs | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/Makefile.objs b/target/arm/Makefile.objs index 993899d731..0178431549 100644 --- a/target/arm/Makefile.objs +++ b/target/arm/Makefile.objs @@ -60,8 +60,6 @@ ifeq ($(CONFIG_TCG),y) obj-$(CONFIG_SEMIHOSTING) +=3D arm-semi.o obj-$(call lnot,$(CONFIG_SEMIHOSTING)) +=3D arm-semi-stub.o =20 -endif # CONFIG_TCG - obj-y +=3D tlb_helper.o debug_helper.o obj-y +=3D translate.o op_helper.o obj-y +=3D crypto_helper.o @@ -80,3 +78,5 @@ obj-$(CONFIG_SOFTMMU) +=3D psci.o obj-$(TARGET_AARCH64) +=3D translate-a64.o helper-a64.o obj-$(TARGET_AARCH64) +=3D translate-sve.o sve_helper.o obj-$(TARGET_AARCH64) +=3D pauth_helper.o + +endif # CONFIG_TCG --=20 2.21.1 From nobody Fri May 3 01:46:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1584378315; cv=none; d=zohomail.com; s=zohoarc; b=k7FKShqniglDj5mUCxDv9LGPzGj04bzC7xyCj2KnmYNMnaNUDb4FmuFWKcOJQx0USytUdcIqMylRRT9mPOl5GgIlWOdZGS9uHmLJi0Hk/0j6ejw6mg3+R9qSacKyArI1eSMOeJJwwesN2qxv0ND8io2BfEvpck8P9W4kl+WvV7I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1584378315; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=TnhwsKKx2kZHqqWBEaWLP72fKQXGq24cvJF0rKa3l1k=; b=eEEXE4M54ksrTVrcTBELnk6Ye6asp84k0YeEBhm7Eg83AWU7q9gaFX97b04ZkhE4faAGGbi1cJEu0Bd1BbcPipI4AMjeRgV0C7H9256huzr5/34zIs51aGv0yZOafGc3DX3jYUopGiFeK6xPWjyUmNl2tIqJsDYC2YRZjGXbgY4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1584378315964236.34927994414704; Mon, 16 Mar 2020 10:05:15 -0700 (PDT) Received: from localhost ([::1]:43066 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jDtAw-0002dA-Ps for importer@patchew.org; Mon, 16 Mar 2020 13:05:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:55975) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jDsHo-0004hp-Rw for qemu-devel@nongnu.org; Mon, 16 Mar 2020 12:08:18 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jDsHn-0007em-Up for qemu-devel@nongnu.org; Mon, 16 Mar 2020 12:08:16 -0400 Received: from us-smtp-delivery-74.mimecast.com ([63.128.21.74]:52773) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jDsHn-0007Yf-Ql for qemu-devel@nongnu.org; Mon, 16 Mar 2020 12:08:15 -0400 Received: from mail-wm1-f69.google.com (mail-wm1-f69.google.com [209.85.128.69]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-280-jt4vyjXIPZaR540rWGHjZw-1; Mon, 16 Mar 2020 12:08:12 -0400 Received: by mail-wm1-f69.google.com with SMTP id a13so6012483wme.7 for ; Mon, 16 Mar 2020 09:08:12 -0700 (PDT) Received: from localhost.localdomain (96.red-83-59-163.dynamicip.rima-tde.net. [83.59.163.96]) by smtp.gmail.com with ESMTPSA id 127sm70683wmd.38.2020.03.16.09.08.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:08:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1584374895; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=TnhwsKKx2kZHqqWBEaWLP72fKQXGq24cvJF0rKa3l1k=; b=fZxFlwkpZ3Ny+FFNTuEj6W18Ym4xznZ3B8eCYs4IuPH6ZXyK1KAPvHHD6kD80XzWvVwY32 Ic2Wu7a8aDUP80csblJd9iOxyboVpS47pT3/vD6C6ZuxhRNljAmZy3KVqCyibrgieejKgH R1wJCdmtWjA84D5D/FvbBR0JzpPhCfw= X-MC-Unique: jt4vyjXIPZaR540rWGHjZw-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kMtlamo7Zl3wCiVgcr8iciiwh4khJI79F07LAInMKRc=; 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charset="utf-8"; text/plain; charset="utf-8" When building a KVM-only QEMU, the 'virt' machine is a good default :) Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index d0903d8544..8e801cd15f 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -1,5 +1,6 @@ config ARM_VIRT bool + default y if KVM imply PCI_DEVICES imply TEST_DEVICES imply VFIO_AMD_XGBE --=20 2.21.1 From nobody Fri May 3 01:46:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) client-ip=192.237.175.120; envelope-from=xen-devel-bounces@lists.xenproject.org; helo=lists.xenproject.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of lists.xenproject.org designates 192.237.175.120 as permitted sender) smtp.mailfrom=xen-devel-bounces@lists.xenproject.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; 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[83.59.163.96]) by smtp.gmail.com with ESMTPSA id x13sm268246wmj.5.2020.03.16.09.08.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:08:15 -0700 (PDT) X-Inumbo-ID: 5e2b5c62-67a0-11ea-b85d-12813bfff9fa DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1584374905; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=kzAY54Ug/Dgdb4+XERmlSJiZ/8IMgFtKzZJKBnbDjxY=; b=X4WKY88qS7QmAUGb7taUeEEVR0JziNXcDQXn/G988BDMIUUc+YhNwUkgj8OJx+lSnS2ssE wLCfcsBK6DvdwgE4gPYW1eXDqTB1d3KVEHQ2WpVCFM6f9JzDhxiZsj0csHgXpX17MELeCZ VnqvrK3dq77+nA1Ld3zkNPa+rwaiXDc= X-MC-Unique: kPtC9XoaOVmiXBHYGvYSNA-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Q9pxkDoDUc80lR6q2sbnb9Lu1UrGguk51WkG66GGoIk=; b=TrzSfNBr2YTu0bS5EuCpz7PlOSLOPWcGLfZIpjZh2mgTR1YmgItulPL+xBZSvl75z7 THexDSM01Az/af+f2slK9npY6YDqsrquUmySWwJYds56Vx18OXr/VSZcRPNrGEeMnKJd u9XpJ0f0pMkT6tAGnGRiulQOtiHnK8ANdKUaX0Q/96qu8XUKLJW6HO+Itd87x4GN6AmZ 90e2cE0cQwCIuz2bJtQKCUnO/h5J2uWRjTGhxDIFC8gtWY30BfMWgyYPgMOYgfdjhkpS UX52DxxXxkraIC/Z82xE/1Jiuud5sHy0pqaTAAsYOJJbC7iX8W0MuK6uElMC3yOABXd/ Ct5g== X-Gm-Message-State: ANhLgQ3xqX/sjbIUtp+YP6wUfdvGUlv7eaO1r5K/D3ZGth6IMJ/Eftwp 6djK9naLwzt8gL8qRtFIT9wFGvT7AcdsECax7X2eIeZWwbPioC0fRq+82jd18/u2/3DfVP9wJJl 3lTe9RgPiNde6iAl5u5SSh5d/lQs= X-Received: by 2002:a50:e44a:: with SMTP id e10mr721634edm.210.1584374898021; Mon, 16 Mar 2020 09:08:18 -0700 (PDT) X-Google-Smtp-Source: ADFU+vtucDPtYCUUmNKo1v786732XgsbrhpkRJ66ECnTqKEicI6pa/tNzUTcvXKFSS8tLcL/QhoQsA== X-Received: by 2002:adf:b3d6:: with SMTP id x22mr99071wrd.242.1584374896425; Mon, 16 Mar 2020 09:08:16 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Date: Mon, 16 Mar 2020 17:06:33 +0100 Message-Id: <20200316160634.3386-19-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Subject: [Xen-devel] [PATCH v3 18/19] hw/arm: Do not build to 'virt' machine on Xen X-BeenThere: xen-devel@lists.xenproject.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Xen developer discussion List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Peter Maydell , Thomas Huth , Stefano Stabellini , kvm@vger.kernel.org, Paul Durrant , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , qemu-arm@nongnu.org, xen-devel@lists.xenproject.org, Anthony Perard , Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Errors-To: xen-devel-bounces@lists.xenproject.org Sender: "Xen-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Xen on ARM does not use QEMU machines [*]. Disable the 'virt' machine there to avoid odd errors such: CC i386-softmmu/hw/cpu/a15mpcore.o hw/cpu/a15mpcore.c:28:10: fatal error: kvm_arm.h: No such file or directo= ry [*] https://wiki.xenproject.org/wiki/Xen_ARM_with_Virtualization_Extensions= #Use_of_qemu-system-i386_on_ARM Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- Cc: Stefano Stabellini Cc: Anthony Perard Cc: Paul Durrant Cc: xen-devel@lists.xenproject.org --- hw/arm/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 8e801cd15f..69a8e30125 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -1,5 +1,6 @@ config ARM_VIRT bool + depends on !XEN default y if KVM imply PCI_DEVICES imply TEST_DEVICES --=20 2.21.1 _______________________________________________ Xen-devel mailing list Xen-devel@lists.xenproject.org https://lists.xenproject.org/mailman/listinfo/xen-devel From nobody Fri May 3 01:46:11 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1584380018; cv=none; d=zohomail.com; s=zohoarc; b=HCOZj67yIzNUoOsc15bXxMlzChUwsi769GkueRqCvmSgdwQyTJ2kn9MNZTMj29WilPd7Ba4VGyO/XU/hDpYSX58wsRmL1sloJR4/BItaBZrDaX+YuesKNPxE5Qk0lDOXv6Pz1/JuAoss4wEFMZwliy6XRQnnCRPrKbZ+EKokomQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1584380018; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/ssNU1W6JmcL4kU4cWyqsOdXjUb4r7kWMVEvWGvo+2k=; b=enxc0Jq/zsfNIULf4BCxrBU1zVm/ZjZ+cDylsX1kVkn7MB4LEkM3p4QlWsOPUunsuCGJE2dgCUhRCIqTPfQ1dlK9uBd+aDNksYCs0wUMQ7JTla5TsFnq7x6Z5gtPJC8SA5qZDHDjrT0awrYP/wC6Xz2LNK/4b3tSp9k5d1nDEjk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1584380018687246.92392696387378; Mon, 16 Mar 2020 10:33:38 -0700 (PDT) Received: from localhost ([::1]:44382 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jDtcP-0002S5-Go for importer@patchew.org; Mon, 16 Mar 2020 13:33:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:56448) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jDsI3-0004nU-3X for qemu-devel@nongnu.org; Mon, 16 Mar 2020 12:08:33 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jDsI0-0001GW-Mo for qemu-devel@nongnu.org; Mon, 16 Mar 2020 12:08:30 -0400 Received: from us-smtp-delivery-74.mimecast.com ([216.205.24.74]:25178) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jDsI0-0001Ct-HI for qemu-devel@nongnu.org; Mon, 16 Mar 2020 12:08:28 -0400 Received: from mail-wr1-f72.google.com (mail-wr1-f72.google.com [209.85.221.72]) (Using TLS) by relay.mimecast.com with ESMTP id us-mta-119-Raf75YFQMQS1G56dk9AvEA-1; Mon, 16 Mar 2020 12:08:23 -0400 Received: by mail-wr1-f72.google.com with SMTP id b11so9234553wru.21 for ; Mon, 16 Mar 2020 09:08:23 -0700 (PDT) Received: from localhost.localdomain (96.red-83-59-163.dynamicip.rima-tde.net. [83.59.163.96]) by smtp.gmail.com with ESMTPSA id v10sm170121wml.44.2020.03.16.09.08.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 Mar 2020 09:08:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1584374908; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=/ssNU1W6JmcL4kU4cWyqsOdXjUb4r7kWMVEvWGvo+2k=; b=Z+jKRamDsUkdz9JxgzcPAcWioKB509NIPYn6vFLnJXDxS+LLazFrLT9JJSoHWoD7G/S5OW /HoDYJdYoVWT7a8lSEflPrBfab/4ULe5Q81hMlLIpRNRZk1slQyNjYM+JU4wPT2GCkWGfP rWedeo8738mN2rbDJ3xeiJdlZYGkza8= X-MC-Unique: Raf75YFQMQS1G56dk9AvEA-1 X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=N7+HmyV0D4vFSs4ZL/u4BopejDTWdgLZjfeVHLnQ9M4=; b=tA/1euOJkXSJZTSwNDwaSzIL1CpAg1Zqz3qcxQSQKM8H3pkqFNaHYGTGxnuaKGUiOh c7jG82eG6M2MZRX9Nkl1kofcX7nuAgTfxwG09bk5DxsOtPCERnGff2a7PRW/W1HaeSPe q1Ez2GybcKBp3lvrObmO0CzTnEg3JqL33s0bDSdmsBFqIefFsPPcQcsU5QfVwin5TUXl Y8Ptu2Dggs5aq5MIYxnBx2/Y3HWuQjmzxc859XFJxWFp5vdkOdLXLFe25betnxtc9SQ0 5GxjTEgWR853n4fPPg+PEVpRFA8RNeL3Vn8nK8UJwCtjKsEveDxJ8EBa6ROa6StHnoCv W9DQ== X-Gm-Message-State: ANhLgQ0KVS6aQjUGppRIduo5eS5wXs3C1XoMrRBDhJy4ixvQS9Q1ECMB 8NqqZUAa8SY3NO4mvzR+xoO/pC84QnLAtejnJDkJFqMapcCaXZ1tvyyjdoByJCgZfp6j59o5Wrp 3PFWCJogoJ8KtCDA= X-Received: by 2002:a1c:984a:: with SMTP id a71mr29937830wme.185.1584374902202; Mon, 16 Mar 2020 09:08:22 -0700 (PDT) X-Google-Smtp-Source: ADFU+vssyfrGmsyQfMixG6XPmVZD6SHgaog1D2LjTAVp2uFXc9h0dhfPsS644yu8c8+ZyHwycJ4JHQ== X-Received: by 2002:a1c:984a:: with SMTP id a71mr29937801wme.185.1584374901937; Mon, 16 Mar 2020 09:08:21 -0700 (PDT) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Subject: [PATCH v3 19/19] .travis.yml: Add a KVM-only Aarch64 job Date: Mon, 16 Mar 2020 17:06:34 +0100 Message-Id: <20200316160634.3386-20-philmd@redhat.com> X-Mailer: git-send-email 2.21.1 In-Reply-To: <20200316160634.3386-1-philmd@redhat.com> References: <20200316160634.3386-1-philmd@redhat.com> MIME-Version: 1.0 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 216.205.24.74 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Fam Zheng , Peter Maydell , Thomas Huth , kvm@vger.kernel.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= , Richard Henderson , qemu-arm@nongnu.org, Paolo Bonzini , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8"; text/plain; charset="utf-8" Add a job to build QEMU on Aarch64 with TCG disabled, so this configuration won't bitrot over time. Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- Job ran for 13 min 1 sec https://travis-ci.org/github/philmd/qemu/jobs/663122258 --- .travis.yml | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/.travis.yml b/.travis.yml index b92798ac3b..ea3c0df185 100644 --- a/.travis.yml +++ b/.travis.yml @@ -450,6 +450,38 @@ jobs: - TEST_CMD=3D"make check check-tcg V=3D1" - CONFIG=3D"--disable-containers --target-list=3D${MAIN_SOFTMMU_TA= RGETS}" =20 + - name: "[aarch64] GCC check (KVM)" + arch: arm64 + dist: xenial + addons: + apt_packages: + - libaio-dev + - libattr1-dev + - libcap-ng-dev + - libgcrypt20-dev + - libgnutls28-dev + - libiscsi-dev + - liblttng-ust-dev + - libnfs-dev + - libnss3-dev + - libpixman-1-dev + - libpng-dev + - librados-dev + - libseccomp-dev + - liburcu-dev + - libusb-1.0-0-dev + - libvdeplug-dev + - libvte-2.91-dev + # Tests dependencies + - genisoimage + env: + - CONFIG=3D"--disable-containers --disable-tcg --enable-kvm --enab= le-fdt --disable-tools" + - TEST_CMD=3D"make check-unit" + script: + # Only select the 'virt' machine. + - echo CONFIG_ARM_VIRT=3Dy > ${SRC_DIR}/default-configs/aarch64-so= ftmmu.mak + - make -j3 && travis_retry ${TEST_CMD} + - name: "[ppc64] GCC check-tcg" arch: ppc64le dist: xenial --=20 2.21.1