From nobody Mon Apr 29 16:34:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1584072563; cv=none; d=zohomail.com; s=zohoarc; b=eR9XVrgUzlrOAl/BaggF9/2oOdLIH27EHpG37JAl7546J38B9AGuDb1UprKX+/nmmtRMOcuOth/ZxnjqXJxTt5GfLMs0nZoSFAH+2WdSQacFwd8c/9i9JFdvK0m1uzUposXvgVTVTFQipyemXJsISxMg6GDuRHV57ldm9t1V7OA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1584072563; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wPwwrK7KLXse9EG1jyUzlWZCyMceh0sZyQEepL95L9I=; b=NRSMd0MRMNDrQeOvKPVWMBoITac3bAacTCXtgybQbi5HkPt/HRA8D1QyqhXmCfP79BMderd7wfKwSweTyvZp9Wh31mR4ZPMiyVlJlGVrYgxHeHCIzBwvagdRcqVEzDNYeEqyRAG4vGoP82eUe2DkJHR6WQQcarzcZapISejGrIw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1584072563475149.9502810455972; Thu, 12 Mar 2020 21:09:23 -0700 (PDT) Received: from localhost ([::1]:53558 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jCbdS-0008R7-Eq for importer@patchew.org; Fri, 13 Mar 2020 00:09:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44220) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jCba8-0003Po-JT for qemu-devel@nongnu.org; Fri, 13 Mar 2020 00:05:59 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jCba6-00076g-5a for qemu-devel@nongnu.org; Fri, 13 Mar 2020 00:05:56 -0400 Received: from bilbo.ozlabs.org ([203.11.71.1]:49169 helo=ozlabs.org) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jCba5-0006rN-Ah; Fri, 13 Mar 2020 00:05:54 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 48dsYj1YFSz9sRN; Fri, 13 Mar 2020 15:05:45 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1584072345; bh=1xtkFiwCdluo8myE4MDdXsPGwwZAwQarkL2wO8T60L8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=I0zI0sHeZW8FZ0eCvPB2VTrCJ5P2N1Ugjm1QkOGRbuDv08M1Q8VpwNNpchjmyavF3 3dAwps6uTKe8JHKVNldmsGUChQcnnGiXJ3o8Q6O+DMNeUaJb96HooG5aOgpC+QQ097 tGEsKG5snqXCqiRg2GKLYFutEx5kDIo8YClLdXIg= From: David Gibson To: groug@kaod.org, clg@kaod.org, philmd@redhat.com Subject: [PATCH 1/4] spapr: Move creation of ibm, dynamic-reconfiguration-memory dt node Date: Fri, 13 Mar 2020 15:05:36 +1100 Message-Id: <20200313040539.819138-2-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200313040539.819138-1-david@gibson.dropbear.id.au> References: <20200313040539.819138-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 203.11.71.1 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) Content-Type: text/plain; charset="utf-8" Currently this node with information about hotpluggable memory is created from spapr_dt_cas_updates(). But that's just a hangover from when we created it only as a diff to the device tree at CAS time. Now that we fully rebuild the DT as CAS time, it makes more sense to create this along with the rest of the memory information in the device tree. So, move it to spapr_populate_memory(). The patch is huge, but it's nearly all just code motion. Signed-off-by: David Gibson Reviewed-by: Greg Kurz --- hw/ppc/spapr.c | 512 +++++++++++++++++++++++++------------------------ 1 file changed, 257 insertions(+), 255 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 64bc8b83e9..66289ffef5 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -341,257 +341,6 @@ static int spapr_populate_memory_node(void *fdt, int = nodeid, hwaddr start, return off; } =20 -static int spapr_populate_memory(SpaprMachineState *spapr, void *fdt) -{ - MachineState *machine =3D MACHINE(spapr); - hwaddr mem_start, node_size; - int i, nb_nodes =3D machine->numa_state->num_nodes; - NodeInfo *nodes =3D machine->numa_state->nodes; - - for (i =3D 0, mem_start =3D 0; i < nb_nodes; ++i) { - if (!nodes[i].node_mem) { - continue; - } - if (mem_start >=3D machine->ram_size) { - node_size =3D 0; - } else { - node_size =3D nodes[i].node_mem; - if (node_size > machine->ram_size - mem_start) { - node_size =3D machine->ram_size - mem_start; - } - } - if (!mem_start) { - /* spapr_machine_init() checks for rma_size <=3D node0_size - * already */ - spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); - mem_start +=3D spapr->rma_size; - node_size -=3D spapr->rma_size; - } - for ( ; node_size; ) { - hwaddr sizetmp =3D pow2floor(node_size); - - /* mem_start !=3D 0 here */ - if (ctzl(mem_start) < ctzl(sizetmp)) { - sizetmp =3D 1ULL << ctzl(mem_start); - } - - spapr_populate_memory_node(fdt, i, mem_start, sizetmp); - node_size -=3D sizetmp; - mem_start +=3D sizetmp; - } - } - - return 0; -} - -static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, - SpaprMachineState *spapr) -{ - MachineState *ms =3D MACHINE(spapr); - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - CPUPPCState *env =3D &cpu->env; - PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cs); - int index =3D spapr_get_vcpu_id(cpu); - uint32_t segs[] =3D {cpu_to_be32(28), cpu_to_be32(40), - 0xffffffff, 0xffffffff}; - uint32_t tbfreq =3D kvm_enabled() ? kvmppc_get_tbfreq() - : SPAPR_TIMEBASE_FREQ; - uint32_t cpufreq =3D kvm_enabled() ? kvmppc_get_clockfreq() : 10000000= 00; - uint32_t page_sizes_prop[64]; - size_t page_sizes_prop_size; - unsigned int smp_threads =3D ms->smp.threads; - uint32_t vcpus_per_socket =3D smp_threads * ms->smp.cores; - uint32_t pft_size_prop[] =3D {0, cpu_to_be32(spapr->htab_shift)}; - int compat_smt =3D MIN(smp_threads, ppc_compat_max_vthreads(cpu)); - SpaprDrc *drc; - int drc_index; - uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; - int i; - - drc =3D spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); - if (drc) { - drc_index =3D spapr_drc_index(drc); - _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)= )); - } - - _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); - _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); - - _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))= ); - _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", - env->dcache_line_size))); - _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", - env->dcache_line_size))); - _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", - env->icache_line_size))); - _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", - env->icache_line_size))); - - if (pcc->l1_dcache_size) { - _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", - pcc->l1_dcache_size))); - } else { - warn_report("Unknown L1 dcache size for cpu"); - } - if (pcc->l1_icache_size) { - _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", - pcc->l1_icache_size))); - } else { - warn_report("Unknown L1 icache size for cpu"); - } - - _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); - _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); - _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_= size))); - _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->= slb_size))); - _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); - _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); - - if (env->spr_cb[SPR_PURR].oea_read) { - _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); - } - if (env->spr_cb[SPR_SPURR].oea_read) { - _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); - } - - if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { - _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", - segs, sizeof(segs)))); - } - - /* Advertise VSX (vector extensions) if available - * 1 =3D=3D VMX / Altivec available - * 2 =3D=3D VSX available - * - * Only CPUs for which we create core types in spapr_cpu_core.c - * are possible, and all of those have VMX */ - if (spapr_get_cap(spapr, SPAPR_CAP_VSX) !=3D 0) { - _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); - } else { - _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); - } - - /* Advertise DFP (Decimal Floating Point) if available - * 0 / no property =3D=3D no DFP - * 1 =3D=3D DFP available */ - if (spapr_get_cap(spapr, SPAPR_CAP_DFP) !=3D 0) { - _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); - } - - page_sizes_prop_size =3D ppc_create_page_sizes_prop(cpu, page_sizes_pr= op, - sizeof(page_sizes_pr= op)); - if (page_sizes_prop_size) { - _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", - page_sizes_prop, page_sizes_prop_size))); - } - - spapr_populate_pa_features(spapr, cpu, fdt, offset); - - _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", - cs->cpu_index / vcpus_per_socket))); - - _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", - pft_size_prop, sizeof(pft_size_prop)))); - - if (ms->numa_state->num_nodes > 1) { - _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); - } - - _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); - - if (pcc->radix_page_info) { - for (i =3D 0; i < pcc->radix_page_info->count; i++) { - radix_AP_encodings[i] =3D - cpu_to_be32(pcc->radix_page_info->entries[i]); - } - _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", - radix_AP_encodings, - pcc->radix_page_info->count * - sizeof(radix_AP_encodings[0])))); - } - - /* - * We set this property to let the guest know that it can use the large - * decrementer and its width in bits. - */ - if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) !=3D SPAPR_CAP_O= FF) - _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", - pcc->lrg_decr_bits))); -} - -static void spapr_populate_cpus_dt_node(void *fdt, SpaprMachineState *spap= r) -{ - CPUState **rev; - CPUState *cs; - int n_cpus; - int cpus_offset; - char *nodename; - int i; - - cpus_offset =3D fdt_add_subnode(fdt, 0, "cpus"); - _FDT(cpus_offset); - _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); - _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); - - /* - * We walk the CPUs in reverse order to ensure that CPU DT nodes - * created by fdt_add_subnode() end up in the right order in FDT - * for the guest kernel the enumerate the CPUs correctly. - * - * The CPU list cannot be traversed in reverse order, so we need - * to do extra work. - */ - n_cpus =3D 0; - rev =3D NULL; - CPU_FOREACH(cs) { - rev =3D g_renew(CPUState *, rev, n_cpus + 1); - rev[n_cpus++] =3D cs; - } - - for (i =3D n_cpus - 1; i >=3D 0; i--) { - CPUState *cs =3D rev[i]; - PowerPCCPU *cpu =3D POWERPC_CPU(cs); - int index =3D spapr_get_vcpu_id(cpu); - DeviceClass *dc =3D DEVICE_GET_CLASS(cs); - int offset; - - if (!spapr_is_thread0_in_vcore(spapr, cpu)) { - continue; - } - - nodename =3D g_strdup_printf("%s@%x", dc->fw_name, index); - offset =3D fdt_add_subnode(fdt, cpus_offset, nodename); - g_free(nodename); - _FDT(offset); - spapr_populate_cpu_dt(cs, fdt, offset, spapr); - } - - g_free(rev); -} - -static int spapr_rng_populate_dt(void *fdt) -{ - int node; - int ret; - - node =3D qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); - if (node <=3D 0) { - return -1; - } - ret =3D fdt_setprop_string(fdt, node, "device_type", - "ibm,platform-facilities"); - ret |=3D fdt_setprop_cell(fdt, node, "#address-cells", 0x1); - ret |=3D fdt_setprop_cell(fdt, node, "#size-cells", 0x0); - - node =3D fdt_add_subnode(fdt, node, "ibm,random-v1"); - if (node <=3D 0) { - return -1; - } - ret |=3D fdt_setprop_string(fdt, node, "compatible", "ibm,random"); - - return ret ? -1 : 0; -} - static uint32_t spapr_pc_dimm_node(MemoryDeviceInfoList *list, ram_addr_t = addr) { MemoryDeviceInfoList *info; @@ -877,14 +626,51 @@ static int spapr_populate_drconf_memory(SpaprMachineS= tate *spapr, void *fdt) return ret; } =20 -static int spapr_dt_cas_updates(SpaprMachineState *spapr, void *fdt, - SpaprOptionVector *ov5_updates) +static int spapr_populate_memory(SpaprMachineState *spapr, void *fdt) { + MachineState *machine =3D MACHINE(spapr); SpaprMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); - int ret =3D 0, offset; + hwaddr mem_start, node_size; + int i, nb_nodes =3D machine->numa_state->num_nodes; + NodeInfo *nodes =3D machine->numa_state->nodes; + + for (i =3D 0, mem_start =3D 0; i < nb_nodes; ++i) { + if (!nodes[i].node_mem) { + continue; + } + if (mem_start >=3D machine->ram_size) { + node_size =3D 0; + } else { + node_size =3D nodes[i].node_mem; + if (node_size > machine->ram_size - mem_start) { + node_size =3D machine->ram_size - mem_start; + } + } + if (!mem_start) { + /* spapr_machine_init() checks for rma_size <=3D node0_size + * already */ + spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); + mem_start +=3D spapr->rma_size; + node_size -=3D spapr->rma_size; + } + for ( ; node_size; ) { + hwaddr sizetmp =3D pow2floor(node_size); + + /* mem_start !=3D 0 here */ + if (ctzl(mem_start) < ctzl(sizetmp)) { + sizetmp =3D 1ULL << ctzl(mem_start); + } + + spapr_populate_memory_node(fdt, i, mem_start, sizetmp); + node_size -=3D sizetmp; + mem_start +=3D sizetmp; + } + } =20 /* Generate ibm,dynamic-reconfiguration-memory node if required */ - if (spapr_ovec_test(ov5_updates, OV5_DRCONF_MEMORY)) { + if (spapr_ovec_test(spapr->ov5_cas, OV5_DRCONF_MEMORY)) { + int ret; + g_assert(smc->dr_lmb_enabled); ret =3D spapr_populate_drconf_memory(spapr, fdt); if (ret) { @@ -892,6 +678,222 @@ static int spapr_dt_cas_updates(SpaprMachineState *sp= apr, void *fdt, } } =20 + return 0; +} + +static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, + SpaprMachineState *spapr) +{ + MachineState *ms =3D MACHINE(spapr); + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + CPUPPCState *env =3D &cpu->env; + PowerPCCPUClass *pcc =3D POWERPC_CPU_GET_CLASS(cs); + int index =3D spapr_get_vcpu_id(cpu); + uint32_t segs[] =3D {cpu_to_be32(28), cpu_to_be32(40), + 0xffffffff, 0xffffffff}; + uint32_t tbfreq =3D kvm_enabled() ? kvmppc_get_tbfreq() + : SPAPR_TIMEBASE_FREQ; + uint32_t cpufreq =3D kvm_enabled() ? kvmppc_get_clockfreq() : 10000000= 00; + uint32_t page_sizes_prop[64]; + size_t page_sizes_prop_size; + unsigned int smp_threads =3D ms->smp.threads; + uint32_t vcpus_per_socket =3D smp_threads * ms->smp.cores; + uint32_t pft_size_prop[] =3D {0, cpu_to_be32(spapr->htab_shift)}; + int compat_smt =3D MIN(smp_threads, ppc_compat_max_vthreads(cpu)); + SpaprDrc *drc; + int drc_index; + uint32_t radix_AP_encodings[PPC_PAGE_SIZES_MAX_SZ]; + int i; + + drc =3D spapr_drc_by_id(TYPE_SPAPR_DRC_CPU, index); + if (drc) { + drc_index =3D spapr_drc_index(drc); + _FDT((fdt_setprop_cell(fdt, offset, "ibm,my-drc-index", drc_index)= )); + } + + _FDT((fdt_setprop_cell(fdt, offset, "reg", index))); + _FDT((fdt_setprop_string(fdt, offset, "device_type", "cpu"))); + + _FDT((fdt_setprop_cell(fdt, offset, "cpu-version", env->spr[SPR_PVR]))= ); + _FDT((fdt_setprop_cell(fdt, offset, "d-cache-block-size", + env->dcache_line_size))); + _FDT((fdt_setprop_cell(fdt, offset, "d-cache-line-size", + env->dcache_line_size))); + _FDT((fdt_setprop_cell(fdt, offset, "i-cache-block-size", + env->icache_line_size))); + _FDT((fdt_setprop_cell(fdt, offset, "i-cache-line-size", + env->icache_line_size))); + + if (pcc->l1_dcache_size) { + _FDT((fdt_setprop_cell(fdt, offset, "d-cache-size", + pcc->l1_dcache_size))); + } else { + warn_report("Unknown L1 dcache size for cpu"); + } + if (pcc->l1_icache_size) { + _FDT((fdt_setprop_cell(fdt, offset, "i-cache-size", + pcc->l1_icache_size))); + } else { + warn_report("Unknown L1 icache size for cpu"); + } + + _FDT((fdt_setprop_cell(fdt, offset, "timebase-frequency", tbfreq))); + _FDT((fdt_setprop_cell(fdt, offset, "clock-frequency", cpufreq))); + _FDT((fdt_setprop_cell(fdt, offset, "slb-size", cpu->hash64_opts->slb_= size))); + _FDT((fdt_setprop_cell(fdt, offset, "ibm,slb-size", cpu->hash64_opts->= slb_size))); + _FDT((fdt_setprop_string(fdt, offset, "status", "okay"))); + _FDT((fdt_setprop(fdt, offset, "64-bit", NULL, 0))); + + if (env->spr_cb[SPR_PURR].oea_read) { + _FDT((fdt_setprop_cell(fdt, offset, "ibm,purr", 1))); + } + if (env->spr_cb[SPR_SPURR].oea_read) { + _FDT((fdt_setprop_cell(fdt, offset, "ibm,spurr", 1))); + } + + if (ppc_hash64_has(cpu, PPC_HASH64_1TSEG)) { + _FDT((fdt_setprop(fdt, offset, "ibm,processor-segment-sizes", + segs, sizeof(segs)))); + } + + /* Advertise VSX (vector extensions) if available + * 1 =3D=3D VMX / Altivec available + * 2 =3D=3D VSX available + * + * Only CPUs for which we create core types in spapr_cpu_core.c + * are possible, and all of those have VMX */ + if (spapr_get_cap(spapr, SPAPR_CAP_VSX) !=3D 0) { + _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 2))); + } else { + _FDT((fdt_setprop_cell(fdt, offset, "ibm,vmx", 1))); + } + + /* Advertise DFP (Decimal Floating Point) if available + * 0 / no property =3D=3D no DFP + * 1 =3D=3D DFP available */ + if (spapr_get_cap(spapr, SPAPR_CAP_DFP) !=3D 0) { + _FDT((fdt_setprop_cell(fdt, offset, "ibm,dfp", 1))); + } + + page_sizes_prop_size =3D ppc_create_page_sizes_prop(cpu, page_sizes_pr= op, + sizeof(page_sizes_pr= op)); + if (page_sizes_prop_size) { + _FDT((fdt_setprop(fdt, offset, "ibm,segment-page-sizes", + page_sizes_prop, page_sizes_prop_size))); + } + + spapr_populate_pa_features(spapr, cpu, fdt, offset); + + _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", + cs->cpu_index / vcpus_per_socket))); + + _FDT((fdt_setprop(fdt, offset, "ibm,pft-size", + pft_size_prop, sizeof(pft_size_prop)))); + + if (ms->numa_state->num_nodes > 1) { + _FDT(spapr_fixup_cpu_numa_dt(fdt, offset, cpu)); + } + + _FDT(spapr_fixup_cpu_smt_dt(fdt, offset, cpu, compat_smt)); + + if (pcc->radix_page_info) { + for (i =3D 0; i < pcc->radix_page_info->count; i++) { + radix_AP_encodings[i] =3D + cpu_to_be32(pcc->radix_page_info->entries[i]); + } + _FDT((fdt_setprop(fdt, offset, "ibm,processor-radix-AP-encodings", + radix_AP_encodings, + pcc->radix_page_info->count * + sizeof(radix_AP_encodings[0])))); + } + + /* + * We set this property to let the guest know that it can use the large + * decrementer and its width in bits. + */ + if (spapr_get_cap(spapr, SPAPR_CAP_LARGE_DECREMENTER) !=3D SPAPR_CAP_O= FF) + _FDT((fdt_setprop_u32(fdt, offset, "ibm,dec-bits", + pcc->lrg_decr_bits))); +} + +static void spapr_populate_cpus_dt_node(void *fdt, SpaprMachineState *spap= r) +{ + CPUState **rev; + CPUState *cs; + int n_cpus; + int cpus_offset; + char *nodename; + int i; + + cpus_offset =3D fdt_add_subnode(fdt, 0, "cpus"); + _FDT(cpus_offset); + _FDT((fdt_setprop_cell(fdt, cpus_offset, "#address-cells", 0x1))); + _FDT((fdt_setprop_cell(fdt, cpus_offset, "#size-cells", 0x0))); + + /* + * We walk the CPUs in reverse order to ensure that CPU DT nodes + * created by fdt_add_subnode() end up in the right order in FDT + * for the guest kernel the enumerate the CPUs correctly. + * + * The CPU list cannot be traversed in reverse order, so we need + * to do extra work. + */ + n_cpus =3D 0; + rev =3D NULL; + CPU_FOREACH(cs) { + rev =3D g_renew(CPUState *, rev, n_cpus + 1); + rev[n_cpus++] =3D cs; + } + + for (i =3D n_cpus - 1; i >=3D 0; i--) { + CPUState *cs =3D rev[i]; + PowerPCCPU *cpu =3D POWERPC_CPU(cs); + int index =3D spapr_get_vcpu_id(cpu); + DeviceClass *dc =3D DEVICE_GET_CLASS(cs); + int offset; + + if (!spapr_is_thread0_in_vcore(spapr, cpu)) { + continue; + } + + nodename =3D g_strdup_printf("%s@%x", dc->fw_name, index); + offset =3D fdt_add_subnode(fdt, cpus_offset, nodename); + g_free(nodename); + _FDT(offset); + spapr_populate_cpu_dt(cs, fdt, offset, spapr); + } + + g_free(rev); +} + +static int spapr_rng_populate_dt(void *fdt) +{ + int node; + int ret; + + node =3D qemu_fdt_add_subnode(fdt, "/ibm,platform-facilities"); + if (node <=3D 0) { + return -1; + } + ret =3D fdt_setprop_string(fdt, node, "device_type", + "ibm,platform-facilities"); + ret |=3D fdt_setprop_cell(fdt, node, "#address-cells", 0x1); + ret |=3D fdt_setprop_cell(fdt, node, "#size-cells", 0x0); + + node =3D fdt_add_subnode(fdt, node, "ibm,random-v1"); + if (node <=3D 0) { + return -1; + } + ret |=3D fdt_setprop_string(fdt, node, "compatible", "ibm,random"); + + return ret ? -1 : 0; +} + +static int spapr_dt_cas_updates(SpaprMachineState *spapr, void *fdt, + SpaprOptionVector *ov5_updates) +{ + int offset; + offset =3D fdt_path_offset(fdt, "/chosen"); if (offset < 0) { offset =3D fdt_add_subnode(fdt, 0, "chosen"); --=20 2.24.1 From nobody Mon Apr 29 16:34:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1584072420; cv=none; d=zohomail.com; s=zohoarc; b=RIXfnnADSTbQ1PXcMZ4IeR4O0Bo8FM3mutGVctRw8KhFMfVal34GHmILzLflJdZ45bsAYxP1gJ/Oq6EyxFuouxza7VBiLcab60PEXbFvBcddu8y+9VI2kTANvYn+djNgzheTnTaLC/zoevOEaLdn7KI5/cC5REMEdY2lTNgDxKA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1584072420; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Fri, 13 Mar 2020 00:05:55 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:34433) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jCba5-0006rh-4P; Fri, 13 Mar 2020 00:05:54 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 48dsYj2Hb5z9sSV; Fri, 13 Mar 2020 15:05:45 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1584072345; bh=lA1CWq6sTkYH0ckLD0jbjNno+xackfvWz9OnWzmHeU4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Gfs3wPNxtW/ijFL365hm7QA99qkUsyyvuShTxzbSp9UOZpQwIC0u+dR1K6Zr5VGoa ERxcdun0ujwsuMTjnZtKBwOjhC0XV6Qr8ZeZDxFYFHud/H2p2xgakJ1FPLEJoWgmwi 2ja21SIfHd1MOTbjebS3U8KIkaM1zRmRc8I2paR8= From: David Gibson To: groug@kaod.org, clg@kaod.org, philmd@redhat.com Subject: [PATCH 2/4] spapr: Move creation of ibm,architecture-vec-5 property Date: Fri, 13 Mar 2020 15:05:37 +1100 Message-Id: <20200313040539.819138-3-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200313040539.819138-1-david@gibson.dropbear.id.au> References: <20200313040539.819138-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Computed bodyhash is different from the expected one) Content-Type: text/plain; charset="utf-8" This is currently called from spapr_dt_cas_updates() which is a hang over from when we created this only as a diff to the DT at CAS time. Now that we fully rebuild the DT at CAS time, just create it alon with the rest of the properties in /chosen. Signed-off-by: David Gibson Reviewed-by: Greg Kurz --- hw/ppc/spapr.c | 26 +++----------------------- 1 file changed, 3 insertions(+), 23 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 66289ffef5..fc28d9df25 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -889,22 +889,6 @@ static int spapr_rng_populate_dt(void *fdt) return ret ? -1 : 0; } =20 -static int spapr_dt_cas_updates(SpaprMachineState *spapr, void *fdt, - SpaprOptionVector *ov5_updates) -{ - int offset; - - offset =3D fdt_path_offset(fdt, "/chosen"); - if (offset < 0) { - offset =3D fdt_add_subnode(fdt, 0, "chosen"); - if (offset < 0) { - return offset; - } - } - return spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, - "ibm,architecture-vec-5"); -} - static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) { MachineState *ms =3D MACHINE(spapr); @@ -1115,6 +1099,9 @@ static void spapr_dt_chosen(SpaprMachineState *spapr,= void *fdt) =20 spapr_dt_ov5_platform_support(spapr, fdt, chosen); =20 + _FDT(spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, + "ibm,architecture-vec-5")); + g_free(stdout_path); g_free(bootlist); } @@ -1263,13 +1250,6 @@ void *spapr_build_fdt(SpaprMachineState *spapr, bool= reset, size_t space) } } =20 - /* ibm,client-architecture-support updates */ - ret =3D spapr_dt_cas_updates(spapr, fdt, spapr->ov5_cas); - if (ret < 0) { - error_report("couldn't setup CAS properties fdt"); - exit(1); - } - if (smc->dr_phb_enabled) { ret =3D spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_PHB); if (ret < 0) { --=20 2.24.1 From nobody Mon Apr 29 16:34:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1584072498; cv=none; d=zohomail.com; s=zohoarc; b=ANFjITVh1t2unYGRCztuENr2XA6rMQq6JcUdIG78pcpvMyuabz4UgWFMzWAVwag2xYS1GGX9tNF6OLIHwu/xLR1kOYuM+lmJsr9iWwmOfAu3q8wEieafiW4nF9V8TV0eacQhdwlLQp2mnGyH8WkPobrwzMvdqHTu0FRiXaRUXZE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1584072498; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4h4GTVTjd4PD+IJNVD8mN+HhxUf25lsIADdLhT/uA4E=; b=UlM8RQm8KuQ/17XJY/0XK9pcDiwh5lHcyrGT1JFeA3K7MVtFS7O13UXeJln3Zhh+KIM9tRqP9ayfyrLS5JyTauLeC3Ar0DtpKgaTAqgrr8/JI3NM7zTins0iGu+wTTOGa8mlYKBo0b3uRWXBnMJJZ65+iK5AoR08kImw99CLNp4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1584072498562754.6935249280455; Thu, 12 Mar 2020 21:08:18 -0700 (PDT) Received: from localhost ([::1]:53550 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jCbcP-0006pj-Gw for importer@patchew.org; Fri, 13 Mar 2020 00:08:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44178) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jCba7-0003Pi-P1 for qemu-devel@nongnu.org; Fri, 13 Mar 2020 00:05:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jCba6-00076R-4g for qemu-devel@nongnu.org; Fri, 13 Mar 2020 00:05:55 -0400 Received: from ozlabs.org ([2401:3900:2:1::2]:45881) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jCba5-0006rM-Cy; Fri, 13 Mar 2020 00:05:54 -0400 Received: by ozlabs.org (Postfix, from userid 1007) id 48dsYj3P9Tz9sSZ; Fri, 13 Mar 2020 15:05:45 +1100 (AEDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=gibson.dropbear.id.au; s=201602; t=1584072345; bh=ZyGNsReuHLghgU8doLbna1YKekJoPV2uMcvG/SjAWAo=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CLz67zEwjFhsRlWUROzzbOOezNmrIzOnAspTVRhWIjdQUyg3/ulTFuXyTmJApuLQ5 Oahf6FTjFbc7/aDV+1M0pe8MEkiSBjVuAUULCKQzzllVrWl6Pwb2KVQHWC2BK8kV49 kqchnSuf2cViQD/WfIA/MNaHd0jM0WWNvxeD/UWM= From: David Gibson To: groug@kaod.org, clg@kaod.org, philmd@redhat.com Subject: [PATCH 3/4] spapr: Rename DT functions to newer naming convention Date: Fri, 13 Mar 2020 15:05:38 +1100 Message-Id: <20200313040539.819138-4-david@gibson.dropbear.id.au> X-Mailer: git-send-email 2.24.1 In-Reply-To: <20200313040539.819138-1-david@gibson.dropbear.id.au> References: <20200313040539.819138-1-david@gibson.dropbear.id.au> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2401:3900:2:1::2 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, David Gibson Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Computed bodyhash is different from the expected one) Content-Type: text/plain; charset="utf-8" In the spapr code we've been gradually moving towards a convention that functions which create pieces of the device tree are called spapr_dt_*(). This patch speeds that along by renaming most of the things that don't yet match that so that they do. For now we leave the *_dt_populate() functions which are actual methods used in the DRCClass::dt_populate method. While we're there we remove a few comments that don't really say anything useful. Signed-off-by: David Gibson Reviewed-by: C=C3=A9dric Le Goater --- hw/ppc/spapr.c | 62 +++++++++++++++++-------------------- hw/ppc/spapr_ovec.c | 4 +-- include/hw/ppc/spapr_ovec.h | 4 +-- 3 files changed, 33 insertions(+), 37 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index fc28d9df25..6c32ec3c0a 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -217,10 +217,9 @@ static int spapr_fixup_cpu_numa_dt(void *fdt, int offs= et, PowerPCCPU *cpu) sizeof(associativity)); } =20 -/* Populate the "ibm,pa-features" property */ -static void spapr_populate_pa_features(SpaprMachineState *spapr, - PowerPCCPU *cpu, - void *fdt, int offset) +static void spapr_dt_pa_features(SpaprMachineState *spapr, + PowerPCCPU *cpu, + void *fdt, int offset) { uint8_t pa_features_206[] =3D { 6, 0, 0xf6, 0x1f, 0xc7, 0x00, 0x80, 0xc0 }; @@ -315,8 +314,8 @@ static void add_str(GString *s, const gchar *s1) g_string_append_len(s, s1, strlen(s1) + 1); } =20 -static int spapr_populate_memory_node(void *fdt, int nodeid, hwaddr start, - hwaddr size) +static int spapr_dt_memory_node(void *fdt, int nodeid, hwaddr start, + hwaddr size) { uint32_t associativity[] =3D { cpu_to_be32(0x4), /* length */ @@ -391,9 +390,8 @@ spapr_get_drconf_cell(uint32_t seq_lmbs, uint64_t base_= addr, return elem; } =20 -/* ibm,dynamic-memory-v2 */ -static int spapr_populate_drmem_v2(SpaprMachineState *spapr, void *fdt, - int offset, MemoryDeviceInfoList *dimms) +static int spapr_dt_dynamic_memory_v2(SpaprMachineState *spapr, void *fdt, + int offset, MemoryDeviceInfoList *di= mms) { MachineState *machine =3D MACHINE(spapr); uint8_t *int_buf, *cur_index; @@ -484,8 +482,7 @@ static int spapr_populate_drmem_v2(SpaprMachineState *s= papr, void *fdt, return 0; } =20 -/* ibm,dynamic-memory */ -static int spapr_populate_drmem_v1(SpaprMachineState *spapr, void *fdt, +static int spapr_dt_dynamic_memory(SpaprMachineState *spapr, void *fdt, int offset, MemoryDeviceInfoList *dimms) { MachineState *machine =3D MACHINE(spapr); @@ -554,7 +551,8 @@ static int spapr_populate_drmem_v1(SpaprMachineState *s= papr, void *fdt, * Refer to docs/specs/ppc-spapr-hotplug.txt for the documentation * of this device tree node. */ -static int spapr_populate_drconf_memory(SpaprMachineState *spapr, void *fd= t) +static int spapr_dt_dynamic_reconfiguration_memory(SpaprMachineState *spap= r, + void *fdt) { MachineState *machine =3D MACHINE(spapr); int nb_numa_nodes =3D machine->numa_state->num_nodes; @@ -593,9 +591,9 @@ static int spapr_populate_drconf_memory(SpaprMachineSta= te *spapr, void *fdt) /* ibm,dynamic-memory or ibm,dynamic-memory-v2 */ dimms =3D qmp_memory_device_list(); if (spapr_ovec_test(spapr->ov5_cas, OV5_DRMEM_V2)) { - ret =3D spapr_populate_drmem_v2(spapr, fdt, offset, dimms); + ret =3D spapr_dt_dynamic_memory_v2(spapr, fdt, offset, dimms); } else { - ret =3D spapr_populate_drmem_v1(spapr, fdt, offset, dimms); + ret =3D spapr_dt_dynamic_memory(spapr, fdt, offset, dimms); } qapi_free_MemoryDeviceInfoList(dimms); =20 @@ -626,7 +624,7 @@ static int spapr_populate_drconf_memory(SpaprMachineSta= te *spapr, void *fdt) return ret; } =20 -static int spapr_populate_memory(SpaprMachineState *spapr, void *fdt) +static int spapr_dt_memory(SpaprMachineState *spapr, void *fdt) { MachineState *machine =3D MACHINE(spapr); SpaprMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); @@ -649,7 +647,7 @@ static int spapr_populate_memory(SpaprMachineState *spa= pr, void *fdt) if (!mem_start) { /* spapr_machine_init() checks for rma_size <=3D node0_size * already */ - spapr_populate_memory_node(fdt, i, 0, spapr->rma_size); + spapr_dt_memory_node(fdt, i, 0, spapr->rma_size); mem_start +=3D spapr->rma_size; node_size -=3D spapr->rma_size; } @@ -661,7 +659,7 @@ static int spapr_populate_memory(SpaprMachineState *spa= pr, void *fdt) sizetmp =3D 1ULL << ctzl(mem_start); } =20 - spapr_populate_memory_node(fdt, i, mem_start, sizetmp); + spapr_dt_memory_node(fdt, i, mem_start, sizetmp); node_size -=3D sizetmp; mem_start +=3D sizetmp; } @@ -672,7 +670,7 @@ static int spapr_populate_memory(SpaprMachineState *spa= pr, void *fdt) int ret; =20 g_assert(smc->dr_lmb_enabled); - ret =3D spapr_populate_drconf_memory(spapr, fdt); + ret =3D spapr_dt_dynamic_reconfiguration_memory(spapr, fdt); if (ret) { return ret; } @@ -681,8 +679,8 @@ static int spapr_populate_memory(SpaprMachineState *spa= pr, void *fdt) return 0; } =20 -static void spapr_populate_cpu_dt(CPUState *cs, void *fdt, int offset, - SpaprMachineState *spapr) +static void spapr_dt_cpu(CPUState *cs, void *fdt, int offset, + SpaprMachineState *spapr) { MachineState *ms =3D MACHINE(spapr); PowerPCCPU *cpu =3D POWERPC_CPU(cs); @@ -782,7 +780,7 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *f= dt, int offset, page_sizes_prop, page_sizes_prop_size))); } =20 - spapr_populate_pa_features(spapr, cpu, fdt, offset); + spapr_dt_pa_features(spapr, cpu, fdt, offset); =20 _FDT((fdt_setprop_cell(fdt, offset, "ibm,chip-id", cs->cpu_index / vcpus_per_socket))); @@ -816,7 +814,7 @@ static void spapr_populate_cpu_dt(CPUState *cs, void *f= dt, int offset, pcc->lrg_decr_bits))); } =20 -static void spapr_populate_cpus_dt_node(void *fdt, SpaprMachineState *spap= r) +static void spapr_dt_cpus(void *fdt, SpaprMachineState *spapr) { CPUState **rev; CPUState *cs; @@ -860,13 +858,13 @@ static void spapr_populate_cpus_dt_node(void *fdt, Sp= aprMachineState *spapr) offset =3D fdt_add_subnode(fdt, cpus_offset, nodename); g_free(nodename); _FDT(offset); - spapr_populate_cpu_dt(cs, fdt, offset, spapr); + spapr_dt_cpu(cs, fdt, offset, spapr); } =20 g_free(rev); } =20 -static int spapr_rng_populate_dt(void *fdt) +static int spapr_dt_rng(void *fdt) { int node; int ret; @@ -1099,8 +1097,7 @@ static void spapr_dt_chosen(SpaprMachineState *spapr,= void *fdt) =20 spapr_dt_ov5_platform_support(spapr, fdt, chosen); =20 - _FDT(spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, - "ibm,architecture-vec-5")); + _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-= 5")); =20 g_free(stdout_path); g_free(bootlist); @@ -1181,7 +1178,7 @@ void *spapr_build_fdt(SpaprMachineState *spapr, bool = reset, size_t space) /* /interrupt controller */ spapr_irq_dt(spapr, spapr_max_server_number(spapr), fdt, PHANDLE_INTC); =20 - ret =3D spapr_populate_memory(spapr, fdt); + ret =3D spapr_dt_memory(spapr, fdt); if (ret < 0) { error_report("couldn't setup memory nodes in fdt"); exit(1); @@ -1191,7 +1188,7 @@ void *spapr_build_fdt(SpaprMachineState *spapr, bool = reset, size_t space) spapr_dt_vdevice(spapr->vio_bus, fdt); =20 if (object_resolve_path_type("", TYPE_SPAPR_RNG, NULL)) { - ret =3D spapr_rng_populate_dt(fdt); + ret =3D spapr_dt_rng(fdt); if (ret < 0) { error_report("could not set up rng device in the fdt"); exit(1); @@ -1206,8 +1203,7 @@ void *spapr_build_fdt(SpaprMachineState *spapr, bool = reset, size_t space) } } =20 - /* cpus */ - spapr_populate_cpus_dt_node(fdt, spapr); + spapr_dt_cpus(fdt, spapr); =20 if (smc->dr_lmb_enabled) { _FDT(spapr_dt_drc(fdt, 0, NULL, SPAPR_DR_CONNECTOR_TYPE_LMB)); @@ -3400,8 +3396,8 @@ int spapr_lmb_dt_populate(SpaprDrc *drc, SpaprMachine= State *spapr, addr =3D spapr_drc_index(drc) * SPAPR_MEMORY_BLOCK_SIZE; node =3D object_property_get_uint(OBJECT(drc->dev), PC_DIMM_NODE_PROP, &error_abort); - *fdt_start_offset =3D spapr_populate_memory_node(fdt, node, addr, - SPAPR_MEMORY_BLOCK_SIZE= ); + *fdt_start_offset =3D spapr_dt_memory_node(fdt, node, addr, + SPAPR_MEMORY_BLOCK_SIZE); return 0; } =20 @@ -3802,7 +3798,7 @@ int spapr_core_dt_populate(SpaprDrc *drc, SpaprMachin= eState *spapr, offset =3D fdt_add_subnode(fdt, 0, nodename); g_free(nodename); =20 - spapr_populate_cpu_dt(cs, fdt, offset, spapr); + spapr_dt_cpu(cs, fdt, offset, spapr); =20 *fdt_start_offset =3D offset; return 0; diff --git a/hw/ppc/spapr_ovec.c b/hw/ppc/spapr_ovec.c index 0ff6d1aeae..dd003f1763 100644 --- a/hw/ppc/spapr_ovec.c +++ b/hw/ppc/spapr_ovec.c @@ -200,8 +200,8 @@ SpaprOptionVector *spapr_ovec_parse_vector(target_ulong= table_addr, int vector) return ov; } =20 -int spapr_ovec_populate_dt(void *fdt, int fdt_offset, - SpaprOptionVector *ov, const char *name) +int spapr_dt_ovec(void *fdt, int fdt_offset, + SpaprOptionVector *ov, const char *name) { uint8_t vec[OV_MAXBYTES + 1]; uint16_t vec_len; diff --git a/include/hw/ppc/spapr_ovec.h b/include/hw/ppc/spapr_ovec.h index 2bed517a2b..d4dee9e06a 100644 --- a/include/hw/ppc/spapr_ovec.h +++ b/include/hw/ppc/spapr_ovec.h @@ -72,8 +72,8 @@ void spapr_ovec_set(SpaprOptionVector *ov, long bitnr); void spapr_ovec_clear(SpaprOptionVector *ov, long bitnr); bool spapr_ovec_test(SpaprOptionVector *ov, long bitnr); SpaprOptionVector *spapr_ovec_parse_vector(target_ulong table_addr, int ve= ctor); -int spapr_ovec_populate_dt(void *fdt, int fdt_offset, - SpaprOptionVector *ov, const char *name); +int spapr_dt_ovec(void *fdt, int fdt_offset, + SpaprOptionVector *ov, const char *name); =20 /* migration */ extern const VMStateDescription vmstate_spapr_ovec; --=20 2.24.1 From nobody Mon Apr 29 16:34:59 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1584072422; cv=none; d=zohomail.com; s=zohoarc; b=nDxp+YqjGkmwRGoaesiEpZXqk0xfSAG2XMi69N1XTS7DY7Y3/E0NRxgYQY6JQEumav60Oo+BCTBX+IO3OUfRDxKxFfl/5ZaoQyfs1qfb5eJBkQHzkWE5K4AE5ccN4rOyPwuzZVvqJ348gSNXKHF7IDA5d1VY0bDONfUwGAdHKxk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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charset="utf-8" The Real Mode Area (RMA) needs to fit within the NUMA node owning memory at address 0. That's usually node 0, but can be a later one if there are some nodes which have no memory (only CPUs). This is currently handled by the spapr_node0_size() helper. It has only one caller, so there's not a lot of point splitting it out. It's also extremely easy to misread the code as clamping to the size of the smallest node rather than the first node with any memory. So, fold it into the caller, and add some commentary to make it a bit clearer exactly what it's doing. Signed-off-by: David Gibson --- hw/ppc/spapr.c | 37 +++++++++++++++++++++---------------- 1 file changed, 21 insertions(+), 16 deletions(-) diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 6c32ec3c0a..6a42c0f1c9 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -295,20 +295,6 @@ static void spapr_dt_pa_features(SpaprMachineState *sp= apr, _FDT((fdt_setprop(fdt, offset, "ibm,pa-features", pa_features, pa_size= ))); } =20 -static hwaddr spapr_node0_size(MachineState *machine) -{ - if (machine->numa_state->num_nodes) { - int i; - for (i =3D 0; i < machine->numa_state->num_nodes; ++i) { - if (machine->numa_state->nodes[i].node_mem) { - return MIN(pow2floor(machine->numa_state->nodes[i].node_me= m), - machine->ram_size); - } - } - } - return machine->ram_size; -} - static void add_str(GString *s, const gchar *s1) { g_string_append_len(s, s1, strlen(s1) + 1); @@ -2631,10 +2617,24 @@ static hwaddr spapr_rma_size(SpaprMachineState *spa= pr, Error **errp) MachineState *machine =3D MACHINE(spapr); SpaprMachineClass *smc =3D SPAPR_MACHINE_GET_CLASS(spapr); hwaddr rma_size =3D machine->ram_size; - hwaddr node0_size =3D spapr_node0_size(machine); =20 /* RMA has to fit in the first NUMA node */ - rma_size =3D MIN(rma_size, node0_size); + if (machine->numa_state->num_nodes) { + /* + * It's possible for there to be some zero-memory nodes first + * in the list. We need the RMA to fit inside the memory of + * the first node which actually has some memory. + */ + int i; + + for (i =3D 0; i < machine->numa_state->num_nodes; ++i) { + if (machine->numa_state->nodes[i].node_mem !=3D 0) { + hwaddr node_size =3D machine->numa_state->nodes[i].node_me= m; + rma_size =3D MIN(rma_size, pow2floor(node_size)); + break; + } + } + } =20 /* * VRMA access is via a special 1TiB SLB mapping, so the RMA can @@ -2651,6 +2651,11 @@ static hwaddr spapr_rma_size(SpaprMachineState *spap= r, Error **errp) rma_size =3D MIN(rma_size, smc->rma_limit); } =20 + /* + * RMA size must be a power of 2 + */ + rma_size =3D pow2floor(rma_size); + if (rma_size < MIN_RMA_SLOF) { error_setg(errp, "pSeries SLOF firmware requires >=3D %ldMiB guest RMA (Real Mode Area memo= ry)", --=20 2.24.1