From nobody Sun May 5 17:47:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1584071662; cv=none; d=zohomail.com; s=zohoarc; b=dpkXUBphsTRHdTI7ac3TgN4JN+criu5NhGdn0R9O51t7ryFc5MeXPMuMBVmiBKwgW7UrsNUFZCmkVAuRN6v5m27remASiTp7Yu2aDC6BNBxrr4X92U+r4nKdHN0ABZRzDLVWEt5Qo+dv6V7tclYT+csrL3gfdzkFyoFprUNpnoE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1584071662; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=olBNTK4tXhmTzDsuDJKOk1KyWEAJGSH0ST4HSMsKTek=; b=CgzhBRgqKfPW4Jdc+dNVxfwRFXFYcBZpz11EmigYNU9HkeKrs8MsEwvupsCLkLVT/9JeMdlllXTypHd4FOowK8QSVKzexUHdN6XKnDxVku0Uza4xXL/qhDAMv9RHcSAa894kUyFbbKmyzRDEczwv1jcDw4qnW+Q4PSAiyAqxKfg= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1584071662518726.4554364162952; Thu, 12 Mar 2020 20:54:22 -0700 (PDT) Received: from localhost ([::1]:53404 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jCbOv-0003B0-I7 for importer@patchew.org; Thu, 12 Mar 2020 23:54:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47827) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jCbMJ-0006td-2a for qemu-devel@nongnu.org; Thu, 12 Mar 2020 23:51:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jCbMH-0000af-Mh for qemu-devel@nongnu.org; Thu, 12 Mar 2020 23:51:38 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:3283 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jCbMH-0000M7-Av; Thu, 12 Mar 2020 23:51:37 -0400 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 7AD17D452872961AD590; Fri, 13 Mar 2020 11:51:26 +0800 (CST) Received: from huawei.com (10.133.201.158) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.487.0; Fri, 13 Mar 2020 11:51:19 +0800 From: Yifei Jiang To: , Subject: [PATCH RFC 1/9] linux-header: Update linux/kvm.h Date: Fri, 13 Mar 2020 11:49:41 +0800 Message-ID: <20200313034949.3028-2-jiangyifei@huawei.com> X-Mailer: git-send-email 2.23.0.windows.1 In-Reply-To: <20200313034949.3028-1-jiangyifei@huawei.com> References: <20200313034949.3028-1-jiangyifei@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.133.201.158] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.191 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: anup.patel@wdc.com, zhang.zhanghailiang@huawei.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, victor.zhangxiaofeng@huawei.com, Alistair.Francis@wdc.com, yinyipeng1@huawei.com, palmer@dabbelt.com, Yifei Jiang , dengkai1@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Update linux/kvm.h to commit b9a6e4cd9 on https://github.com/kvm-riscv/linu= x. Only use this header file, so do not update all linux headers. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- linux-headers/linux/kvm.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index 265099100e..7cfc111af5 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux/kvm.h @@ -236,6 +236,7 @@ struct kvm_hyperv_exit { #define KVM_EXIT_IOAPIC_EOI 26 #define KVM_EXIT_HYPERV 27 #define KVM_EXIT_ARM_NISV 28 +#define KVM_EXIT_RISCV_SBI 28 =20 /* For KVM_EXIT_INTERNAL_ERROR */ /* Emulate instruction failed. */ @@ -400,6 +401,13 @@ struct kvm_run { __u64 esr_iss; __u64 fault_ipa; } arm_nisv; + /* KVM_EXIT_RISCV_SBI */ + struct { + unsigned long extension_id; + unsigned long function_id; + unsigned long args[6]; + unsigned long ret[2]; + } riscv_sbi; /* Fix the size of the union. */ char padding[256]; }; --=20 2.19.1 From nobody Sun May 5 17:47:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1584071728; cv=none; d=zohomail.com; s=zohoarc; b=lUfhw6nXQ9lkjJ5puo+lrtthVbpiVxDfpjorZObOfSFuhIuFPNUioP7cW1fl1pBo3Rv4VbIkhCtgPzZtXRtIkjrQculnX7qhs1i5pILe7QK4VxiZ57zity9oVIYr37aIcFGHYc4eWs8VrDQ3vkW8LI+Xxu7ApMhzzy9Dvr5i31Q= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1584071728; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+BBeFaZQIGZFdsnOxp04hPQDbTT3GRK7e8g8JIDJQ2A=; b=fBKPed2eCA1yNT1eifRffqZAML40RW5BEbYrpH4Dwoqj+oesO4reI9P2mLaPEsnl3BDQLM7LG+NypeNDTi+U2ITNnZS+3E0TtonQCvMT8wkTcnWCDa0xHy3Ogeammlc3iNCY4RmJCBRciwy/uz2Sp26ilBLONit4o1ARTCZFyhE= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1584071728730443.17759583364375; Thu, 12 Mar 2020 20:55:28 -0700 (PDT) Received: from localhost ([::1]:53414 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jCbPz-0004qQ-Lp for importer@patchew.org; Thu, 12 Mar 2020 23:55:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47859) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jCbMJ-0006th-Em for qemu-devel@nongnu.org; Thu, 12 Mar 2020 23:51:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jCbMH-0000am-NF for qemu-devel@nongnu.org; Thu, 12 Mar 2020 23:51:39 -0400 Received: from szxga05-in.huawei.com ([45.249.212.191]:3285 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jCbMH-0000M2-Ax; Thu, 12 Mar 2020 23:51:37 -0400 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 831932CB3E1B378AD7EF; Fri, 13 Mar 2020 11:51:26 +0800 (CST) Received: from huawei.com (10.133.201.158) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.487.0; Fri, 13 Mar 2020 11:51:20 +0800 From: Yifei Jiang To: , Subject: [PATCH RFC 2/9] target/riscv: Add target/riscv/kvm.c to place the public kvm interface Date: Fri, 13 Mar 2020 11:49:42 +0800 Message-ID: <20200313034949.3028-3-jiangyifei@huawei.com> X-Mailer: git-send-email 2.23.0.windows.1 In-Reply-To: <20200313034949.3028-1-jiangyifei@huawei.com> References: <20200313034949.3028-1-jiangyifei@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.133.201.158] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.191 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: anup.patel@wdc.com, zhang.zhanghailiang@huawei.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, victor.zhangxiaofeng@huawei.com, Alistair.Francis@wdc.com, yinyipeng1@huawei.com, palmer@dabbelt.com, Yifei Jiang , dengkai1@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Add target/riscv/kvm.c to place kvm_arch_* function needed by kvm/kvm-all.c. Meanwhile, add riscv64 kvm support to configure. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- configure | 1 + target/riscv/Makefile.objs | 1 + target/riscv/kvm.c | 128 +++++++++++++++++++++++++++++++++++++ 3 files changed, 130 insertions(+) create mode 100644 target/riscv/kvm.c diff --git a/configure b/configure index 3c7470096f..30024a8aef 100755 --- a/configure +++ b/configure @@ -200,6 +200,7 @@ supported_kvm_target() { x86_64:i386 | x86_64:x86_64 | x86_64:x32 | \ mips:mips | mipsel:mips | \ ppc:ppc | ppc64:ppc | ppc:ppc64 | ppc64:ppc64 | ppc64:ppc64le | \ + riscv64:riscv64 | \ s390x:s390x) return 0 ;; diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs index ff651f69f6..7ea8f4c3da 100644 --- a/target/riscv/Makefile.objs +++ b/target/riscv/Makefile.objs @@ -1,5 +1,6 @@ obj-y +=3D translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o g= dbstub.o obj-$(CONFIG_SOFTMMU) +=3D pmp.o +obj-$(CONFIG_KVM) +=3D kvm.o =20 ifeq ($(CONFIG_SOFTMMU),y) obj-y +=3D monitor.o diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c new file mode 100644 index 0000000000..8c386d9acf --- /dev/null +++ b/target/riscv/kvm.c @@ -0,0 +1,128 @@ +/* + * RISC-V implementation of KVM hooks + * + * Copyright (c) 2020 Huawei Technologies Co., Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include + +#include + +#include "qemu-common.h" +#include "qemu/timer.h" +#include "qemu/error-report.h" +#include "qemu/main-loop.h" +#include "sysemu/sysemu.h" +#include "sysemu/kvm.h" +#include "sysemu/kvm_int.h" +#include "cpu.h" +#include "trace.h" +#include "hw/pci/pci.h" +#include "exec/memattrs.h" +#include "exec/address-spaces.h" +#include "hw/boards.h" +#include "hw/irq.h" +#include "qemu/log.h" +#include "hw/loader.h" + +const KVMCapabilityInfo kvm_arch_required_capabilities[] =3D { + KVM_CAP_LAST_INFO +}; + +int kvm_arch_get_registers(CPUState *cs) +{ + return 0; +} + +int kvm_arch_put_registers(CPUState *cs, int level) +{ + return 0; +} + +int kvm_arch_release_virq_post(int virq) +{ + return 0; +} + +int kvm_arch_fixup_msi_route(struct kvm_irq_routing_entry *route, + uint64_t address, uint32_t data, PCIDevice *d= ev) +{ + return 0; +} + +int kvm_arch_destroy_vcpu(CPUState *cs) +{ + return 0; +} + +unsigned long kvm_arch_vcpu_id(CPUState *cpu) +{ + return cpu->cpu_index; +} + +void kvm_arch_init_irq_routing(KVMState *s) +{ +} + +int kvm_arch_init_vcpu(CPUState *cs) +{ + return 0; +} + +int kvm_arch_msi_data_to_gsi(uint32_t data) +{ + abort(); +} + +int kvm_arch_add_msi_route_post(struct kvm_irq_routing_entry *route, + int vector, PCIDevice *dev) +{ + return 0; +} + +int kvm_arch_init(MachineState *ms, KVMState *s) +{ + return 0; +} + +int kvm_arch_irqchip_create(KVMState *s) +{ + return 0; +} + +int kvm_arch_process_async_events(CPUState *cs) +{ + return 0; +} + +void kvm_arch_pre_run(CPUState *cs, struct kvm_run *run) +{ +} + +MemTxAttrs kvm_arch_post_run(CPUState *cs, struct kvm_run *run) +{ + return MEMTXATTRS_UNSPECIFIED; +} + +bool kvm_arch_stop_on_emulation_error(CPUState *cs) +{ + return true; +} + +int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) +{ + return 0; +} --=20 2.19.1 From nobody Sun May 5 17:47:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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Thu, 12 Mar 2020 23:51:37 -0400 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 854F2B06234F1C8F1D0E; Fri, 13 Mar 2020 11:51:31 +0800 (CST) Received: from huawei.com (10.133.201.158) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.487.0; Fri, 13 Mar 2020 11:51:21 +0800 From: Yifei Jiang To: , Subject: [PATCH RFC 3/9] target/riscv: Implement function kvm_arch_init_vcpu Date: Fri, 13 Mar 2020 11:49:43 +0800 Message-ID: <20200313034949.3028-4-jiangyifei@huawei.com> X-Mailer: git-send-email 2.23.0.windows.1 In-Reply-To: <20200313034949.3028-1-jiangyifei@huawei.com> References: <20200313034949.3028-1-jiangyifei@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.133.201.158] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: anup.patel@wdc.com, zhang.zhanghailiang@huawei.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, victor.zhangxiaofeng@huawei.com, Alistair.Francis@wdc.com, yinyipeng1@huawei.com, palmer@dabbelt.com, Yifei Jiang , dengkai1@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Get isa info from kvm while kvm init. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/kvm.c | 26 +++++++++++++++++++++++++- 1 file changed, 25 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 8c386d9acf..3e8f8e7185 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -38,6 +38,18 @@ #include "qemu/log.h" #include "hw/loader.h" =20 +static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx) +{ + __u64 id =3D KVM_REG_RISCV | type | idx; + +#if defined(TARGET_RISCV32) + id |=3D KVM_REG_SIZE_U32; +#elif defined(TARGET_RISCV64) + id |=3D KVM_REG_SIZE_U64; +#endif + return id; +} + const KVMCapabilityInfo kvm_arch_required_capabilities[] =3D { KVM_CAP_LAST_INFO }; @@ -79,7 +91,19 @@ void kvm_arch_init_irq_routing(KVMState *s) =20 int kvm_arch_init_vcpu(CPUState *cs) { - return 0; + int ret =3D 0; + uint64_t isa; + RISCVCPU *cpu =3D RISCV_CPU(cs); + __u64 id; + + id =3D kvm_riscv_reg_id(KVM_REG_RISCV_CONFIG, KVM_REG_RISCV_CONFIG_REG= (isa)); + ret =3D kvm_get_one_reg(cs, id, &isa); + if (ret) { + return ret; + } + cpu->env.misa =3D isa; + + return ret; } =20 int kvm_arch_msi_data_to_gsi(uint32_t data) --=20 2.19.1 From nobody Sun May 5 17:47:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1584071568; cv=none; d=zohomail.com; s=zohoarc; b=djuA3CL3gTlaE1WlTmIGLMoNIIyMcjZqqCVNnsDi4Q01rv4NZ8x/JDEnR41fVj254WDe6Feqla2Wgul/EaTQTYbuGGcbqksCFBiiuksvQG9CmgUB0t2cx0niJTw3MrEV+yyuP0qyJm2NLlpbv8aQKddp6FPkJjcPQNQpkCbAwek= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1584071568; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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Thu, 12 Mar 2020 23:51:39 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:35000 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jCbMH-0000SI-At; Thu, 12 Mar 2020 23:51:37 -0400 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 9114347B0B2A80B7DBEE; Fri, 13 Mar 2020 11:51:31 +0800 (CST) Received: from huawei.com (10.133.201.158) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.487.0; Fri, 13 Mar 2020 11:51:21 +0800 From: Yifei Jiang To: , Subject: [PATCH RFC 4/9] target/riscv: Implement kvm_arch_get_registers Date: Fri, 13 Mar 2020 11:49:44 +0800 Message-ID: <20200313034949.3028-5-jiangyifei@huawei.com> X-Mailer: git-send-email 2.23.0.windows.1 In-Reply-To: <20200313034949.3028-1-jiangyifei@huawei.com> References: <20200313034949.3028-1-jiangyifei@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.133.201.158] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: anup.patel@wdc.com, zhang.zhanghailiang@huawei.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, victor.zhangxiaofeng@huawei.com, Alistair.Francis@wdc.com, yinyipeng1@huawei.com, palmer@dabbelt.com, Yifei Jiang , dengkai1@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Get GPR CSR and FP registers from kvm by KVM_GET_ONE_REG ioctl. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/kvm.c | 144 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 143 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 3e8f8e7185..8d5069b9e9 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -50,13 +50,155 @@ static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx) return id; } =20 +#define RISCV_CORE_REG(name) kvm_riscv_reg_id(KVM_REG_RISCV_CORE, \ + KVM_REG_RISCV_CORE_REG(name)) + +#define RISCV_CSR_REG(name) kvm_riscv_reg_id(KVM_REG_RISCV_CSR, \ + KVM_REG_RISCV_CSR_REG(name)) + +#define RISCV_FP_F_REG(idx) kvm_riscv_reg_id(KVM_REG_RISCV_FP_F, idx) + +#define RISCV_FP_D_REG(idx) kvm_riscv_reg_id(KVM_REG_RISCV_FP_D, idx) + +static int kvm_riscv_get_regs_core(CPUState *cs) +{ + int ret =3D 0; + int i; + uint64_t reg; + CPURISCVState *env =3D &RISCV_CPU(cs)->env; + + ret =3D kvm_get_one_reg(cs, RISCV_CORE_REG(regs.pc), ®); + if (ret) { + return ret; + } + env->pc =3D reg; + + for (i =3D 1; i < 32; i++) { + __u64 id =3D kvm_riscv_reg_id(KVM_REG_RISCV_CORE, i); + ret =3D kvm_get_one_reg(cs, id, ®); + if (ret) { + return ret; + } + env->gpr[i] =3D reg; + } + + return ret; +} + +static int kvm_riscv_get_regs_csr(CPUState *cs) +{ + int ret =3D 0; + uint64_t reg; + CPURISCVState *env =3D &RISCV_CPU(cs)->env; + + ret =3D kvm_get_one_reg(cs, RISCV_CSR_REG(sstatus), ®); + if (ret) { + return ret; + } + env->mstatus =3D reg; + + ret =3D kvm_get_one_reg(cs, RISCV_CSR_REG(sie), ®); + if (ret) { + return ret; + } + env->mie =3D reg; + + ret =3D kvm_get_one_reg(cs, RISCV_CSR_REG(stvec), ®); + if (ret) { + return ret; + } + env->stvec =3D reg; + + ret =3D kvm_get_one_reg(cs, RISCV_CSR_REG(sscratch), ®); + if (ret) { + return ret; + } + env->sscratch =3D reg; + + ret =3D kvm_get_one_reg(cs, RISCV_CSR_REG(sepc), ®); + if (ret) { + return ret; + } + env->sepc =3D reg; + + ret =3D kvm_get_one_reg(cs, RISCV_CSR_REG(scause), ®); + if (ret) { + return ret; + } + env->scause =3D reg; + + ret =3D kvm_get_one_reg(cs, RISCV_CSR_REG(sip), ®); + if (ret) { + return ret; + } + env->mip =3D reg; + + ret =3D kvm_get_one_reg(cs, RISCV_CSR_REG(sstatus), ®); + if (ret) { + return ret; + } + env->satp =3D reg; + + return ret; +} + +static int kvm_riscv_get_regs_fp(CPUState *cs) +{ + int ret =3D 0; + int i; + CPURISCVState *env =3D &RISCV_CPU(cs)->env; + + if (riscv_has_ext(env, RVD)) { + uint64_t reg; + for (i =3D 0; i < 32; i++) { + ret =3D kvm_get_one_reg(cs, RISCV_FP_D_REG(i), ®); + if (ret) { + return ret; + } + env->fpr[i] =3D reg; + } + return ret; + } + + if (riscv_has_ext(env, RVF)) { + uint32_t reg; + for (i =3D 0; i < 32; i++) { + ret =3D kvm_get_one_reg(cs, RISCV_FP_F_REG(i), ®); + if (ret) { + return ret; + } + env->fpr[i] =3D reg; + } + return ret; + } + + return ret; +} + const KVMCapabilityInfo kvm_arch_required_capabilities[] =3D { KVM_CAP_LAST_INFO }; =20 int kvm_arch_get_registers(CPUState *cs) { - return 0; + int ret =3D 0; + + ret =3D kvm_riscv_get_regs_core(cs); + if (ret) { + return ret; + } + + ret =3D kvm_riscv_get_regs_csr(cs); + if (ret) { + return ret; + } + + ret =3D kvm_riscv_get_regs_fp(cs); + if (ret) { + return ret; + } + + return ret; } =20 int kvm_arch_put_registers(CPUState *cs, int level) --=20 2.19.1 From nobody Sun May 5 17:47:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1584071569; cv=none; d=zohomail.com; s=zohoarc; b=FceFCvXzqs0KKwguPpmVQ/op8FUyZHO0vNkgmc0d2CEaNyh0l4+x9cnAB+Q1x37rHO7gOkdQzdKfIfH8sWpyg5zcnze8zcsHuuTALrDRU9KyWQt13r+o2xVnsnNr54CQdo2zEVi2rueE3SFDys9FbwzlKzOm1bPZ3y+Wt+Klqts= ARC-Message-Signature: i=1; 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Thu, 12 Mar 2020 23:52:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47849) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jCbMJ-0006tg-AF for qemu-devel@nongnu.org; Thu, 12 Mar 2020 23:51:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jCbMH-0000b3-Nk for qemu-devel@nongnu.org; Thu, 12 Mar 2020 23:51:39 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:35008 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jCbMH-0000SJ-Ay; Thu, 12 Mar 2020 23:51:37 -0400 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 9C4DA5360106C1A36A6D; Fri, 13 Mar 2020 11:51:31 +0800 (CST) Received: from huawei.com (10.133.201.158) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.487.0; Fri, 13 Mar 2020 11:51:22 +0800 From: Yifei Jiang To: , Subject: [PATCH RFC 5/9] target/riscv: Implement kvm_arch_put_registers Date: Fri, 13 Mar 2020 11:49:45 +0800 Message-ID: <20200313034949.3028-6-jiangyifei@huawei.com> X-Mailer: git-send-email 2.23.0.windows.1 In-Reply-To: <20200313034949.3028-1-jiangyifei@huawei.com> References: <20200313034949.3028-1-jiangyifei@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.133.201.158] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: anup.patel@wdc.com, zhang.zhanghailiang@huawei.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, victor.zhangxiaofeng@huawei.com, Alistair.Francis@wdc.com, yinyipeng1@huawei.com, palmer@dabbelt.com, Yifei Jiang , dengkai1@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Put GPR CSR and FP registers by kvm by KVM_SET_ONE_REG ioctl Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/kvm.c | 136 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 135 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 8d5069b9e9..6dffda36bb 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -85,6 +85,31 @@ static int kvm_riscv_get_regs_core(CPUState *cs) return ret; } =20 +static int kvm_riscv_put_regs_core(CPUState *cs) +{ + int ret =3D 0; + int i; + uint64_t reg; + CPURISCVState *env =3D &RISCV_CPU(cs)->env; + + reg =3D env->pc; + ret =3D kvm_set_one_reg(cs, RISCV_CORE_REG(regs.pc), ®); + if (ret) { + return ret; + } + + for (i =3D 1; i < 32; i++) { + __u64 id =3D kvm_riscv_reg_id(KVM_REG_RISCV_CORE, i); + reg =3D env->gpr[i]; + ret =3D kvm_set_one_reg(cs, id, ®); + if (ret) { + return ret; + } + } + + return ret; +} + static int kvm_riscv_get_regs_csr(CPUState *cs) { int ret =3D 0; @@ -142,6 +167,64 @@ static int kvm_riscv_get_regs_csr(CPUState *cs) return ret; } =20 +static int kvm_riscv_put_regs_csr(CPUState *cs) +{ + int ret =3D 0; + uint64_t reg; + CPURISCVState *env =3D &RISCV_CPU(cs)->env; + + reg =3D env->mstatus; + ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(sstatus), ®); + if (ret) { + return ret; + } + + reg =3D env->mie; + ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(sie), ®); + if (ret) { + return ret; + } + + reg =3D env->stvec; + ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(stvec), ®); + if (ret) { + return ret; + } + + reg =3D env->sscratch; + ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(sscratch), ®); + if (ret) { + return ret; + } + + reg =3D env->sepc; + ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(sepc), ®); + if (ret) { + return ret; + } + + reg =3D env->scause; + ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(scause), ®); + if (ret) { + return ret; + } + + reg =3D env->mip; + ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(sip), ®); + if (ret) { + return ret; + } + + reg =3D env->satp; + ret =3D kvm_set_one_reg(cs, RISCV_CSR_REG(sstatus), ®); + if (ret) { + return ret; + } + + return ret; +} + + static int kvm_riscv_get_regs_fp(CPUState *cs) { int ret =3D 0; @@ -175,6 +258,40 @@ static int kvm_riscv_get_regs_fp(CPUState *cs) return ret; } =20 +static int kvm_riscv_put_regs_fp(CPUState *cs) +{ + int ret =3D 0; + int i; + CPURISCVState *env =3D &RISCV_CPU(cs)->env; + + if (riscv_has_ext(env, RVD)) { + uint64_t reg; + for (i =3D 0; i < 32; i++) { + reg =3D env->fpr[i]; + ret =3D kvm_set_one_reg(cs, RISCV_FP_D_REG(i), ®); + if (ret) { + return ret; + } + } + return ret; + } + + if (riscv_has_ext(env, RVF)) { + uint32_t reg; + for (i =3D 0; i < 32; i++) { + reg =3D env->fpr[i]; + ret =3D kvm_set_one_reg(cs, RISCV_FP_F_REG(i), ®); + if (ret) { + return ret; + } + } + return ret; + } + + return ret; +} + + const KVMCapabilityInfo kvm_arch_required_capabilities[] =3D { KVM_CAP_LAST_INFO }; @@ -203,7 +320,24 @@ int kvm_arch_get_registers(CPUState *cs) =20 int kvm_arch_put_registers(CPUState *cs, int level) { - return 0; + int ret =3D 0; + + ret =3D kvm_riscv_put_regs_core(cs); + if (ret) { + return ret; + } + + ret =3D kvm_riscv_put_regs_csr(cs); + if (ret) { + return ret; + } + + ret =3D kvm_riscv_put_regs_fp(cs); + if (ret) { + return ret; + } + + return ret; } =20 int kvm_arch_release_virq_post(int virq) --=20 2.19.1 From nobody Sun May 5 17:47:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1584071803; cv=none; d=zohomail.com; s=zohoarc; b=CldZZvB1zj3GC5DMxkXa5C5yE0T74vgKzw6P3h4hfmWPruWYeGEUtoVsUBXnDM7QMAPRHNXsQOP/tPYjYSI+YWOCv10EtTuEpGO2aVSq8DzapJVExairUcEYcp3Js7uQbwtmV+wEMZEuI/nNjihEEcLRL4t7bgfkZ0Ez/GFwTmA= ARC-Message-Signature: i=1; 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Thu, 12 Mar 2020 23:56:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47875) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jCbMJ-0006ti-Ov for qemu-devel@nongnu.org; Thu, 12 Mar 2020 23:51:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jCbMH-0000b8-OJ for qemu-devel@nongnu.org; Thu, 12 Mar 2020 23:51:39 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:34964 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jCbMH-0000SH-Az; Thu, 12 Mar 2020 23:51:37 -0400 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 8AF45C604A1ED36CCD46; Fri, 13 Mar 2020 11:51:31 +0800 (CST) Received: from huawei.com (10.133.201.158) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.487.0; Fri, 13 Mar 2020 11:51:23 +0800 From: Yifei Jiang To: , Subject: [PATCH RFC 6/9] target/riscv: Support start kernel directly by KVM Date: Fri, 13 Mar 2020 11:49:46 +0800 Message-ID: <20200313034949.3028-7-jiangyifei@huawei.com> X-Mailer: git-send-email 2.23.0.windows.1 In-Reply-To: <20200313034949.3028-1-jiangyifei@huawei.com> References: <20200313034949.3028-1-jiangyifei@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.133.201.158] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: anup.patel@wdc.com, zhang.zhanghailiang@huawei.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, victor.zhangxiaofeng@huawei.com, Alistair.Francis@wdc.com, yinyipeng1@huawei.com, palmer@dabbelt.com, Yifei Jiang , dengkai1@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Get kernel and fdt start address in virt.c, and pass them to KVM when cpu reset.In addition,add kvm_riscv.h to place riscv specific interface. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- hw/riscv/virt.c | 15 +++++++++++++-- target/riscv/cpu.c | 4 ++++ target/riscv/cpu.h | 3 +++ target/riscv/kvm.c | 14 ++++++++++++++ target/riscv/kvm_riscv.h | 24 ++++++++++++++++++++++++ 5 files changed, 58 insertions(+), 2 deletions(-) create mode 100644 target/riscv/kvm_riscv.h diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 85ec9e22aa..e42c61208d 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -42,6 +42,7 @@ #include "exec/address-spaces.h" #include "hw/pci/pci.h" #include "hw/pci-host/gpex.h" +#include "sysemu/kvm.h" =20 #include =20 @@ -480,6 +481,9 @@ static void riscv_virt_board_init(MachineState *machine) target_ulong start_addr =3D memmap[VIRT_DRAM].base; int i; unsigned int smp_cpus =3D machine->smp.cpus; + uint64_t kernel_entry =3D 0; + hwaddr start_fdt; + CPUState *cs; =20 /* Initialize SOC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc= ), @@ -510,7 +514,7 @@ static void riscv_virt_board_init(MachineState *machine) memmap[VIRT_DRAM].base); =20 if (machine->kernel_filename) { - uint64_t kernel_entry =3D riscv_load_kernel(machine->kernel_filena= me, + kernel_entry =3D riscv_load_kernel(machine->kernel_filename, NULL); =20 if (machine->initrd_filename) { @@ -564,10 +568,17 @@ static void riscv_virt_board_init(MachineState *machi= ne) exit(1); } qemu_fdt_dumpdtb(s->fdt, fdt_totalsize(s->fdt)); + start_fdt =3D memmap[VIRT_MROM].base + sizeof(reset_vec); rom_add_blob_fixed_as("mrom.fdt", s->fdt, fdt_totalsize(s->fdt), - memmap[VIRT_MROM].base + sizeof(reset_vec), + start_fdt, &address_space_memory); =20 + for (cs =3D first_cpu; cs; cs =3D CPU_NEXT(cs)) { + RISCVCPU *riscv_cpu =3D RISCV_CPU(cs); + riscv_cpu->env.loader_start =3D kernel_entry; + riscv_cpu->env.fdt_start =3D start_fdt; + } + /* create PLIC hart topology configuration string */ plic_hart_config_len =3D (strlen(VIRT_PLIC_HART_CONFIG) + 1) * smp_cpu= s; plic_hart_config =3D g_malloc0(plic_hart_config_len); diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c0b7023100..3c3264869f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -28,6 +28,7 @@ #include "hw/qdev-properties.h" #include "migration/vmstate.h" #include "fpu/softfloat-helpers.h" +#include "kvm_riscv.h" =20 /* RISC-V CPU definitions */ =20 @@ -346,6 +347,9 @@ static void riscv_cpu_reset(CPUState *cs) cs->exception_index =3D EXCP_NONE; env->load_res =3D -1; set_default_nan_mode(1, &env->fp_status); +#ifdef CONFIG_KVM + kvm_riscv_reset_vcpu(cpu); +#endif } =20 static void riscv_cpu_disas_set_info(CPUState *s, disassemble_info *info) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 3dcdf92227..2724eca714 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -213,6 +213,9 @@ struct CPURISCVState { =20 /* Fields from here on are preserved across CPU reset. */ QEMUTimer *timer; /* Internal timer */ + + hwaddr loader_start; + hwaddr fdt_start; }; =20 #define RISCV_CPU_CLASS(klass) \ diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 6dffda36bb..b9aec66b69 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -37,6 +37,7 @@ #include "hw/irq.h" #include "qemu/log.h" #include "hw/loader.h" +#include "kvm_riscv.h" =20 static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx) { @@ -426,3 +427,16 @@ int kvm_arch_handle_exit(CPUState *cs, struct kvm_run = *run) { return 0; } + +void kvm_riscv_reset_vcpu(RISCVCPU *cpu) +{ + CPURISCVState *env =3D &cpu->env; + + if (!kvm_enabled()) { + return; + } + env->pc =3D cpu->env.loader_start; + env->gpr[10] =3D kvm_arch_vcpu_id(CPU(cpu)); /* a0 */ + env->gpr[11] =3D cpu->env.fdt_start; /* a1 */ +} + diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h new file mode 100644 index 0000000000..f38c82bf59 --- /dev/null +++ b/target/riscv/kvm_riscv.h @@ -0,0 +1,24 @@ +/* + * QEMU KVM support -- RISC-V specific functions. + * + * Copyright (c) 2020 Huawei Technologies Co., Ltd + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef QEMU_KVM_RISCV_H +#define QEMU_KVM_RISCV_H + +void kvm_riscv_reset_vcpu(RISCVCPU *cpu); + +#endif --=20 2.19.1 From nobody Sun May 5 17:47:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1584071731; cv=none; d=zohomail.com; s=zohoarc; b=dA8GE3Wu/qPcHYa3025/cesrUDhdH4cO9GZG57oH6baA7HWVXUg9au36gyUo/iTD9DHO7K3ajbP85QUWMvFREzKfuWG3yJEePECTS26FaLp8FR9AB2vXkuGJfxFUa67zu3u9+AVM8VtiEeo5xwDUg8KBO/58J/p6UVOVFSHXUBE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1584071731; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=v0mn08GuzRqnX2Xg4NOgmr3+kv/gL0VDoDyRZfsEw3Y=; b=NIC9pGGiF+ADNM8WLmLmWNE5Mzzt8zKuOIG4/JQVTjEutC+ctp3JW0AFFMStydVDcVBEKDw8m1rMXcedMZAtFuZ9O9zL4yQSKR9tKttbJ0wxw/5SPpM1cuXHJNJ9NTPBO8nfSBKZAHghyWXVMV7wPMHzsPyJ5N7xl11XC92eawU= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1584071731302248.29769491655804; Thu, 12 Mar 2020 20:55:31 -0700 (PDT) Received: from localhost ([::1]:53416 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jCbQ2-0004uq-8j for importer@patchew.org; Thu, 12 Mar 2020 23:55:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47883) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jCbMJ-0006tj-T5 for qemu-devel@nongnu.org; Thu, 12 Mar 2020 23:51:41 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jCbMI-0000dJ-Jp for qemu-devel@nongnu.org; Thu, 12 Mar 2020 23:51:39 -0400 Received: from szxga06-in.huawei.com ([45.249.212.32]:35016 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jCbMI-0000SK-71; Thu, 12 Mar 2020 23:51:38 -0400 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 96924BFA16C42F5E1A22; Fri, 13 Mar 2020 11:51:31 +0800 (CST) Received: from huawei.com (10.133.201.158) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.487.0; Fri, 13 Mar 2020 11:51:24 +0800 From: Yifei Jiang To: , Subject: [PATCH RFC 7/9] hw/riscv: PLIC update external interrupt by KVM when kvm enabled Date: Fri, 13 Mar 2020 11:49:47 +0800 Message-ID: <20200313034949.3028-8-jiangyifei@huawei.com> X-Mailer: git-send-email 2.23.0.windows.1 In-Reply-To: <20200313034949.3028-1-jiangyifei@huawei.com> References: <20200313034949.3028-1-jiangyifei@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.133.201.158] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.32 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: anup.patel@wdc.com, zhang.zhanghailiang@huawei.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, victor.zhangxiaofeng@huawei.com, Alistair.Francis@wdc.com, yinyipeng1@huawei.com, palmer@dabbelt.com, Yifei Jiang , dengkai1@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Only support supervisor external interrupt currently. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- hw/riscv/sifive_plic.c | 31 ++++++++++++++++++++++--------- target/riscv/kvm.c | 19 +++++++++++++++++++ target/riscv/kvm_riscv.h | 1 + 3 files changed, 42 insertions(+), 9 deletions(-) diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c index c1e04cbb98..ff5c18ed20 100644 --- a/hw/riscv/sifive_plic.c +++ b/hw/riscv/sifive_plic.c @@ -29,6 +29,8 @@ #include "target/riscv/cpu.h" #include "sysemu/sysemu.h" #include "hw/riscv/sifive_plic.h" +#include "sysemu/kvm.h" +#include "kvm_riscv.h" =20 #define RISCV_DEBUG_PLIC 0 =20 @@ -145,15 +147,26 @@ static void sifive_plic_update(SiFivePLICState *plic) continue; } int level =3D sifive_plic_irqs_pending(plic, addrid); - switch (mode) { - case PLICMode_M: - riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_MEIP, BOOL_TO_MASK(le= vel)); - break; - case PLICMode_S: - riscv_cpu_update_mip(RISCV_CPU(cpu), MIP_SEIP, BOOL_TO_MASK(le= vel)); - break; - default: - break; + if (kvm_enabled()) { + if (mode =3D=3D PLICMode_M) { + continue; + } +#ifdef CONFIG_KVM + kvm_riscv_set_irq(RISCV_CPU(cpu), IRQ_S_EXT, level); +#endif + } else { + switch (mode) { + case PLICMode_M: + riscv_cpu_update_mip(RISCV_CPU(cpu), + MIP_MEIP, BOOL_TO_MASK(level)); + break; + case PLICMode_S: + riscv_cpu_update_mip(RISCV_CPU(cpu), + MIP_SEIP, BOOL_TO_MASK(level)); + break; + default: + break; + } } } =20 diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index b9aec66b69..0f429fd802 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -440,3 +440,22 @@ void kvm_riscv_reset_vcpu(RISCVCPU *cpu) env->gpr[11] =3D cpu->env.fdt_start; /* a1 */ } =20 +void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level) +{ + int ret; + unsigned virq =3D level ? KVM_INTERRUPT_SET : KVM_INTERRUPT_UNSET; + + if (irq !=3D IRQ_S_EXT) { + return; + } + + if (!kvm_enabled()) { + return; + } + + ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_INTERRUPT, &virq); + if (ret < 0) { + perror("Set irq failed"); + abort(); + } +} diff --git a/target/riscv/kvm_riscv.h b/target/riscv/kvm_riscv.h index f38c82bf59..ed281bdce0 100644 --- a/target/riscv/kvm_riscv.h +++ b/target/riscv/kvm_riscv.h @@ -20,5 +20,6 @@ #define QEMU_KVM_RISCV_H =20 void kvm_riscv_reset_vcpu(RISCVCPU *cpu); +void kvm_riscv_set_irq(RISCVCPU *cpu, int irq, int level); =20 #endif --=20 2.19.1 From nobody Sun May 5 17:47:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1584071657; cv=none; d=zohomail.com; s=zohoarc; b=emxf/Kv5HxmRVQ2+sMaPpnXjHEBlA2yPzNt866hdMQpCpd1TM77BdYUafRwSG1aTiwROf0UtJvfUzUT4mSI32ref/MpFEBU37TWcObCU7+M1KkqYByYclgC1MhaxMS+TozzK4I2yOyWXyVMYXdIt7LFZleaIQoW6rfGkaGq6QKk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1584071657; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=htbLeYyAI5iuKcvprHwpVPGBzKClkNbj7Ga8F9L2xs4=; b=P9raN+aF+PG4kYug5p/7HtlWPkF2EDnHfE96/7g539mg5KmCLDOWRg0moUIOM0rVZoi3osKSPYvTnDe9Cb4nLEwvZ+jr7dSZhMwauxGE/b4a9nj+7KIcDnT0fLN8sUhP4vsNmx+xlGMZWMdPclpfv4N0ohTubTCzIJr/f8jEtnY= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1584071657537866.7191471916066; Thu, 12 Mar 2020 20:54:17 -0700 (PDT) Received: from localhost ([::1]:53402 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jCbOq-00038U-FX for importer@patchew.org; Thu, 12 Mar 2020 23:54:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47848) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jCbMJ-0006tf-9l for qemu-devel@nongnu.org; Thu, 12 Mar 2020 23:51:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jCbMH-0000bT-VH for qemu-devel@nongnu.org; Thu, 12 Mar 2020 23:51:39 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:3201 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jCbMH-0000SL-EM; Thu, 12 Mar 2020 23:51:37 -0400 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.58]) by Forcepoint Email with ESMTP id B2A68667E133AF381F94; Fri, 13 Mar 2020 11:51:31 +0800 (CST) Received: from huawei.com (10.133.201.158) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.487.0; Fri, 13 Mar 2020 11:51:25 +0800 From: Yifei Jiang To: , Subject: [PATCH RFC 8/9] target/riscv: Handler KVM_EXIT_RISCV_SBI exit Date: Fri, 13 Mar 2020 11:49:48 +0800 Message-ID: <20200313034949.3028-9-jiangyifei@huawei.com> X-Mailer: git-send-email 2.23.0.windows.1 In-Reply-To: <20200313034949.3028-1-jiangyifei@huawei.com> References: <20200313034949.3028-1-jiangyifei@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.133.201.158] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.190 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: anup.patel@wdc.com, zhang.zhanghailiang@huawei.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, victor.zhangxiaofeng@huawei.com, Alistair.Francis@wdc.com, yinyipeng1@huawei.com, palmer@dabbelt.com, Yifei Jiang , dengkai1@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Use char-fe handler console sbi call, which implement early console io while apply 'earlycon=3Dsbi' into kernel parameters. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/kvm.c | 54 +++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 53 insertions(+), 1 deletion(-) diff --git a/target/riscv/kvm.c b/target/riscv/kvm.c index 0f429fd802..1df70fbb29 100644 --- a/target/riscv/kvm.c +++ b/target/riscv/kvm.c @@ -38,6 +38,7 @@ #include "qemu/log.h" #include "hw/loader.h" #include "kvm_riscv.h" +#include "chardev/char-fe.h" =20 static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx) { @@ -61,6 +62,19 @@ static __u64 kvm_riscv_reg_id(__u64 type, __u64 idx) =20 #define RISCV_FP_D_REG(idx) kvm_riscv_reg_id(KVM_REG_RISCV_FP_D, idx) =20 +enum sbi_ext_id { + SBI_EXT_0_1_SET_TIMER =3D 0x0, + SBI_EXT_0_1_CONSOLE_PUTCHAR =3D 0x1, + SBI_EXT_0_1_CONSOLE_GETCHAR =3D 0x2, + SBI_EXT_0_1_CLEAR_IPI =3D 0x3, + SBI_EXT_0_1_SEND_IPI =3D 0x4, + SBI_EXT_0_1_REMOTE_FENCE_I =3D 0x5, + SBI_EXT_0_1_REMOTE_SFENCE_VMA =3D 0x6, + SBI_EXT_0_1_REMOTE_SFENCE_VMA_ASID =3D 0x7, + SBI_EXT_0_1_SHUTDOWN =3D 0x8, + SBI_EXT_BASE =3D 0x10, +}; + static int kvm_riscv_get_regs_core(CPUState *cs) { int ret =3D 0; @@ -423,9 +437,47 @@ bool kvm_arch_stop_on_emulation_error(CPUState *cs) return true; } =20 +static int kvm_riscv_handle_sbi(struct kvm_run *run) +{ + int ret =3D 0; + unsigned char ch; + switch (run->riscv_sbi.extension_id) { + case SBI_EXT_0_1_CONSOLE_PUTCHAR: + ch =3D run->riscv_sbi.args[0]; + qemu_chr_fe_write(serial_hd(0)->be, &ch, sizeof(ch)); + break; + case SBI_EXT_0_1_CONSOLE_GETCHAR: + ret =3D qemu_chr_fe_read_all(serial_hd(0)->be, &ch, sizeof(ch)); + if (ret =3D=3D sizeof(ch)) { + run->riscv_sbi.args[0] =3D ch; + } else { + run->riscv_sbi.args[0] =3D -1; + } + break; + default: + qemu_log_mask(LOG_UNIMP, + "%s: un-handled SBI EXIT, specific reasons is %lu\n", + __func__, run->riscv_sbi.extension_id); + ret =3D -1; + break; + } + return ret; +} + int kvm_arch_handle_exit(CPUState *cs, struct kvm_run *run) { - return 0; + int ret =3D 0; + switch (run->exit_reason) { + case KVM_EXIT_RISCV_SBI: + ret =3D kvm_riscv_handle_sbi(run); + break; + default: + qemu_log_mask(LOG_UNIMP, "%s: un-handled exit reason %d\n", + __func__, run->exit_reason); + ret =3D -1; + break; + } + return ret; } =20 void kvm_riscv_reset_vcpu(RISCVCPU *cpu) --=20 2.19.1 From nobody Sun May 5 17:47:36 2024 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1584071873; cv=none; d=zohomail.com; s=zohoarc; b=cAo3QV3igBikitNcJz+b0XTTql5BrdYa6q/1bvpML8J4Ff28HFbxa9YqEhv8ynGto5cVr9ZgkyXDKuyUm3vNWkwzc/KMLgIQbMuhQRT+fHeTQSFlNd2B+m/AcP1gMdolHWl/UWqRQ+20Ohift0RK7miNGSwh42cnp4QBEGDHSwc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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Thu, 12 Mar 2020 23:57:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47983) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jCbML-0006uR-Cp for qemu-devel@nongnu.org; Thu, 12 Mar 2020 23:51:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jCbMK-0000gU-6x for qemu-devel@nongnu.org; Thu, 12 Mar 2020 23:51:41 -0400 Received: from szxga04-in.huawei.com ([45.249.212.190]:3202 helo=huawei.com) by eggs.gnu.org with esmtps (TLS1.0:DHE_RSA_AES_256_CBC_SHA1:32) (Exim 4.71) (envelope-from ) id 1jCbMJ-0000Za-RH; Thu, 12 Mar 2020 23:51:40 -0400 Received: from DGGEMS413-HUB.china.huawei.com (unknown [172.30.72.60]) by Forcepoint Email with ESMTP id 8BC5E364828BCADEAA05; Fri, 13 Mar 2020 11:51:36 +0800 (CST) Received: from huawei.com (10.133.201.158) by DGGEMS413-HUB.china.huawei.com (10.3.19.213) with Microsoft SMTP Server id 14.3.487.0; Fri, 13 Mar 2020 11:51:25 +0800 From: Yifei Jiang To: , Subject: [PATCH RFC 9/9] target/riscv: add host riscv64 cpu type Date: Fri, 13 Mar 2020 11:49:49 +0800 Message-ID: <20200313034949.3028-10-jiangyifei@huawei.com> X-Mailer: git-send-email 2.23.0.windows.1 In-Reply-To: <20200313034949.3028-1-jiangyifei@huawei.com> References: <20200313034949.3028-1-jiangyifei@huawei.com> MIME-Version: 1.0 X-Originating-IP: [10.133.201.158] X-CFilter-Loop: Reflected Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 45.249.212.190 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: anup.patel@wdc.com, zhang.zhanghailiang@huawei.com, sagark@eecs.berkeley.edu, kbastian@mail.uni-paderborn.de, victor.zhangxiaofeng@huawei.com, Alistair.Francis@wdc.com, yinyipeng1@huawei.com, palmer@dabbelt.com, Yifei Jiang , dengkai1@huawei.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Content-Type: text/plain; charset="utf-8" Currently, host cpu is inherited simply. Signed-off-by: Yifei Jiang Signed-off-by: Yipeng Yin --- target/riscv/cpu.c | 5 +++++ target/riscv/cpu.h | 1 + 2 files changed, 6 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3c3264869f..11557719cf 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -203,6 +203,10 @@ static void rv64imacu_nommu_cpu_init(Object *obj) set_feature(env, RISCV_FEATURE_PMP); } =20 +static void riscv_host_cpu_init(Object *obj) +{ +} + #endif =20 static ObjectClass *riscv_cpu_class_by_name(const char *cpu_model) @@ -622,6 +626,7 @@ static const TypeInfo riscv_cpu_type_infos[] =3D { DEFINE_CPU(TYPE_RISCV_CPU_BASE64, riscv_base64_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_in= it), + DEFINE_CPU(TYPE_RISCV_CPU_HOST, riscv_host_cpu_init), /* Deprecated */ DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init), DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_in= it), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2724eca714..10b053a467 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -39,6 +39,7 @@ #define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51") #define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34") #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") +#define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") /* Deprecated */ #define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nom= mu") #define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9= .1") --=20 2.19.1