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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id g69sm6824842pje.34.2020.03.12.12.43.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2020 12:43:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D6dUTV6+AbmOvovc5B167VTVViwAF6biFLlOzA9HmSw=; b=e09oKrAdsRYr04MKQUlFO5Sqre3QYt0so/zB/TKS5uGXJhsG6oOYeV7w+jgh5Y62Lm I//ZEHwflheAWSAxD8k+NuOx8a2NbefPHvR1uQGSDQh9SPObQtbjp+osr2MIT3T73/4X kCg72AenLxeDqJ4LAMGUnnKpQA9LdegM2cAAuMHnW/3wi6bee2ocaZuhXVV6nK+GTtNm BqB4lzAmezWoeC/GAjhoGbblxnFeHnrZy1NjmKTtdJwKktoCcaFStfNgnapjKM9lpmd0 bRCJuzjeyPs+oyKiwfYbszRwc0ZT0iKX6Innswx5xCPMOd5b573cvaSCUHY/Ya957npe W05Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D6dUTV6+AbmOvovc5B167VTVViwAF6biFLlOzA9HmSw=; b=ujb3RzujdRBRk292qynfO9xHs5GZRWnpNNOaIQmfUIOlXOAQeN+Udpi7NNmK/Lqr6z d2Hj4bCUHu5zGSbVRhWKusc8pNmJ3Z1gz5nXd9MmxIKSeyH6aAZh/vT23ys2sv4e+Yp6 545ep9erOz98yCSU/Nta+K4DeDZLDrnWZWaijz3yKAR+uKUf8rVk4h4pjVcWdZTK6JET wNJDDKfdydjV+Wc5WqrcspH4wtnV07bj+/491ulq0XFX14+baAUEn0QEI5Y/yUgtMoIZ N+2PJreXN0nNa64sfRhgEqqTaF5cEpttYviE2glBCkwIwv2ChREy0mygX8dr0OpBrDGS oJ1g== X-Gm-Message-State: ANhLgQ0E2Q68pPheJ3YVIFbppi8/4dVlsdPCbxzzUYmaTMTeL1E7eyO8 96lNnfp922CONS3t9Vo9/ljHApyIm00= X-Google-Smtp-Source: ADFU+vuBH+RPEBGPrZa1p2Vs6VHSN6g4Zif2yEuU7dsc48h3upM17JSgGj4hBgX89AK3TeDaLTHS/w== X-Received: by 2002:a17:902:8a88:: with SMTP id p8mr10026309plo.56.1584042197603; Thu, 12 Mar 2020 12:43:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 42/42] target/arm: Add allocation tag storage for system mode Date: Thu, 12 Mar 2020 12:42:19 -0700 Message-Id: <20200312194219.24406-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200312194219.24406-1-richard.henderson@linaro.org> References: <20200312194219.24406-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::643 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Look up the physical address for the given virtual address, convert that to a tag physical address, and finally return the host address that backs it. Signed-off-by: Richard Henderson --- target/arm/mte_helper.c | 128 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 128 insertions(+) diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index c51f7f04f4..47db87a5a1 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -21,6 +21,7 @@ #include "cpu.h" #include "internals.h" #include "exec/exec-all.h" +#include "exec/ram_addr.h" #include "exec/cpu_ldst.h" #include "exec/helper-proto.h" =20 @@ -74,8 +75,135 @@ static uint8_t *allocation_tag_mem(CPUARMState *env, in= t ptr_mmu_idx, int ptr_size, MMUAccessType tag_access, int tag_size, uintptr_t ra) { +#ifdef CONFIG_USER_ONLY /* Tag storage not implemented. */ return NULL; +#else + uintptr_t index; + CPUIOTLBEntry *iotlbentry; + int in_page, flags; + ram_addr_t ptr_ra; + hwaddr ptr_paddr, tag_paddr, xlat; + MemoryRegion *mr; + ARMASIdx tag_asi; + AddressSpace *tag_as; + void *host; + + /* + * The caller must split calls to this function such that it will + * not access *tag* memory beyond the end of the page. + */ + in_page =3D -(ptr | -(TARGET_PAGE_SIZE >> (LOG2_TAG_GRANULE + 1))); + g_assert(tag_size <=3D in_page); + + /* + * Probe the first byte of the virtual address. This raises an + * exception for inaccessible pages, and resolves the virtual address + * into the softmmu tlb. + */ + flags =3D probe_access_flags(env, ptr, ptr_access, ptr_mmu_idx, + false, &host, ra); + + /* + * Find the iotlbentry for ptr. This *must* be present in the TLB + * because we just found the mapping. + * TODO: Perhaps there should be a cputlb helper that returns a + * matching tlb entry + iotlb entry. + */ + index =3D tlb_index(env, ptr_mmu_idx, ptr); +# ifdef CONFIG_DEBUG_TCG + { + CPUTLBEntry *entry =3D tlb_entry(env, ptr_mmu_idx, ptr); + target_ulong comparator =3D (ptr_access =3D=3D MMU_DATA_LOAD + ? entry->addr_read + : tlb_addr_write(entry)); + g_assert(tlb_hit(comparator, ptr)); + } +# endif + iotlbentry =3D &env_tlb(env)->d[ptr_mmu_idx].iotlb[index]; + + /* If the virtual page MemAttr !=3D Tagged, access unchecked. */ + if (!iotlbentry->attrs.target_tlb_bit1) { + return NULL; + } + + /* If not normal memory, tag storage is not implemented, access unchec= ked. */ + if (unlikely(flags & TLB_MMIO)) { + qemu_log_mask(LOG_GUEST_ERROR, + "Page @ 0x%" PRIx64 " indicates Tagged Normal memory= " + "but is Device memory\n", ptr); + return NULL; + } + + /* + * The Normal memory access can extend to the next page. E.g. a single + * 8-byte access to the last byte of a page will check only the last + * tag on the first page. + * Any page access exception has priority over tag check exception. + */ + in_page =3D -(ptr | TARGET_PAGE_MASK); + if (unlikely(ptr_size > in_page)) { + void *ignore; + flags |=3D probe_access_flags(env, ptr + in_page, ptr_access, + ptr_mmu_idx, false, &ignore, ra); + } + + /* Any debug exception has priority over a tag check exception. */ + if (unlikely(flags & TLB_WATCHPOINT)) { + int wp =3D ptr_access =3D=3D MMU_DATA_LOAD ? BP_MEM_READ : BP_MEM_= WRITE; + cpu_check_watchpoint(env_cpu(env), ptr, ptr_size, + iotlbentry->attrs, wp, ra); + } + + /* + * Find the physical address within the normal mem space. + * The memory region lookup must succeed because TLB_MMIO was + * not set in the cputlb lookup above. + */ + mr =3D memory_region_from_host(host, &ptr_ra); + tcg_debug_assert(mr !=3D NULL); + tcg_debug_assert(memory_region_is_ram(mr)); + ptr_paddr =3D ptr_ra; + do { + ptr_paddr +=3D mr->addr; + mr =3D mr->container; + } while (mr); + + /* Convert to the physical address in tag space. */ + tag_paddr =3D ptr_paddr >> (LOG2_TAG_GRANULE + 1); + + /* Look up the address in tag space. */ + tag_asi =3D iotlbentry->attrs.secure ? ARMASIdx_TagS : ARMASIdx_TagNS; + tag_as =3D cpu_get_address_space(env_cpu(env), tag_asi); + mr =3D address_space_translate(tag_as, tag_paddr, &xlat, NULL, + tag_access =3D=3D MMU_DATA_STORE, + iotlbentry->attrs); + + /* + * Note that @mr will never be NULL. If there is nothing in the addre= ss + * space at @tag_paddr, the translation will return the unallocated me= mory + * region. For our purposes, the result must be ram. + */ + if (unlikely(!memory_region_is_ram(mr))) { + /* ??? Failure is a board configuration error. */ + qemu_log_mask(LOG_UNIMP, + "Tag Memory @ 0x%" HWADDR_PRIx " not found for " + "Normal Memory @ 0x%" HWADDR_PRIx "\n", + tag_paddr, ptr_paddr); + return NULL; + } + + /* + * Ensure the tag memory is dirty on write, for migration. + * Tag memory can never contain code or display memory (vga). + */ + if (tag_access =3D=3D MMU_DATA_STORE) { + ram_addr_t tag_ra =3D memory_region_get_ram_addr(mr) + xlat; + cpu_physical_memory_set_dirty_flag(tag_ra, DIRTY_MEMORY_MIGRATION); + } + + return memory_region_get_ram_ptr(mr) + xlat; +#endif } =20 uint64_t HELPER(irg)(CPUARMState *env, uint64_t rn, uint64_t rm) --=20 2.20.1