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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id g69sm6824842pje.34.2020.03.12.12.43.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2020 12:43:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FqxgWRxNaOrIo80/rd7EvP+ZqoigJ+ge9JbM5ILrh50=; b=K/7RAi1QturA2wu+mnUAiJRDSFP6ttUS8ps8kO5kEbQcYbkkfdpiLl/sqCvp1CffMB LXFC1b95ipYR3Iq0L7trKv1BI7MZyioDSvX8Y6druJ6mBm5Sq5TEkH1QXM8ORL4b5iZg TX6vpF8s4RzuzRA2nYUO3zWV13axJExKtOEKTYqOxrSbOtzwH5lWZTlehNHJ3uJ+WRtr h3jEC/pptA3Zo4ME6xJ1gaEKbslG30rDF6Emp3yPr5MOQULRunwUSRyqSacJOR8Og4Tf ZMM2Zl6NC16F23k5rhMzU3aWodvdAPgA3Jn9NeC07HhHYo+Tem8iN/WO7+f8u2daSKEE mX6A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FqxgWRxNaOrIo80/rd7EvP+ZqoigJ+ge9JbM5ILrh50=; b=S4kO/SFhd+G+YuNrRQWZAeA6Wcs04QKPzUvWSKTkuEy/lKaY6jJvhJB/FiGq2DB3Ph hxhTEBV1BD8bsa555KSzq7RdoOIPm9Sd65L/OAHcD2MkKhG05/W334aAvEQMHltG8nng RBY0elHy5reBCpkZQAZzalTxWiTeKI+HzEmAPnsIHQHCRMDVIbetlaZjgxEuurFs6OLt AoLR34Iey3euvFiWSr8zFoR/p650zsiQkbwa944Y1lfg3nliws3D9B914I2u3PemwXC0 ly3zeL1VdpMyakDiWdgYiObuIdG9eqKUgJKeg2gala/NcUy4BfIdYROvXOJ8TlPo41x5 RdVg== X-Gm-Message-State: ANhLgQ2UzU5Ay6FBFhO585JtB/MLdBUcLFG+Jz3KPK5jFjdq8p/OPsO9 CrjokRBcbJbxQwAuQSx5jgtXPbpQOdw= X-Google-Smtp-Source: ADFU+vudl2xEsP4dZjy2/5sVwRI0ebMp0Qk63/29HruLoZaWbdQSyiterXbB8FatlHplsY7/5CcSzw== X-Received: by 2002:a17:902:7298:: with SMTP id d24mr9600552pll.134.1584042194660; Thu, 12 Mar 2020 12:43:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 40/42] target/arm: Cache the Tagged bit for a page in MemTxAttrs Date: Thu, 12 Mar 2020 12:42:17 -0700 Message-Id: <20200312194219.24406-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200312194219.24406-1-richard.henderson@linaro.org> References: <20200312194219.24406-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::1044 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This "bit" is a particular value of the page's MemAttr. Signed-off-by: Richard Henderson --- v6: Test HCR_EL2.{DC,DCT}; test Stage2 attributes. --- target/arm/helper.c | 43 +++++++++++++++++++++++++++++++++++-------- 1 file changed, 35 insertions(+), 8 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index b38dc74733..c272c48467 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10785,6 +10785,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, ta= rget_ulong address, uint64_t descaddrmask; bool aarch64 =3D arm_el_is_aa64(env, el); bool guarded =3D false; + uint8_t memattr; =20 /* TODO: * This code does not handle the different format TCR for VTCR_EL2. @@ -11013,17 +11014,32 @@ static bool get_phys_addr_lpae(CPUARMState *env, = target_ulong address, txattrs->target_tlb_bit0 =3D true; } =20 - if (cacheattrs !=3D NULL) { + if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { + memattr =3D convert_stage2_attrs(env, extract32(attrs, 0, 4)); + } else { + /* Index into MAIR registers for cache attributes */ + uint64_t mair =3D env->cp15.mair_el[el]; + memattr =3D extract64(mair, extract32(attrs, 0, 3) * 8, 8); + } + + /* When MTE is enabled, remember Tagged Memory in IOTLB. */ + if (aarch64 && cpu_isar_feature(aa64_mte, cpu)) { if (mmu_idx =3D=3D ARMMMUIdx_Stage2) { - cacheattrs->attrs =3D convert_stage2_attrs(env, - extract32(attrs, 0, 4= )); + /* + * Require Normal, I+O Shareable, WB, NT, RA, WA (0xff). + * If not, squash stage1 tagged normal setting. + */ + if (memattr !=3D 0xff) { + txattrs->target_tlb_bit1 =3D false; + } } else { - /* Index into MAIR registers for cache attributes */ - uint8_t attrindx =3D extract32(attrs, 0, 3); - uint64_t mair =3D env->cp15.mair_el[regime_el(env, mmu_idx)]; - assert(attrindx <=3D 7); - cacheattrs->attrs =3D extract64(mair, attrindx * 8, 8); + /* Tagged Normal Memory (0xf0). */ + txattrs->target_tlb_bit1 =3D (memattr =3D=3D 0xf0); } + } + + if (cacheattrs !=3D NULL) { + cacheattrs->attrs =3D memattr; cacheattrs->shareability =3D extract32(attrs, 6, 2); } =20 @@ -11978,6 +11994,17 @@ bool get_phys_addr(CPUARMState *env, target_ulong = address, *phys_ptr =3D address; *prot =3D PAGE_READ | PAGE_WRITE | PAGE_EXEC; *page_size =3D TARGET_PAGE_SIZE; + + /* Stage1 translations are Tagged or Untagged based on HCR_DCT. */ + if (cpu_isar_feature(aa64_mte, env_archcpu(env)) + && (mmu_idx =3D=3D ARMMMUIdx_Stage1_E0 || + mmu_idx =3D=3D ARMMMUIdx_Stage1_E1 || + mmu_idx =3D=3D ARMMMUIdx_Stage1_E1_PAN)) { + uint64_t hcr =3D arm_hcr_el2_eff(env); + if ((hcr & (HCR_DC | HCR_DCT)) =3D=3D (HCR_DC | HCR_DCT)) { + attrs->target_tlb_bit1 =3D true; + } + } return 0; } =20 --=20 2.20.1