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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id g69sm6824842pje.34.2020.03.12.12.43.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2020 12:43:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7tXXL1aIZa+UtCbjnv5unnvpKSgUfOHdhgWj90HH058=; b=HZ3J9BIFMbH7FTKw2xECHChtcI/vfAPmLedYZgT7AaIastMiLWoLzpNsDA8DAdtjag yFAuH2ei1xRkSMGW2HDGnjXKLkquL9K4St1Ow5O0l9U8Z7Rf10ACMv6Zswy7W7Indbgf 2yqm8EwQIWxAfFa+lIVEHcjJQDp04LTPkxgMxNQjCOqsMtz5Y/kydTGJ0UKiFqruaeNe D1swpVBdQyyVVGplkmmTnjb78/sWKdXltVBJvDDYEAfy+S3HQo5SLOJ9TWyDgDhPHiad 1qHCmfug6qyasfyFxAsW6n1I6PLxPL5gcdKQHFUpvmnhMgJlrOwqJBH+uNrRTAyunbwD Wy3g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7tXXL1aIZa+UtCbjnv5unnvpKSgUfOHdhgWj90HH058=; b=DgOOx1PC2aRQOiM/aI2ByBUGYIDHd12LCRhxyvxuMqj+ayyLMglAsJtYln2wqH420Y qmZgn4XdVYzxBHNpC1Ik1JesKEr/nQUN5rt720/qJ05kUEjPTa62r7h4ml/54Qkqx0J3 3s8ZXyeAb341YabZazaqfYM8Czf/cg3WNVrQI8fO6Lufll959ZmB0VJV11Yj4dYZM2ma DWaRbzE+JQAMY0hrhK37gwhMl+3EdnpQ/KnSUsVOZ8Dou6f5kie0HWyfkQXELCRoCenm gyC2oO0gboQKf6Pp9M0lYFrJaG50IEFvdiSwuf74T/5592V0+GO3aSXCeNL5+cAQGUUO 2AyA== X-Gm-Message-State: ANhLgQ06xKeS/TuaahlTiPVfFFEzJM1HVSJ2edMW9xaWm6WfWMtw1tc2 TL53fh8EtBJo96OEGqtve4WhgtybRjM= X-Google-Smtp-Source: ADFU+vuSgUUQzkGrrD8l/QTXUUUK3o1dEQ2IFGMXMGIop4GeZcgOdNNmzRqQPG1UGD9EYabTqjCQMA== X-Received: by 2002:a17:902:694c:: with SMTP id k12mr9427834plt.329.1584042190805; Thu, 12 Mar 2020 12:43:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 37/42] target/arm: Implement data cache set allocation tags Date: Thu, 12 Mar 2020 12:42:14 -0700 Message-Id: <20200312194219.24406-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200312194219.24406-1-richard.henderson@linaro.org> References: <20200312194219.24406-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::642 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" This is DC GVA and DC GZVA, and the tag check for DC ZVA. Signed-off-by: Richard Henderson --- v2: Use allocation_tag_mem + memset. v3: Require pre-cleaned addresses. v6: Move DCZ block size assert to cpu realize. Perform a tag check for DC ZVA. --- target/arm/cpu.h | 4 +++- target/arm/helper.c | 16 ++++++++++++++++ target/arm/translate-a64.c | 39 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 58 insertions(+), 1 deletion(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 67164d56a1..b78bf2be4a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2337,7 +2337,9 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpreg= id) #define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) #define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) #define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) -#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA +#define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600) +#define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700) +#define ARM_LAST_SPECIAL ARM_CP_DC_GZVA #define ARM_CP_FPU 0x1000 #define ARM_CP_SVE 0x2000 #define ARM_CP_NO_GDB 0x4000 diff --git a/target/arm/helper.c b/target/arm/helper.c index e4b4366af7..44e7c0d19b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6983,6 +6983,22 @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = =3D { .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 14, .opc2 =3D 5, .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D aa64_cacheop_poc_access }, + { .name =3D "DC_GVA", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 4, .opc2 =3D 3, + .access =3D PL0_W, .type =3D ARM_CP_DC_GVA, +#ifndef CONFIG_USER_ONLY + /* Avoid overhead of an access check that always passes in user-mode= */ + .accessfn =3D aa64_zva_access, +#endif + }, + { .name =3D "DC_GZVA", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 4, .opc2 =3D 4, + .access =3D PL0_W, .type =3D ARM_CP_DC_GZVA, +#ifndef CONFIG_USER_ONLY + /* Avoid overhead of an access check that always passes in user-mode= */ + .accessfn =3D aa64_zva_access, +#endif + }, REGINFO_SENTINEL }; =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 1314b200e0..f33f174584 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1919,6 +1919,45 @@ static void handle_sys(DisasContext *s, uint32_t ins= n, bool isread, } gen_helper_dc_zva(cpu_env, tcg_rt); return; + case ARM_CP_DC_GVA: + { + TCGv_i64 clean_addr, tag; + + /* + * DC_GVA, like DC_ZVA, requires that we supply the original + * pointer for an invalid page. Probe that address first. + */ + tcg_rt =3D cpu_reg(s, rt); + clean_addr =3D clean_data_tbi(s, tcg_rt); + gen_probe_access(s, clean_addr, MMU_DATA_STORE, MO_8); + + if (s->ata) { + /* Extract the tag from the register to match STZGM. */ + tag =3D tcg_temp_new_i64(); + tcg_gen_shri_i64(tag, tcg_rt, 56); + gen_helper_stzgm_tags(cpu_env, clean_addr, tag); + tcg_temp_free_i64(tag); + } + } + return; + case ARM_CP_DC_GZVA: + { + TCGv_i64 clean_addr, tag; + + /* For DC_GZVA, we can rely on DC_ZVA for the proper fault. */ + tcg_rt =3D cpu_reg(s, rt); + clean_addr =3D clean_data_tbi(s, tcg_rt); + gen_helper_dc_zva(cpu_env, clean_addr); + + if (s->ata) { + /* Extract the tag from the register to match STZGM. */ + tag =3D tcg_temp_new_i64(); + tcg_gen_shri_i64(tag, tcg_rt, 56); + gen_helper_stzgm_tags(cpu_env, clean_addr, tag); + tcg_temp_free_i64(tag); + } + } + return; default: break; } --=20 2.20.1