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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id g69sm6824842pje.34.2020.03.12.12.42.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2020 12:42:23 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rGpxLm79CCdrNbLq46EhVbUpI55c0cfdmX2p0AxkOgU=; b=maOYaX3+B9tNyub/KhSP8AclpZeniqojXcZkHxnY3XmvWUR23nXZm2ZY/UCMhSfyUo uZt1om1FYgtxoaOtBizkswF2S4u2Vb644HxciOjxh/3JPTO0blJjUmcJG77w9fCU9+I9 pKp6cumbkSGkWqLHzSZRrxLmP10BUGbeY4AN4dHD/Pqldk/EJiXw81+5Yk/0bQcXnTJ8 n3VdHtAXuddMi9bZHWePe0vW7pyIiqG6YOUJjJSRJZhEZhh/mNhbyQpLJIbu4jTlMG4B bLO1/FBHGwJMw27+7L84PufVWfCblzOpm5wcNdyblBFM4gNSyq+tkYaI0pZtv6wegVDm 6Ssg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rGpxLm79CCdrNbLq46EhVbUpI55c0cfdmX2p0AxkOgU=; b=kRaQavoY71jy5x7ZVfsGSvOwab4F6608UkeD4v0Yh8BHFWJwcnH7/Cgl2TRUpFM7KZ es4/6p++TnGM4doYzY7LkfEidY311ejLPTfKjr9n6Bg6yAgq9ywLSStgBEayt96621UZ iiM8hQo1jvuqncLp8z872dUg2aL4Fl3k3blwaAJReSSEHJ9t7Gdb2PJmUUS5iCjouVXH j62VrOt2ByzUq9UEyKahfYkFhFYNg1CoQacha+9i5I/70XCFmkuptMTAu48PgfQDgkvu EyMrLY341xCY/dvH3HQH92owFFUEOn7caeFcTJStK6RHXIByP6dZMCLCdHg/+HFAeJTw zfyw== X-Gm-Message-State: ANhLgQ2Y0jE33wyfEdOASV7+lNmDskx9w1UyW9xD9+fx9na/fUCh7/gu 74FlNpSrX1s55yAQslHdixTj+F5MQrw= X-Google-Smtp-Source: ADFU+vubA8FNHNaedG9rokcg0Goayg7BEHMdZicUkQpwfspkEmMMVuNj2hbwlC1y88XIE3eraDmmiQ== X-Received: by 2002:a17:90a:6545:: with SMTP id f5mr5984646pjs.42.1584042143854; Thu, 12 Mar 2020 12:42:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 02/42] target/arm: Improve masking of SCR RES0 bits Date: Thu, 12 Mar 2020 12:41:39 -0700 Message-Id: <20200312194219.24406-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200312194219.24406-1-richard.henderson@linaro.org> References: <20200312194219.24406-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::641 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Protect reads of aa64 id registers with ARM_CP_STATE_AA64. Use this as a simpler test than arm_el_is_aa64, since EL3 cannot change mode. Signed-off-by: Richard Henderson --- target/arm/helper.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8f81ca4f54..d04fc0a140 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1966,9 +1966,16 @@ static void scr_write(CPUARMState *env, const ARMCPR= egInfo *ri, uint64_t value) uint32_t valid_mask =3D 0x3fff; ARMCPU *cpu =3D env_archcpu(env); =20 - if (arm_el_is_aa64(env, 3)) { + if (ri->state =3D=3D ARM_CP_STATE_AA64) { value |=3D SCR_FW | SCR_AW; /* these two bits are RES1. */ valid_mask &=3D ~SCR_NET; + + if (cpu_isar_feature(aa64_lor, cpu)) { + valid_mask |=3D SCR_TLOR; + } + if (cpu_isar_feature(aa64_pauth, cpu)) { + valid_mask |=3D SCR_API | SCR_APK; + } } else { valid_mask &=3D ~(SCR_RW | SCR_ST); } @@ -1987,12 +1994,6 @@ static void scr_write(CPUARMState *env, const ARMCPR= egInfo *ri, uint64_t value) valid_mask &=3D ~SCR_SMD; } } - if (cpu_isar_feature(aa64_lor, cpu)) { - valid_mask |=3D SCR_TLOR; - } - if (cpu_isar_feature(aa64_pauth, cpu)) { - valid_mask |=3D SCR_API | SCR_APK; - } =20 /* Clear all-context RES0 bits. */ value &=3D valid_mask; --=20 2.20.1