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[97.126.123.70]) by smtp.gmail.com with ESMTPSA id g69sm6824842pje.34.2020.03.12.12.42.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2020 12:42:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4Zgn64d07+UFzKhr0znCC5cl8O2aEpkp4d53c1uLaxI=; b=jSBRRxdFx+8H7x7rxYfvZ+OBGlY65h3RHatJGFXfY/oPdNmoXB7G4wyXBQgNb3T3AD 6yI7wAFLBVLYMiWpfNx+8lP1Bpsxh97hSg7lr8ELG1tZ8kUZo/InEx/+l0oYezUMzkvH 8d9ZWDgys5sWHjqGqWtHmMKilXiXYT2OaNbXJXCFbMh+aMqXbzZOTeG0pc0LrD+y9kG+ j9efijfKsK+hamb7XXHq7/7S6z72acAy6fDxRFSNxPgRlsuwoUAQI59tf6bRoGleJQp5 VLGRkptRIHyuOYFS6Wfpd9SWLmRFtFP2iGn5C6Cn4H1JUcQ+3Wc7uXvZRw9B5ccDJi7n Hspg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4Zgn64d07+UFzKhr0znCC5cl8O2aEpkp4d53c1uLaxI=; b=bLg/mc8h22HB8KK4nuYrBfR/Qpxn+fGiWcnlhy1QXAV8UhWUdtptIDISsooRuBHnA8 2YfqXjE2ZRPyX8K8l3FvG15Zz9ZzbqYrGd6K0hv+MkU822lDGRNxiquuj6coiseNYF+y iTtgJ7aO7dtVWbo9eGNkVEa9byf48RxEMm9kCo0sy1aHah76DzEXZQbssGXMZCd5+/K+ f4gTMvWtNWQkVJj4/jO/pSMzpWKz0R6AIpmrOei885tjIB0JANt9YNjXtF69AxANVJaJ 8O1Opto5zv1+cQ1CjQoGglEAoiJBD5q4osQEKcTerCD9attpqAg4XAn4KkmIS0XJD49V oRPw== X-Gm-Message-State: ANhLgQ2SVkmbCJveSunXZ4usw93GbZsEuXNdSyUzeWgH4j285pVrbqS6 Cw4hlkrbfhEgPTO1aoV9lgL44hVqo1k= X-Google-Smtp-Source: ADFU+vs8j4jzwLyPg5SZ3pMX1ji1pqwWtB7zLIP19HAmKvcBYC7C7C+8dZR4y2QDxjIMrZ5E1U3c1g== X-Received: by 2002:aa7:98c9:: with SMTP id e9mr9587574pfm.204.1584042178425; Thu, 12 Mar 2020 12:42:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 28/42] target/arm: Use mte_checkN for sve unpredicated loads Date: Thu, 12 Mar 2020 12:42:05 -0700 Message-Id: <20200312194219.24406-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200312194219.24406-1-richard.henderson@linaro.org> References: <20200312194219.24406-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::434 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/helper-sve.h | 2 + target/arm/sve_helper.c | 74 ++++++++++++++++++++++++++++-- target/arm/translate-sve.c | 93 ++++++++++++++++---------------------- 3 files changed, 110 insertions(+), 59 deletions(-) diff --git a/target/arm/helper-sve.h b/target/arm/helper-sve.h index 2f47279155..82ea70cf63 100644 --- a/target/arm/helper-sve.h +++ b/target/arm/helper-sve.h @@ -1123,6 +1123,8 @@ DEF_HELPER_FLAGS_5(sve_ftmad_h, TCG_CALL_NO_RWG, void= , ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sve_ftmad_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) DEF_HELPER_FLAGS_5(sve_ftmad_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) =20 +DEF_HELPER_FLAGS_4(sve_ldr, TCG_CALL_NO_WG, void, env, ptr, tl, int) + DEF_HELPER_FLAGS_4(sve_ld1bb_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) DEF_HELPER_FLAGS_4(sve_ld2bb_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) DEF_HELPER_FLAGS_4(sve_ld3bb_r, TCG_CALL_NO_WG, void, env, ptr, tl, i32) diff --git a/target/arm/sve_helper.c b/target/arm/sve_helper.c index 80453953ad..ede72a2989 100644 --- a/target/arm/sve_helper.c +++ b/target/arm/sve_helper.c @@ -3967,10 +3967,6 @@ void HELPER(sve_fcmla_zpzzz_d)(CPUARMState *env, voi= d *vg, uint32_t desc) } while (i !=3D 0); } =20 -/* - * Load contiguous data, protected by a governing predicate. - */ - /* * Load elements into @vd + @reg_off, from @host, * or the reverse for stores. @@ -4194,6 +4190,76 @@ static bool sve_probe_page(SVEHostPage *info, bool n= ofault, return true; } =20 +/* + * Load contiguous data, unpredicated. + * + * Note that unpredicated load/store of vector/predicate registers + * are defined as a stream of bytes, which equates to little-endian + * operations on larger quantities. + * + * Note any MTE check is already handled. + */ + +void HELPER(sve_ldr)(CPUARMState *env, void *vd, target_ulong addr, int si= ze) +{ + int mmu_idx =3D cpu_mmu_index(env, false); + int in_page =3D -((int)addr | TARGET_PAGE_MASK); + uintptr_t ra =3D GETPC(); + uint64_t val; + int i; + + /* Small loads are expanded inline. */ + tcg_debug_assert(size > 2 * 8); + + /* Bulk copy the data from memory to the register. */ + if (likely(size <=3D in_page)) { + void *host =3D probe_read(env, addr, size, mmu_idx, ra); + + if (unlikely(!host)) { + goto mmio; + } + memcpy(vd, host, size); + } else { + void *h1 =3D probe_read(env, addr, in_page, mmu_idx, ra); + void *h2 =3D probe_read(env, addr + in_page, size - in_page, mmu_i= dx, ra); + + if (unlikely(!h1 || !h2)) { + goto mmio; + } + memcpy(vd, h1, in_page); + memcpy(vd + in_page, h2, size - in_page); + } + + /* Predicate load length may be any multiple of 2; ensure high bits 0.= */ + if (unlikely(size & 7)) { + memset(vd + size, 0, 8 - (size & 7)); + } + + /* + * The memcpy and memset above kept the bytes in memory order. + * The in-register format has uint64_t in host order, so for + * big-endian host we need to bswap. + */ + for (i =3D 0; i < size; i +=3D 8) { + le64_to_cpus(vd + i); + } + return; + + mmio: + for (i =3D 0; i + 8 <=3D size; i +=3D 8) { + val =3D cpu_ldq_data_ra(env, addr + i, ra); + val =3D le_bswap64(val); + *(uint64_t *)(vd + i) =3D val; + } + + /* Predicate load length may be any multiple of 2. */ + if (unlikely(i !=3D size)) { + val =3D cpu_ldq_data_ra(env, addr + i, ra); + val =3D le_bswap64(val); + val >>=3D (size - i) * 8; + *(uint64_t *)(vd + i + 8) =3D val; + } +} =20 /* * Analyse contiguous data, protected by a governing predicate. diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 7bd7de80e6..e55f8835bb 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4352,8 +4352,13 @@ static bool trans_UCVTF_dd(DisasContext *s, arg_rpr_= esz *a) *** SVE Memory - 32-bit Gather and Unsized Contiguous Group */ =20 -/* Subroutine loading a vector register at VOFS of LEN bytes. +/* + * Subroutine loading a vector register at VOFS of LEN bytes. * The load should begin at the address Rn + IMM. + * + * Note that unpredicated load/store of vector/predicate registers + * are defined as a stream of bytes, which equates to little-endian + * operations on larger quantities. */ =20 static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int im= m) @@ -4362,81 +4367,59 @@ static void do_ldr(DisasContext *s, uint32_t vofs, = int len, int rn, int imm) int len_remain =3D len % 8; int nparts =3D len / 8 + ctpop8(len_remain); int midx =3D get_mem_index(s); - TCGv_i64 addr, t0, t1; + TCGv_i64 dirty_addr, clean_addr, t0, t1; + int i; =20 - addr =3D tcg_temp_new_i64(); - t0 =3D tcg_temp_new_i64(); + dirty_addr =3D read_cpu_reg_sp(s, rn, true); + tcg_gen_addi_i64(dirty_addr, dirty_addr, imm); =20 - /* Note that unpredicated load/store of vector/predicate registers - * are defined as a stream of bytes, which equates to little-endian - * operations on larger quantities. There is no nice way to force - * a little-endian load for aarch64_be-linux-user out of line. - * - * Attempt to keep code expansion to a minimum by limiting the - * amount of unrolling done. - */ - if (nparts <=3D 4) { - int i; + clean_addr =3D gen_mte_checkN(s, dirty_addr, false, rn !=3D 31, len, M= O_8); =20 - for (i =3D 0; i < len_align; i +=3D 8) { - tcg_gen_addi_i64(addr, cpu_reg_sp(s, rn), imm + i); - tcg_gen_qemu_ld_i64(t0, addr, midx, MO_LEQ); - tcg_gen_st_i64(t0, cpu_env, vofs + i); - } - } else { - TCGLabel *loop =3D gen_new_label(); - TCGv_ptr tp, i =3D tcg_const_local_ptr(0); + /* Limit tcg code expansion by doing large loads out of line. */ + if (nparts > 4) { + TCGv_ptr t_rd =3D tcg_temp_new_ptr(); + TCGv_i32 t_len =3D tcg_const_i32(len); =20 - gen_set_label(loop); - - /* Minimize the number of local temps that must be re-read from - * the stack each iteration. Instead, re-compute values other - * than the loop counter. - */ - tp =3D tcg_temp_new_ptr(); - tcg_gen_addi_ptr(tp, i, imm); - tcg_gen_extu_ptr_i64(addr, tp); - tcg_gen_add_i64(addr, addr, cpu_reg_sp(s, rn)); - - tcg_gen_qemu_ld_i64(t0, addr, midx, MO_LEQ); - - tcg_gen_add_ptr(tp, cpu_env, i); - tcg_gen_addi_ptr(i, i, 8); - tcg_gen_st_i64(t0, tp, vofs); - tcg_temp_free_ptr(tp); - - tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop); - tcg_temp_free_ptr(i); + tcg_gen_addi_ptr(t_rd, cpu_env, vofs); + gen_helper_sve_ldr(cpu_env, t_rd, clean_addr, t_len); + tcg_temp_free_ptr(t_rd); + tcg_temp_free_i32(t_len); + return; } =20 - /* Predicate register loads can be any multiple of 2. - * Note that we still store the entire 64-bit unit into cpu_env. + t0 =3D tcg_temp_new_i64(); + for (i =3D 0; i < len_align; i +=3D 8) { + tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEQ); + tcg_gen_st_i64(t0, cpu_env, vofs + i); + tcg_gen_addi_i64(clean_addr, clean_addr, 8); + } + + /* + * Predicate register loads can be any multiple of 2. + * Note that we still store the entire 64-bit unit into cpu_env + * so that the high bits are zeroed. */ if (len_remain) { - tcg_gen_addi_i64(addr, cpu_reg_sp(s, rn), imm + len_align); - switch (len_remain) { case 2: - case 4: - case 8: - tcg_gen_qemu_ld_i64(t0, addr, midx, MO_LE | ctz32(len_remain)); + tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEUW); + break; + case 4: + tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEUL); break; - case 6: t1 =3D tcg_temp_new_i64(); - tcg_gen_qemu_ld_i64(t0, addr, midx, MO_LEUL); - tcg_gen_addi_i64(addr, addr, 4); - tcg_gen_qemu_ld_i64(t1, addr, midx, MO_LEUW); + tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEUL); + tcg_gen_addi_i64(clean_addr, clean_addr, 4); + tcg_gen_qemu_ld_i64(t1, clean_addr, midx, MO_LEUW); tcg_gen_deposit_i64(t0, t0, t1, 32, 32); tcg_temp_free_i64(t1); break; - default: g_assert_not_reached(); } tcg_gen_st_i64(t0, cpu_env, vofs + len_align); } - tcg_temp_free_i64(addr); tcg_temp_free_i64(t0); } =20 --=20 2.20.1