From nobody Tue Sep 23 21:38:22 2025 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1584042602; cv=none; d=zohomail.com; s=zohoarc; b=et6DrNR343xWcx4P3bISCdjXvUAe/wOJCS+Zu49Meya01SNfPmH2h8vglZSApUlTu7jp69asUKWcyFFLqw51aitlEpOBHW1h+up0hTOVqZkWT9tzkI1kmUTAvyCFok3L2LThHUScm73AzKjJ24oyHjhhHOfFr3MFN9C3m/fUvkw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1584042602; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PFt+v48W7QA8GvHg/8rhS6cw302F8aQHkOa+rEb7BHc=; b=ig0HRKUL6ocK4KacuMooyXoNq9vgKhM/J/mqS7OZnAvqwT2bxftK5VzE582L+NJiX5bI0eVUs+ydyzBplHDFBiYRGIQxLtpyMCZQ9kNlQmfqrQacZlVWiaw/IJQksPzuIcl/X86WwUsveJTakOPjw9YPwORJzOfyh2DBdXAJmuA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) header.from= Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1584042602015473.9435842645371; Thu, 12 Mar 2020 12:50:02 -0700 (PDT) Received: from localhost ([::1]:49350 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jCTqC-0000NG-OM for importer@patchew.org; Thu, 12 Mar 2020 15:50:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:45621) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1jCTjL-0005oW-GN for qemu-devel@nongnu.org; Thu, 12 Mar 2020 15:42:57 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1jCTjJ-0002Cf-L0 for qemu-devel@nongnu.org; Thu, 12 Mar 2020 15:42:55 -0400 Received: from mail-pg1-x542.google.com ([2607:f8b0:4864:20::542]:35432) by eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16) (Exim 4.71) (envelope-from ) id 1jCTjJ-0002C6-En for qemu-devel@nongnu.org; Thu, 12 Mar 2020 15:42:53 -0400 Received: by mail-pg1-x542.google.com with SMTP id 7so3575614pgr.2 for ; Thu, 12 Mar 2020 12:42:53 -0700 (PDT) Received: from localhost.localdomain (97-126-123-70.tukw.qwest.net. [97.126.123.70]) by smtp.gmail.com with ESMTPSA id g69sm6824842pje.34.2020.03.12.12.42.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Mar 2020 12:42:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PFt+v48W7QA8GvHg/8rhS6cw302F8aQHkOa+rEb7BHc=; b=hLobWc0VI6Hy5e0m6wO/MuAFzcmzEocDmoibUTpv7yQF/RFv2RCrBur5URLhQpZeqi LDSXMh2s7dbtik22q8gtaK50eL64AfernpNhyOg6PauiYtHqmHtaShGZ/z0IpM68VpOp CpB6UaP9WlFoNto/gLDtdYPDWz+Iw+nImQNgXn7WO3TszMnNdijF/tGr9375gmA8Bq4v kYbG6T+mUUw/IRO7oLnvVXqSmAxm0yc3kFf1dFMouywA3Hi1jIKs9M43ZgSJ3lY4Y728 AyMMtWZKNISfH9mr1/eCwyXJvEZCEb1y1JoAEh1wqvy9nBqihOq5wHzSON2CAh7RAuKG /sEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PFt+v48W7QA8GvHg/8rhS6cw302F8aQHkOa+rEb7BHc=; b=aMl3IK+oQ5a9DREZB4iVkwkt7MjPfopM5rZ5oYn9UfE9D9GhZmq6EP8rgwgG8GKDdJ RAH28iJSq9ALHT4JbjAqwgm3EUkAKEUNRUy3C9RylfT/FJMaNWVk5bpSRbaYBDk3lc38 D5gUvu3ZaljzWPiW4TiuWYqjPEn/ANH9LaTYUK9+J4JdYO4KzW7h2qtyHDdonUAktPQi kHVP2LHP0n097un3b9OL5RR5afZXcLJpCMqUxYfyivGb2Ky/DhdZyWAuftZMXuNxAe7A FKrnHrnPr5cwfLNFXpIBx2zFRqqJHnYtAW31My+JDNr0EURqa+I1guJWFzKOdKGdfTrV cmcQ== X-Gm-Message-State: ANhLgQ3UqldM4dL5CfLNp0Nb/yP+zVOhbluEY+u0gxthtfJ99LsUfxSE 3jeCrxBXHdAH+Z4UNKTo+HhTMhkrL5s= X-Google-Smtp-Source: ADFU+vtiX2cwiWDlrjTjNrZo/+EpXNuE3s5j53IjZvwAhVflgzT3kTjO/5io5vZROfb0mvEqGSjMgQ== X-Received: by 2002:a63:8342:: with SMTP id h63mr9516183pge.141.1584042171925; Thu, 12 Mar 2020 12:42:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v6 23/42] target/arm: Add gen_mte_check1 Date: Thu, 12 Mar 2020 12:42:00 -0700 Message-Id: <20200312194219.24406-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.20.1 In-Reply-To: <20200312194219.24406-1-richard.henderson@linaro.org> References: <20200312194219.24406-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: Genre and OS details not recognized. X-Received-From: 2607:f8b0:4864:20::542 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, qemu-arm@nongnu.org, alex.bennee@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) Content-Type: text/plain; charset="utf-8" Replace existing uses of check_data_tbi in translate-a64.c that perform a single logical memory access. Leave the helper blank for now to reduce the patch size. Signed-off-by: Richard Henderson --- target/arm/helper-a64.h | 1 + target/arm/internals.h | 8 ++++ target/arm/translate-a64.h | 2 + target/arm/mte_helper.c | 8 ++++ target/arm/translate-a64.c | 96 ++++++++++++++++++++++++++++---------- 5 files changed, 91 insertions(+), 24 deletions(-) diff --git a/target/arm/helper-a64.h b/target/arm/helper-a64.h index 7b628d100e..2faa49d0a3 100644 --- a/target/arm/helper-a64.h +++ b/target/arm/helper-a64.h @@ -104,6 +104,7 @@ DEF_HELPER_FLAGS_3(autdb, TCG_CALL_NO_WG, i64, env, i64= , i64) DEF_HELPER_FLAGS_2(xpaci, TCG_CALL_NO_RWG_SE, i64, env, i64) DEF_HELPER_FLAGS_2(xpacd, TCG_CALL_NO_RWG_SE, i64, env, i64) =20 +DEF_HELPER_FLAGS_3(mte_check1, TCG_CALL_NO_WG, i64, env, i32, i64) DEF_HELPER_FLAGS_3(irg, TCG_CALL_NO_RWG, i64, env, i64, i64) DEF_HELPER_FLAGS_4(addsubg, TCG_CALL_NO_RWG_SE, i64, env, i64, s32, i32) DEF_HELPER_FLAGS_3(ldg, TCG_CALL_NO_WG, i64, env, i64, i64) diff --git a/target/arm/internals.h b/target/arm/internals.h index 56fb07f2b6..a993e8ca0a 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1306,6 +1306,14 @@ void arm_log_exception(int idx); #define LOG2_TAG_GRANULE 4 #define TAG_GRANULE (1 << LOG2_TAG_GRANULE) =20 +/* Bits within a descriptor passed to the helper_mte_check* functions. */ +FIELD(MTEDESC, MIDX, 0, 4) +FIELD(MTEDESC, TBI, 4, 2) +FIELD(MTEDESC, TCMA, 6, 2) +FIELD(MTEDESC, WRITE, 8, 1) +FIELD(MTEDESC, ESIZE, 9, 5) +FIELD(MTEDESC, TSIZE, 14, 10) /* mte_checkN only */ + static inline int allocation_tag_from_addr(uint64_t ptr) { return extract64(ptr, 56, 4); diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index 4c2c91ae1b..cc77e6ce8b 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -40,6 +40,8 @@ TCGv_ptr get_fpstatus_ptr(bool); bool logic_imm_decode_wmask(uint64_t *result, unsigned int immn, unsigned int imms, unsigned int immr); bool sve_access_check(DisasContext *s); +TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, + bool tag_checked, int log2_size); =20 /* We should have at some point before trying to access an FP register * done the necessary access check, so assert that diff --git a/target/arm/mte_helper.c b/target/arm/mte_helper.c index 27d4b4536c..ec12768dfc 100644 --- a/target/arm/mte_helper.c +++ b/target/arm/mte_helper.c @@ -358,3 +358,11 @@ void HELPER(stzgm_tags)(CPUARMState *env, uint64_t ptr= , uint64_t val) memset(mem, tag_pair, tag_bytes); } } + +/* + * Perform an MTE checked access for a single logical or atomic access. + */ +uint64_t HELPER(mte_check1)(CPUARMState *env, uint32_t desc, uint64_t ptr) +{ + return ptr; +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index f010aa2b58..683a8a3dba 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -221,20 +221,20 @@ static void gen_a64_set_pc(DisasContext *s, TCGv_i64 = src) } =20 /* - * Return a "clean" address for ADDR according to TBID. - * This is always a fresh temporary, as we need to be able to - * increment this independently of a dirty write-back address. + * Handle MTE and/or TBI. + * + * For TBI, ideally, we would do nothing. Proper behaviour on fault is + * for the tag to be present in the FAR_ELx register. But for user-only + * mode, we do not have a TLB with which to implement this, so we must + * remote the top byte now. + * + * Always return a fresh temporary that we can increment independently + * of the write-back address. */ + static TCGv_i64 clean_data_tbi(DisasContext *s, TCGv_i64 addr) { TCGv_i64 clean =3D new_tmp_a64(s); - /* - * In order to get the correct value in the FAR_ELx register, - * we must present the memory subsystem with the "dirty" address - * including the TBI. In system mode we can make this work via - * the TLB, dropping the TBI during translation. But for user-only - * mode we don't have that option, and must remove the top byte now. - */ #ifdef CONFIG_USER_ONLY gen_top_byte_ignore(s, clean, addr, s->tbid); #else @@ -262,6 +262,45 @@ static void gen_probe_access(DisasContext *s, TCGv_i64= ptr, tcg_temp_free_i32(t_size); } =20 +/* + * For MTE, check a single logical or atomic access. This probes a single + * address, the exact one specified. The size and alignment of the access + * is not relevant to MTE, per se, but watchpoints do require the size, + * and we want to recognize those before making any other changes to state. + */ +static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, TCGv_i64 addr, + bool is_write, bool tag_checked, + int log2_size, bool is_unpriv, + int core_idx) +{ + if (tag_checked && s->mte_active[is_unpriv]) { + TCGv_i32 tcg_desc; + TCGv_i64 ret; + int desc =3D 0; + + desc =3D FIELD_DP32(desc, MTEDESC, MIDX, core_idx); + desc =3D FIELD_DP32(desc, MTEDESC, TBI, s->tbid); + desc =3D FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); + desc =3D FIELD_DP32(desc, MTEDESC, WRITE, is_write); + desc =3D FIELD_DP32(desc, MTEDESC, ESIZE, 1 << log2_size); + tcg_desc =3D tcg_const_i32(desc); + + ret =3D new_tmp_a64(s); + gen_helper_mte_check1(ret, cpu_env, tcg_desc, addr); + tcg_temp_free_i32(tcg_desc); + + return ret; + } + return clean_data_tbi(s, addr); +} + +TCGv_i64 gen_mte_check1(DisasContext *s, TCGv_i64 addr, bool is_write, + bool tag_checked, int log2_size) +{ + return gen_mte_check1_mmuidx(s, addr, is_write, tag_checked, log2_size, + false, get_mem_index(s)); +} + typedef struct DisasCompare64 { TCGCond cond; TCGv_i64 value; @@ -2412,7 +2451,7 @@ static void gen_compare_and_swap(DisasContext *s, int= rs, int rt, if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn !=3D 31, = size); tcg_gen_atomic_cmpxchg_i64(tcg_rs, clean_addr, tcg_rs, tcg_rt, memidx, size | MO_ALIGN | s->be_data); } @@ -2430,7 +2469,9 @@ static void gen_compare_and_swap_pair(DisasContext *s= , int rs, int rt, if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + + /* This is a single atomic access, despite the "pair". */ + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn !=3D 31, = size + 1); =20 if (size =3D=3D 2) { TCGv_i64 cmp =3D tcg_temp_new_i64(); @@ -2555,7 +2596,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn !=3D = 31, size); gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, false); return; =20 @@ -2564,7 +2605,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), false, rn !=3D= 31, size); s->is_ldex =3D true; gen_load_exclusive(s, rt, rt2, clean_addr, size, false); if (is_lasr) { @@ -2584,7 +2625,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) gen_check_sp_alignment(s); } tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), true, rn !=3D = 31, size); do_gpr_st(s, cpu_reg(s, rt), clean_addr, size, true, rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); return; @@ -2600,7 +2641,7 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), false, rn !=3D= 31, size); do_gpr_ld(s, cpu_reg(s, rt), clean_addr, size, false, false, true,= rt, disas_ldst_compute_iss_sf(size, false, 0), is_lasr); tcg_gen_mb(TCG_MO_ALL | TCG_BAR_LDAQ); @@ -2614,7 +2655,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (is_lasr) { tcg_gen_mb(TCG_MO_ALL | TCG_BAR_STRL); } - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), + true, rn !=3D 31, size); gen_store_exclusive(s, rs, rt, rt2, clean_addr, size, true); return; } @@ -2632,7 +2674,8 @@ static void disas_ldst_excl(DisasContext *s, uint32_t= insn) if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), + false, rn !=3D 31, size); s->is_ldex =3D true; gen_load_exclusive(s, rt, rt2, clean_addr, size, true); if (is_lasr) { @@ -2926,6 +2969,7 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, bool iss_valid =3D !is_vector; bool post_index; bool writeback; + int memidx; =20 TCGv_i64 clean_addr, dirty_addr; =20 @@ -2983,7 +3027,11 @@ static void disas_ldst_reg_imm9(DisasContext *s, uin= t32_t insn, if (!post_index) { tcg_gen_addi_i64(dirty_addr, dirty_addr, imm9); } - clean_addr =3D clean_data_tbi(s, dirty_addr); + + memidx =3D is_unpriv ? get_a64_user_mem_index(s) : get_mem_index(s); + clean_addr =3D gen_mte_check1_mmuidx(s, dirty_addr, is_store, + writeback || rn !=3D 31, + size, is_unpriv, memidx); =20 if (is_vector) { if (is_store) { @@ -2993,7 +3041,6 @@ static void disas_ldst_reg_imm9(DisasContext *s, uint= 32_t insn, } } else { TCGv_i64 tcg_rt =3D cpu_reg(s, rt); - int memidx =3D is_unpriv ? get_a64_user_mem_index(s) : get_mem_ind= ex(s); bool iss_sf =3D disas_ldst_compute_iss_sf(size, is_signed, opc); =20 if (is_store) { @@ -3090,7 +3137,7 @@ static void disas_ldst_reg_roffset(DisasContext *s, u= int32_t insn, ext_and_shift_reg(tcg_rm, tcg_rm, opt, shift ? size : 0); =20 tcg_gen_add_i64(dirty_addr, dirty_addr, tcg_rm); - clean_addr =3D clean_data_tbi(s, dirty_addr); + clean_addr =3D gen_mte_check1(s, dirty_addr, is_store, true, size); =20 if (is_vector) { if (is_store) { @@ -3175,7 +3222,7 @@ static void disas_ldst_reg_unsigned_imm(DisasContext = *s, uint32_t insn, dirty_addr =3D read_cpu_reg_sp(s, rn, 1); offset =3D imm12 << size; tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); - clean_addr =3D clean_data_tbi(s, dirty_addr); + clean_addr =3D gen_mte_check1(s, dirty_addr, is_store, rn !=3D 31, siz= e); =20 if (is_vector) { if (is_store) { @@ -3268,7 +3315,7 @@ static void disas_ldst_atomic(DisasContext *s, uint32= _t insn, if (rn =3D=3D 31) { gen_check_sp_alignment(s); } - clean_addr =3D clean_data_tbi(s, cpu_reg_sp(s, rn)); + clean_addr =3D gen_mte_check1(s, cpu_reg_sp(s, rn), false, rn !=3D 31,= size); =20 if (o3_opc =3D=3D 014) { /* @@ -3345,7 +3392,8 @@ static void disas_ldst_pac(DisasContext *s, uint32_t = insn, tcg_gen_addi_i64(dirty_addr, dirty_addr, offset); =20 /* Note that "clean" and "dirty" here refer to TBI not PAC. */ - clean_addr =3D clean_data_tbi(s, dirty_addr); + clean_addr =3D gen_mte_check1(s, dirty_addr, false, + is_wback || rn !=3D 31, size); =20 tcg_rt =3D cpu_reg(s, rt); do_gpr_ld(s, tcg_rt, clean_addr, size, /* is_signed */ false, --=20 2.20.1